ENEE 313, Fall ’08
Supplement IV
An Example Problem on the NMOS
and A PMOS Introduction
Zeynep Dilli, Dec. 2008
This is a supplement presenting an example question on MOSFET operation and reviews the MOSFET
concepts during the solution. Later three sections summarize, once again, the band-energy diagrams of an
NMOS under different bias conditions, then present the structure of a PMOS and give summaries of its
band-energy diagrams under different bias conditions and its IV curve.
1
Device Structure
An n-channel silicon MOSFET (NMOS) has the following construction: The p-type substrate doping is
NA = 5 × 1016 1/cm3 . The n-type polysilicon gate is doped at ND = 1019 1/cm3 . The gate length is
0.5 µm. The oxide thickness tox =20 nm. The device width is 20 µm. The source and drain are doped
degenerately (very highly) at ND = 1020 cm. The source and drain regions are each 1 µm wide and 0.25
µm deep. The p-type bulk (substrate) is 100 µm deep.
Relevant constants: Silicon dioxide and silicon permittivities are ox = 3.9 × 8.9 × 10−14 F/cm and
Si = 11.7 × 8.9 × 10−14 F/cm. ni = 1.45 × 1010 1/cm3 . µn = 500 cm2 /V.sec. 1 nm=0.001 µm. Assume
room temperature, so that kT /q=0.026 V.
2
Device Analysis
Question: Sketch the two-dimensional cross-section of this device. The thickness/depth
dimension does not have to be to scale.
Answer:
Question: Draw the band diagram with no bias applied to the substrate. Then calculate
the threshold voltage Vthr under that condition.
The gate is not metal, but polysilicon, so instead of the work function of a metal ΦM we have to use the
work function of the polysilicon gate while aligning the Fermi levels of the polysilicon and silicon along with
the vacuum energy level. Let’s denote the work function of the polysilicon gate with Φpoly and that of the
silicon substrate with ΦSi . Polysilicon and silicon both have the same electron affinity, χSi = E0 − EC,Si
where E0 is the vacuum energy level, and the same bandgap, Eg,Si . So when separate, the band energy
diagrams of our gate and body materials will look as in Figure 2:
As can be seen from the figure, when the materials are put together, and at equilibrium the Fermi
levels align, the work function difference ΦSi − Φpoly will cause band-bending. Here is the situation shown
in Figure 3, with the oxide layer in the polysilicon/oxide/silicon system inserted:
To find the threshold voltage, we need to use the expression
Vthr = Vox + 2|φb | + VF B ;
(1)
where Vox is the potential drop across the oxide (which charges up the depletion region capacitance), φb is
the “body potential” (more about it later) and thus 2|φb | is the potential needed to draw enough electrons
1
Figure 1: The NMOS device described in this supplement.
Figure 2: Band energy diagrams for the n-type polysilicon (“metal”) gate and the p-type silicon body.
Figure 3: Band diagram of the MOS system formed by the polysilicon and silicon as described in the text
and the oxide layer of thickness tox in between.
to the surface of this p-type substrate to “invert” it, and VF B is the “calibration” factor of the flat-band
voltage. We’ll start by calculating VF B .
2
As can be tracked from Figure 3, the total band-bending is |ΦSi − Φpoly | = (χSi + Eg /2 + (Ei,Si − EF )) −
(χSi + Eg /2 − (EF − Ei,poly ) = (Ei,Si − EF ) + (EF − Ei,poly ). Or, if we write the “body potential” of the
silicon substrate far from the interface as |φb | = |(Ei,Si − EF )/q| and the potential of the n-type polysilicon
gate as |φn | = |(Ei,Si − EF )/q|, we can write the magnitude of the total band-bending in units of energy
as q(φb + φn ). So the magnitude of VF B , the potential that should be applied between the “metal” (here
polysilicon) gate and the silicon substrate to cancel the band-bending, is φb + φn .
By definition, the flat-band potential is measured as applied between the gate and the substrate (body):
VF B = VG − VB , where VB is any potential applied to the body. Here, looking at the band energy diagram,
obviously we need to “raise” the gate side to create the flat-band condition. Therefore, the potential
applied between the gate and the substrate needs to be negative (i.e. the gate put to a more negative
potential than the substrate). Then, for this problem
NA,body
ND,poly
kT
kT
ln (
)+
ln (
))
q
ni
q
ni
5 × 1019
5 × 1019
)
+
ln
(
)) = −0.026 ∗ (15.05 + 20.35) = −0.94 V.
= −0.026(ln (
1.45 × 1010
1.45 × 1010
VF B = −(φb + φn ) = −(
When this potential is applied between the gate and the body, the material reaches flat-band condition,
as in Figure 4:
Figure 4: The MOS system described here at flat band condition. Note that the Fermi level in the
polysilicon (“metal”) gate is higher than that in the silicon body now. To achieve this, a negative potential
needs to be applied between the gate and the body.
As for the other terms in the threshold voltage expression, Vox , the potential drop across the oxide, is
given by
q
tox
Vox =
2qNA,Si 2|φb |Si
ox
20 × 10−7 cm p
=
4 × 1.6 × 10−19 × 5 × 1016 × 0.3914 × 1.035 × 10−12 = 0.66 V.
3.45 × 10−13 F/cm
Once again, this is the potential required, starting from the flatband condition, to create a depletion
region under the gate oxide where the holes have been pushed away, so that although the substrate
material is p-type, there are not many holes near the surface any more. Then there is the extra potential
required to draw enough electrons to the surface and create the inversion layer, which is 2|φb | = 2 ∗
Vthermal ln(NA,substrate /ni ) = 2 ∗ 0.026 ∗ 15.05 = 2 ∗ 0.39 = 0.78 V at the onset of strong inversion by
definition. Then the threshold voltage for this n-channel MOSFET is
Vthr = Vox + 2|φb | + VF B = 0.66 + 0.78 − 0.92 = 0.52 V.
3
(2)
Note that the initial doping levels of the polysilicon gate and silicon body happened to set a situation
very close to surface depletion already (as could be seen in Figure 2). So in this case, the flatband voltage
actually works to bring the threshold voltage down. At different doping levels, the situation would be
different.
The band diagram at the onset of strong inversion is as in Figure 5.
Figure 5: The described MOS system at strong inversion. The gate is at a higher potential than the
substrate, as shown by the lower Fermi level at the gate. At this potential level, Vthr , the magnitude of the
surface potential |φs | is equal to the magnitude of the body potential |φb ; in other words, the total band
bending in the silicon is 2|φb |, which is the origin of that term in the threshold voltage expression Eqn. 1.
Question: What happens if the body is not grounded initially, but held at a voltage VB ?
The effect of a body voltage is to change the depletion region growth as a potential is applied to the
gate. Therefore, it changes the Vox component of the threshold voltage as follows:
Vox =
tox
ox
q
2qNA,Si 2|(φb − VB )|Si
(3)
So for instance, if the body voltage is set at -1 V for this transistor, the new threshold voltage would
be
Vthr = Vox + 2|φb | + VF B
20 × 10−7 cm p
=
4 × 1.6 × 10−19 × 5 × 1016 × (0.3914 − (−1)) × 1.035 × 10−12 + 0.78 − 0.92
3.45 × 10−13 F/cm
= 1.24 + 0.78 − 0.92 = 1.1 V
In normal digital operation, we typically ground the p-type body of the NMOS transistors and connect
the n-type body of PMOS transistors to the highest potential in the circuit. But during integrated circuit
operation, stray currents in the common substrate shared by all transistors can create differing potential
levels for different transistors’ substrates, and as shown above, this can cause transistors that should have
been identical to have different threshold voltages and thus different operating characteristics. This body
effect (or substrate bias effect) is then unwanted.
4
Question: What is the operation region of this MOSFET for this MOSFET at the following bias conditions, and what is the drain current? Assume the body potential is 0.
1. VDS =0.5 V, VGS =2.0 V
2. VDS =3.0 V, VGS =2.0 V
3. VDS =0.5 V, VGS =3.0 V
4. VDS =3.0 V, VGS =3.0 V
5. VDS =0.5 V, VGS =4.0 V
6. VDS =3.0 V, VGS =4.0 V
First, for all these cases VGS > Vthr , so the transistor is not in cut-off: It’s either in linear (triode) region
or saturation region of operation. To see which, we compare the drain-source voltage VDS to VGS − Vthr :
How much the gate potential is exceeding the threshold voltage. As the body potential is set to be zero,
we will use the first threshold voltage we calculated:
In cases 1. and 2.: VGS − Vthr = 2 − 0.52 = 1.48 V. Then for case 1, VDS = 0.5 V < VGS − Vthr , and
the transistor is in the linear region. Then the drain-source current is given by
0
IDS,lin = µn Cox
V2
W
[(VGS − Vthr )VDS − DS ]
L
2
(4)
0 is the oxide capacitance of this transistor per unit area:
Here, Cox
0
Cox
=
ox
tox
(5)
Then for our particular transistor, with the given width (W = 1 µm) and length (L = 0.5 µm) in the
device description, the drain-source current in the linear region with VGS = 2.0 V and VDS = 0.5 V will be
IDS = 500
3.54 × 10−13 20
0.52
[(2
−
0.52)0.5
−
] = 2.1 × 10−3 A
20 × 10−7 0.5
2
For case 2, VDS = 3.0 V > VGS − Vthr , so the transistor is in the saturation region. Then, ignoring
channel-length modulation, the drain-source current is given by
0
IDS,sat = µn Cox
W
(VGS − Vthr )2
2L
(6)
and for our particular transistor, the drain-source current in the saturation region with VGS = 2.0 V
and VDS = 0.5 V will be
IDS = 500
3.54 × 10−13 20
(2 − 0.52)2 = 3.8 × 10−3 A.
20 × 10−7 2 × 0.5
Similarly, in case 3 the transistor is in linear region, case 4, saturation region, case 5, linear region. In
case 6, note that the transistor is still in linear region: VDS = 3.0 V < VGS − Vthr = 4.0 − 0.52 V.
The IV curves for this transistor for the three gate biases are given in Figure 6.
5
Figure 6: IV curves for this NMOS.
Question: If the transistor has a channel-length modulation parameter λ = 0.01 V−1 , what
does this change in the IV curves?
A non-zero channel-length modulation parameter changes the saturation region current:
0
IDS,sat = µn Cox
W
(VGS − Vthr )2 (1 + λVDS )
2L
(7)
This is the result of the effective channel length actually changing with VDS . The effect on the IV curve
at saturation is shown in Figure 7 for VGS = 2 V.
Question: What about the cut-off region of operation?
The transistor is in cut-off when VGS < Vthr ; in this case, when gate-to-source bias is lower than 0.52
V. In that case, we call the transistor to be in the sub-threshold regime. Remember that the threshold
point is defined at the onset of strong inversion, that is, the surface potential φs is equal in magnitude to
the body potential φb . But the intrinsic Fermi level at the surface rises above the Fermi level at the surface
at lower applied gate-to-source potentials than that. The MOSFET is then in weak inversion, with some
electrons having been drawn to the surface to form a lightly-populated channel. There is still some (small)
current flowing.
6
Figure 7: IV curves for this NMOS with channel-length modulation considered.
7
3
NMOS Band-Energy Diagrams
Here is a summary table of the situation in an NMOS for no bias, flat-band, accumulation, depletion,
weak inversion, and onset of strong inversion. As described in the sections above, the no-bias situation is
set by the doping levels of the polysilicon gate and the silicon substrate (by the difference of their work
functions). The rest follows.
Band-energy diagram
Condition and notes
No bias.
Band-bending is set by ΦSi and Φpoly difference.
Flat-band condition.
Requires applying a negative potential to
gate with respect to the body.
Accumulation condition.
The substrate is p-type. Holes are the
majority. Accumulation is defined where
there is an even higher density of majority carriers “accumulated” at the surface
than there are in the body. The figure
shows this is the case—Fermi level is farther from intrinsic Fermi level near the
substrate surface.
Requires applying an higher negative potential to the gate with respect to the
body than the case for flat-band condition.
8
Depletion.
Requires applying a small positive potential to the gate with respect to the
body. The positively-charged holes are
being pushed away from the surface
under the effect of this gate potential
and a depletion region, with exposed
negatively-charged acceptor ions, is being formed under the gate.
Weak inversion.
Requires applying a higher positive potential to the gate with respect to the
body. When electron-hole pairs are generated in the depletion region near the
surface, now the electric-field created by
the gate potential is separating them before they can recombine and pulling the
negatively-charged electrons to the surface. Ei has crossed EF and the surface
looks like weakly n-type now.
Onset of strong inversion.
By definition, this happens at the potential level where Ei and EF are separated
as much in the surface as they are deep
in the substrate, but in the opposite way.
In other words, the surface looks as much
n-type as the deep substrate is p-type.
Requires applying a high positive potential to the gate with respect to the body.
4
The PMOS
The p-channel MOSFET, or the PMOS, is the complementary device to the NMOS. All its regions have
the opposite doping to their NMOS counterparts. A sketch of the PMOS is given in Figure 4.
For this device to have a conductive channel between the source and the drain, first the majority
electrons of the n-type substrate must be depleted from under the gate, then an inversion layer must be
formed by holes being drawn to the surface. This requires applying a negative potential to the gate with
respect to the source to turn on the PMOS. In other words, the PMOS threshold voltage is negative.
Another way to think about it is to consider the PMOS threshold voltage positive, but measure the biase
from the source to the gate instead of the other way around, and write VSG > Vthr for the boundary-of-cutoff
condition.
9
Figure 8: A p-channel MOSFET, or a PMOS.
Below, we summarize the band-energy diagram of a PMOS under no bias, then demonstrate the
accumulation and strong inversion conditions. Instead of a polysilicon gate, this PMOS is shown to have
a metal gate. All the calculations for the polysilicon gate still apply, using the workfunction of the metal
instead of the workfunction of the polysilicon.
Band-energy diagram
Condition and notes
No bias.
Band-bending is set by ΦSi and Φmetal
difference.
10
Accumulation condition.
Requires applying a positive potential to
gate with respect to the body.
Onset of strong inversion.
The substrate is n-type. Electrons are
the majority. At this potential condition, the surface looks as much p-type as
the deep substrate is n-type.
Requires applying a high negative potential to the gate with respect to the body.
11