Quad Output Switching Converter Provides Power
for Large TFT LCD Panels – Design Note 349
Dongyan Zhou
All four regulators are synchronized to a 1.2MHz internal
clock, allowing the use of small, low cost inductors and
ceramic capacitors. Since different types of panels may
require different bias voltages, all output voltages are
adjustable for maximum flexibility. Programmable softstart capability is included in all outputs to limit inrush
current. The LT1943 has a built-in start-up sequence
and panel protection feature. The LT1943 is available
in a low-profile 28-pin TSSOP package.
Introduction
The LT®1943 is a highly integrated, 4-output regulator
designed to power large TFT LCD panels. The LT1943
employs switching regulators—instead of linear regulators—to minimize power dissipation and accommodate
a wide input voltage range. The wide input range, 4.5V
to 22V, allows it to accept a variety of power sources,
including the commonly used 5V, 12V and 19V AC adaptors. The first buck regulator provides a logic voltage
with up to 2A of current. The other three switching
regulators provide the three bias voltages, AVDD, VON
and VOFF, required by LCDs.
VOFF
–10V
50mA
ZHCS400 0.47μF
2.2μF
10V
VIN
4.5V TO 8V
L3
10μH
L2
4.7μH
10μF
10V
ZHCS400
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6.8μH
80.6k
VIN
SW4
SW2
FB2
RUN-SS
10pF
VLOGIC
3.3V
1.5A
16.5k
0.22μF
L1
4.7μH
AVDD
13V
500mA
0.047μF
VON
30V
20mA
E3
232k
SW1
B230A
FB3
VC1
10.0k
VC2
10.0k
GND
SGND
VC4
FB1
22μF
6.3V
0.015μF
PGOOD
VON
LT1943
BOOST
Si2343DS
0.015μF
CT
BIAS
100k
10.0k
SS-234
FB4
CMDSH-3
10μF
16V
95.3k
SW3
NFB4
10.0k
B240A
VC3
2.2μF
35V
7.5k
100pF
2.7nF
L1: TDK RLF7030T-4R7M3R4
L2: TDK SLF6028T-4R7M1R6
4.7k
100pF
4.7nF
30k
100pF
1.5nF
13k
100pF
2.2nF
L3: TDK RLF5018T-100MR94
Figure 1. Quad Output TFT LCD Power Supply with 4.5V to 8V Input Voltage Range
10/04/349_conv
0.47μF
35V
DN349 F01
4-Output Supply with Soft-Start
Figure 1 shows a 4-output TFT LCD power supply with
a 4.5V to 8V input range. The first output provides a
3.3V, up to 1.5A, logic supply using a buck regulator. The
second output employs a boost converter to generate a
13V, 500mA AVDD bias supply. Another boost converter
and an inverter generate VON and VOFF.
When power is first applied to the input, the RUN/SS
pin starts charging. When its voltage reaches 0.7V,
switcher 1 is enabled. The capacitor at RUN/SS pin
controls the VLOGIC ramping rate and inrush current in L1.
Switchers 2, 3 and 4 are controlled by the BIAS pin,
which is usually connected to VLOGIC. When the BIAS
pin is higher than 2.8V, the SS-234 pin begins charging
to enable switchers 2, 3 and 4. When AVDD reaches
approximately 90% of its programmed voltage, the
PGOOD pin is pulled low. When AVDD, VOFF and E3 all
reach 90% of their programmed voltages, the CT timer
is enabled and a 20μA current source begins to charge
CT. When the CT pin reaches 1.1V, an output PNP turns
on, enabling VON. Since VON has to be present to turn on
the LCD panel, the VON turn-on delay gives the column
drivers and digital circuitry in the LCD panel time to get
ready, preventing high currents from flowing into the
panel. Figure 2 illustrates the start-up sequencing of
the 4-output power supply in Figure 1. Figure 3 gives
the overall efficiency for the circuit in Figure 1.
If one of the regulated voltages, VLOGIC, AVDD, VOFF or
E3 drops more than 10%, the internal PNP turns off to
shut down VON. This action protects the panel in a fault
condition. The PGOOD pin is used to drive an optional
PMOS device at the output of the AVDD boost regulator
to disconnect AVDD from the input during shutdown.
The converter uses all ceramic capacitors. X5R or
X7R type ceramic capacitors are recommended, as
these materials retain their capacitance over a wide
temperature range.
Wide Input Range Supply
If the input voltage may be higher than the AVDD set
value, a SEPIC regulator can be used in place of a boost
regulator to generate the AVDD output. This covers the
commonly used 12V and 19V inputs. Details for this
are covered in the LT1943 data sheet.
Conclusion
The LT1943 simplifies and shrinks power supplies for
TFT LCD panels. Its four integrated switching regulators
enable a wide input voltage range and reduce power
dissipation. All regulators have a 1.2MHz switching
frequency and allow the exclusive use of ceramic capacitors to minimize circuit size, cost and output ripple.
100
90
EFFICIENCY (%)
RUN-SS
2V/DIV
VLOGIC
5V/DIV
AVDD
10V/DIV
VOFF
10V/DIV
80
70
VE3
20V/DIV
VON
50V/DIV
IIN(AVG)
1A/DIV
60
5ms/DIV
0
300
900
1200
600
LOAD AT VLOGIC (A)
1500
DN349 F02
Figure 2. Start-Up Waveforms of the
Power Supply in Figure 1
Data Sheet Download
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Linear Technology Corporation
DN349 F03
Figure 3. Total Circuit Efficiency of the Power
Supply in Figure 1 (Load at AVDD: 500mA)
For applications help,
call (408) 432-1900
dn349f_conv LT/TP 1004 305K • PRINTED IN THE USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
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