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Contents lists available at ScienceDirect
Electric Power Systems Research
journal homepage: www.elsevier.com/locate/epsr
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H. Iman-Eini a,b , Sh. Farhangi a , J.-L. Schanen b,∗ , M. Khakbazan-Fard c
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A modular power electronic transformer based on a cascaded
H-bridge multilevel converter
School of Electrical and Computer Engineering, University of Tehran, P.O. Box 14395-515, Tehran, Iran
G2ELab, INPG-UJF-CNRS, UMR 5269 ENSIEG, B.P. 46, F-38402 St Martin d’Heres Cedex, Grenoble, France
Iran Power Generation, Distribution and Transmission Management Company, Tehran, Iran
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Article history:
Received 6 February 2008
Received in revised form 22 February 2009
Accepted 21 June 2009
Available online xxx
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In this paper a modular power electronic transformer (PET) for feeding critical loads is presented. The PEbased transformer is a multi-cellular step-down converter that can directly connect to medium voltage
levels on the primary side and provide a low voltage, highly stable interface for consumer applications.
The presented structure consists of three stages: a cascaded H-bridge (CHB) rectifier, an isolation stage,
and an output stage. The CHB rectifier serves as an active rectifier to ensure that the input current is
sinusoidal, and it converts the high AC input voltage to low DC voltages. The isolated DC/DC converters
are then connected to the DC links and provide galvanic isolation between the HV and LV sides. Finally,
a three-phase inverter generates the AC output with the desired amplitude and frequency. This paper
introduces a new control strategy to maintain DC voltage balance among the CHB converter cells, even
if the attached loads are different. The effects of voltage offsets and device mismatches on the equal
load-current sharing are investigated, and an active load-current sharing method is presented to balance
the load power among the parallel-output cells. The validity of the proposed controllers and the PET
performance are verified by simulation and experimental results.
© 2009 Elsevier B.V. All rights reserved.
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1. Introduction
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In recent years, significant advances in power semiconductor
device technology, low-cost, high-speed control processors, and
matured PWM algorithms have led to a number of modern power
converter topologies. A new type of transformer based on power
electronics (PE) has been introduced that realizes voltage transformation, galvanic isolation, and power quality enhancements in a
single device. This PE-based transformer provides a fundamentally
different and more complete approach to transformer design by
using power electronics on the primary and secondary sides of the
transformer. Several integrated PQ features, such as instantaneous
voltage regulation under load dynamics and transients, voltage sag
compensation, power factor correction, and harmonic suppression,
can be incorporated into a PET thanks to the application of power
electronics technology.
For realizing the PET, different topologies have been proposed in
the literature [1–9]. In [1], an AC/AC buck converter was introduced
to transform the voltage level directly and without any isolation
transformer. This method is perhaps the most direct approach to
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Keywords:
Power electronic transformer
Modular converters
Power quality
DC voltage balancing
Active load-current sharing
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∗ Corresponding author. Tel.: +33 476826360; fax: +33 476826300.
E-mail addresses: jean-luc.schanen@g2elab.inpg.fr, h imaneini@yahoo.com
(J.-L. Schanen).
single-phase AC power conversion, but it would cause semiconductor devices to bear very high stress. In [2–4], the concept of a high
frequency (HF) AC link, termed an electronic transformer, was proposed. In this approach, the line side AC waveform is modulated
into a HF square wave coupled to the secondary of the HF transformer, and again is demodulated to its AC form by a synchronous
converter. This method, however, does not provide any benefits in
terms of control or power factor improvement, and may not protect
critical loads from momentary power interruptions due to the lack
of an energy storage system.
Another approach is a three-part design that utilizes an input
stage, an isolation stage, and an output stage, as addressed in [5–8].
This approach enhances the flexibility and functionality of electronic transformers owing to the available DC links. The converter
presented in [5,6] contains a unity power factor active rectifier for
each input stage module and a hard-switched bridge for each isolation stage module and provides only single-directional power flow.
In [7], a topology based on back-to-back diode-clamp multilevel
converters was introduced. This approach can perform different
power quality functions and provide galvanic isolation. However,
modularity and scaling to different voltage and power levels is not
straightforward.
In [8], a classification system for three-part structures was proposed. A description and analysis of the power flow and energy
balance characteristics of multi-cellular converters was also pre-
0378-7796/$ – see front matter © 2009 Elsevier B.V. All rights reserved.
doi:10.1016/j.epsr.2009.06.010
Please cite this article in press as: H. Iman-Eini, et al., A modular power electronic transformer based on a cascaded H-bridge multilevel
converter, Electr. Power Syst. Res. (2009), doi:10.1016/j.epsr.2009.06.010
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2. Power electronic-based transformer with DC link
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Fig. 1 illustrates the basic block diagram of a power electronic
transformer with DC link. The first part, or the input stage, is an
AC/DC converter that is used to shape the input current, to correct
the input power factor, and to regulate the primary DC-link voltage. The isolation stage provides the galvanic isolation between the
primary and secondary sides. The DC voltage is converted to a high
frequency square-wave voltage, coupled to the secondary of the HF
transformer and is rectified to form a secondary DC-link voltage.
On the output side, conventional voltage source inverters or motor
drives (which can be part of the respective load) are connected.
This stage generates the symmetric three-phase voltages with the
desired amplitude and frequency.
In comparison with the electronic transformers that use HF AC
link, such as in [2–4], it is possible to incorporate energy storage
devices to enhance the ride-through capability of PET or to prepare
an integrated interface for distributed resources thanks to available DC links. The power electronic-based transformer with a DC
link prevents voltage or current harmonics from propagating on
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either side of the transformer, even if the input voltage has low
order harmonic content or the load is non-linear. Such a converter
can also provide DC output or variable frequency outputs (e.g., 50,
60, 400 Hz, etc.).
Although PETs are considerably more expensive, as well as less
efficient, than the conventional transformers, considering their
enhanced functionality and flexibility (integrated interface for distributed resources, ability to provide high quality power for selected
customers), the added cost can be easily justified. In [16], a comprehensive comparative analysis was performed for different design
approaches to realize a PET converter. The results showed that
the PET converter with intermediate DC links allows the highest
flexibility and is favorable if power requirements are high and if
bidirectional power flow is of importance. It is likely that this kind
of PET will have a major impact on the utility industry and places
such as aircraft and ships where high quality power conversion is
very desirable [7].
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3. Configuration of PET converter
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Fig. 1. Basic block diagram of the power electronic transformer with DC link.
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In this paper, a modular structure based on the classification
system given in [8] is proposed (Fig. 2). The main AC/DC converter
shown in Fig. 2(a) is composed of “N” H-bridge cells connected in
series on the primary side and “N” DC/DC converters connected in
parallel on the secondary side. The PET structure can also be rearranged to supply different types of electric loads simultaneously.
This capability is shown in Fig. 2(b), where M parallel-output cells
will supply a three-phase voltage source inverter and the remaining
cells will supply individual loads. In this case, the input power fed to
the series H-bridges would be different. Therefore, the CHB rectifier
should maintain voltage balance among the primary DC links and
correct the input power factor. Another challenging issue is related
to the equal load-current sharing among the parallel cells. A very
small mismatch among the parallel cells can cause a large current
deviation among them. This problem, in practice, is intensified by
the non-ideality of parallel cells.
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3.1. Input power stage
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The input stage is a multilevel CHB rectifier, which is particularly
attractive in high voltage applications. This structure is extremely
modular, it has a simple physical layout, and it needs the lowest number of components in comparison with other multilevel
converters. This paper focuses only on the single-phase CHB rectifier. The three-phase structure is obtained by association of three
single-phase CHB converters connected in a star configuration [17].
Furthermore, unidirectional power flow can be realized from the
bidirectional rectifier by turning off the top switches in all H-bridges
or by replacing them with relatively fast diodes (Fig. 2(a)). In this
work, a single-phase bidirectional CHB converter is analyzed, and
the results can be used either in a unidirectional converter or a
three-phase system.
In Fig. 2, there are “N” series-connected H-bridge cells and each
cell can generate three voltage levels on the AC side: 0, +VC and −VC ,
where VC is the desired DC-link voltage. Thus, using “N” H-bridge
cells, a maximum of 2N + 1 different voltage levels are obtained to
synthesize Van (AC terminal voltage):
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sented. In this reference, however, line-frequency switching of the
multi-cellular converter structures was considered and seemed to
be insufficient to meet the control requirements. The principal limiting factor is the low frequency harmonics that are generated when
voltage control is required and the switching strategy is restricted
to achieve power balance.
In [9–11], novel multilevel line side converter sections based on
cascaded H-bridge converters were proposed. These converters can
replace the heavy and bulky line side transformers in electric trains.
In these topologies, a series connection of H-bridge cells is used to
reduce the high input voltage level.
In all multi-cellular structures, the main control issues are the
voltage and power balance among the series-input and paralleloutput converters, respectively. Several references have studied the
DC bus voltage balance problem in CHB converters and proposed
different control strategies using low-frequency modulation techniques, such as in [12,13]. Other references have proposed control
methods to achieve active load-current sharing among the paralleloutput converters [14,15].
The focus of this paper is to realize a MV-to-LV power electronic
transformer as a power delivery component to supply sensitive
loads. In this light, a three-part structure based on cascaded Hbridge rectifiers is presented. The proposed PET would supply
different AC and DC loads simultaneously. Additionally, a new control strategy is introduced to maintain DC voltage balance among
the CHB converter links, even if the series H-bridges have slightly
different characteristics or the attached loads are different. An
active load-current sharing method is also presented to balance
the load power among the parallel-output cells. Analytical formulas are derived to calculate the effects of mismatches on the equal
load-current sharing. The results of this effort, as well as the novel
features of the PET, are verified by simulation and experimental
investigation on a laboratory scale prototype.
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Van =
N
Vhi
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(1)
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(2)
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where Vhi , VCi and hi are the AC terminal voltage, the capacitor
voltage and the switching function of ith H-bridge, respectively.
Applying Kirchhoff’s voltage law (KVL) at the input voltage loop
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i=1
Vhi = hi VCi ,
i = 1, 2, . . . , N
Please cite this article in press as: H. Iman-Eini, et al., A modular power electronic transformer based on a cascaded H-bridge multilevel
converter, Electr. Power Syst. Res. (2009), doi:10.1016/j.epsr.2009.06.010
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Fig. 2. Configuration of PET converter: (a) standard PET converter and (b) rearranged PET converter to feed AC and DC loads.
Please cite this article in press as: H. Iman-Eini, et al., A modular power electronic transformer based on a cascaded H-bridge multilevel
converter, Electr. Power Syst. Res. (2009), doi:10.1016/j.epsr.2009.06.010
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Vin = Van + Lb
dIin
dt
(3)
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where Vin is the input voltage, Iin is the input current, and Lb is the
input inductance which is used to shape the input current. Applying
Kirchhoff’s current law (KCL) for each cell leads to:
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Ihi = hi Iin ,
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i = 1, . . . , N
where Ihi is the output current of ith H-bridge and is a function of
the input current. Eqs. (1)–(4) describe a linear time varying (LTV)
system with one input (Vin ) and N + 1 states (VC1 to VCN and Iin ). The
CHB controller should determine the switching functions, h1 to hN ,
in order to achieve the control goals.
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The second part of the PET structure (Fig. 2) contains the isolated DC/DC converters. These converters are connected to the CHB
converter links and provide a highly stable DC interface on the LV
side. In the above topology, several isolated converters can be paralleled on the LV side to increase the power capacity. However, the
parallel cells should share the load-current equally and uniformly,
in order to achieve identical operating conditions. This fact is also
important from a thermal viewpoint.
In the isolation stage, different kinds of DC/DC converters can
be utilized. Nevertheless, we use a full-bridge converter, which is
the best in terms of efficiency and voltage stress [18]. Among the
full-bridge topologies, the zero voltage switched converter (ZVSFB)
has a better performance than alternative topologies. All switches,
in this topology, are turned on in the ZVS condition, and the turnoff losses are controlled by the parallel capacitors. Furthermore, in
this PET application, we need good voltage isolation between the
HV and LV sides, which corresponds to high leakage inductance.
Therefore it appears more reasonable to use a ZVSFB converter as
opposed to other alternatives that require a low leakage inductance
transformer.
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3.3. Output stage
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The output stage usually contains a single-phase or three-phase
voltage source inverter that is connected to the DC bus and generates the AC output with the desired amplitude and frequency. The
DC bus may also connect directly to a DC load or to a combination
of AC and DC loads, as in Fig. 2(b). Further information about the
voltage source inverters and their controls can be obtained from
[19].
In brief, the strictly modular PET converter shown in Fig. 2 (a)
and (b) has the following features:
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• Well proven and reliable H-bridge converter technology that can
be used immediately.
• No major change of existing production lines is required.
• Scaling to different voltage and power levels is carried out simply
by varying the number of sub-modules.
• Maintenance operation and repair of power converter modules is
rather simple [20].
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4. Proposed control strategy for PET converter
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The power electronic transformer has three stages and each
stage can be controlled independently from the other because the
intermediate DC bus capacitors are large enough to decouple the
operation and control of the power stages.
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4.1. Control of the CHB rectifier
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The main challenges associated with the CHB rectifier control
are shaping the input current, controlling the input power factor,
and keeping the DC-link voltages at the desired reference value. In
rectification mode, the CHB converter aims to achieve N equal DC
voltages across the capacitors (C1 to CN ). However, this can become
difficult if the loads (or converters) attached to the H-bridge cells are
not equal, or the series H-bridges have slightly different characteristics. When implementing very high voltage converters, even the
parasitic stray capacitances to earth can lead to unwanted scaling
effects and lead to unequal voltage distribution among the seriesconnected converters.
In Fig. 3(a), the basic block diagram of the proposed controller is
shown. This block consists of analog and digital controllers. The analog controller generates the pulse width modulated (PWM) signal,
Q, and the digital controller determines the appropriate switching
functions h1 to hN . The digital controller also generates a synchro (ϕ) in Fig. 3(a)} to control both the
nized square-wave signal {Vin
active and reactive powers.
Fig. 3(b) shows the basic block diagram of the analog controller.
This controller is intended to shape the input current and regulate
the total voltage of primary DC links. The controller has two control
loops: the inner current loop and the outer voltage loop. The voltage
loop contains a PI controller to regulate the total voltage of DC buses
to the reference value, i.e., VCi = NVC . In the classical methods, the
output of PI regulator is multiplied by the sample of input voltage to
∗ . In this paper, the digital
generate a sinusoidal reference current, Iin
, from the
controller generates a square-wave alternative signal, Vin
input voltage which is in opposite direction to Vin . The square-wave
signal has the same frequency as the input voltage and its phase, i.e.,
− , is adjusted by the digital controller (see Fig. 3(b)). This signal
is then filtered by a low-pass Butterworth filter and multiplied by
the output of voltage regulator. As the low pass filter introduces
phase lag between square-wave input and sinusoidal output, the
square-wave signal is delayed enough by the digital controller to
cancel the filter phase lag and to control the input power factor.
Using this method, a pure sinusoidal reference is generated, even in
the polluted environments with noise and harmonics. Additionally,
the phase of input current, ϕ, and power factor are controlled, and
the gain of voltage loop becomes independent from the input volt∗ , the inner
age variations. After generating the reference current Iin
current loop programs the input current Iin to follow the reference
signal by PWM control.
The digital controller determines the appropriate switching
functions, h1 to hN , for the series-connected H-bridges. Each switching function hi (i = 1,. . .,N) corresponds to four operating modes: “0”,
“+1”, “−1”, and PWM. The switching functions are determined by
the digital controller and are applied to the H-bridge cells (Fig. 3(c)).
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(4)
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system with (N − 1) converters reconnects to the line (redundant
operation).
• Other renewable energy sources, such as photovoltaic systems
and fuel cells, can be connected to the PET at the secondary DC
links.
• The PET structure can be reconfigured as a unified power flow
controller (UPFC) simply by replacing the last stage with a cascade
H-bridge inverter.
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Other features of the proposed PET are as follows:
• H-bridge cells and the input inductance, Lb , will not need to tolerate voltages greater than VC .
• If a failure occurs in one converter cell, the destructed converter
cell may be short-circuited (e.g., by an external switch) and the
Please cite this article in press as: H. Iman-Eini, et al., A modular power electronic transformer based on a cascaded H-bridge multilevel
converter, Electr. Power Syst. Res. (2009), doi:10.1016/j.epsr.2009.06.010
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Fig. 3. Block diagram of the CHB controller: (a) main controller, (b) analog controller and (c) drive circuit for the ith H-bridge cell.
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g1 = V Q̄ ,
g2 = V Q̄
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g3 = V̄ Q,
g4 = V̄ Q
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The operating mode “0” corresponds to the conduction of bottom
switches (S2 and S4 ). In modes “+1” and “−1” the diagonal switches
(S1 and S4 ) and (S2 and S3 ) are turned on, respectively. In PWM
mode, the gate signals, g1 to g4 , drive the corresponding cell. These
signals are obtained from Q, the output of analog controller, as
follows:
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(5)
(6)
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Region K : (K − 1)VC < Vin < KVC ,
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where V is the sign of input voltage and is one if the input voltage is positive; otherwise it is zero. In bidirectional power flow,
alternating between the conduction of top and bottom switches for
realizing mode “0” would evenly spread switching stress among the
switches.
To take advantage of both low frequency (stepped modulation)
and high frequency (PWM) modulation techniques, we employ the
hybrid modulation method as shown in Fig. 4. In this method, the
input voltage Vin is divided into equal sections with the scale of VC
(VC is the reference of DC-link voltages). Now we define the voltage
region K as follows:
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Region K is the voltage interval that the magnitude of input voltage,
|Vin |, lies between (K − 1)VC and KVC . Note that the minimum number of cells to synthesize the multilevel waveform, Van , is equal to
the closest integer greater than (Vm /VC ), where Vm is the peak input
voltage.
In Fig. 4, Tac is the mains half-cycle, tK and tK correspond to
the change of voltage regions, where Vin = KVC , and tN is equal to
Tac /2. According to Fig. 4, the duration of voltage region K can be
represented by the time intervals (tK−1 , tK ) and (tK , tK−1
) as well.
K = 1, . . . , N
(7)
Fig. 4. Definition of voltage regions for K = 1,. . .,N.
Please cite this article in press as: H. Iman-Eini, et al., A modular power electronic transformer based on a cascaded H-bridge multilevel
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Assuming Vin = Vm sin(ωt), tK and tK are derived as follows:
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tK =
C
Vm
and tK = Tac − tK
(see Fig. 8(b)). The following remarks about this method should be
noted:
(8)
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The digital controller performs the control algorithm to maintain
voltage balance among the primary DC links, while the analog controller regulates the sum of DC-link voltages to NVC . The proposed
control rules, defined hereafter, aim to synthesize the waveform
shown in Fig. 4 and to maintain voltage balance across the DC links.
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1. If Vin > 0, Iin > 0, and the voltage region is K, then (K − 1) cells with
the lowest DC bus voltage are chosen to be charged in mode “+1”,
the Kth cell in PWM mode, and the rest in mode “0”.
2. If Vin > 0, Iin < 0, and the voltage region is K, then (K − 1) cells with
the highest DC bus voltage are chosen to be discharged in mode
“+1”, the Kth cell in PWM mode, and the rest in mode “0”.
3. If Vin < 0, Iin > 0, and the voltage region is K, then (K − 1) cells with
the highest DC bus voltage are chosen to be discharged in mode
“−1”, the Kth cell in PWM mode, and the rest in mode “0”.
4. If Vin < 0, Iin < 0, and the voltage region is K, then (K − 1) cells with
the lowest DC bus voltage are chosen to be charged in mode “−1”,
the Kth cell in PWM mode, and the rest in mode “0”.
To perform the above rules, the digital controller employs the
flowchart shown in Fig. 5. In the flowchart, the vector (V1 , V2 ,. . .,
VN ) is a mapping for the DC-link voltages, sorted in ascending
order. The digital controller takes the voltage and current samples with the sampling frequency fo . Then, the region of input
voltage, K, is updated according to (7), the control algorithm is
performed, and the appropriate switching functions, h1 to hN , are
determined. The switching functions are applied to the H-bridge
cells and the corresponding operating modes are selected by the
multiplexers. This procedure is repeated in the next sampling periods. As a result, the voltage of DC buses is controlled by adjusting
the average current fed to the H-bridge cells, over mains half-cycle
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As an example, assume that N = 3, K = 2, Vin > 0, Iin > 0 and the sort
of DC-link voltages is VC1 ≤ VC3 ≤ VC2 at tx . According to the control
rules, the switching functions are determined as h1 = “+1”, h2 = “0”,
and h3 = PWM. At this situation, the first cell is completely on and
its current is equal to the input current, i.e., Ih1 = Iin . The second cell
does not participate in the modulation and its current is zero. The
third cell works in PWM mode and its current is a PWM function of
the input current. In this situation, the third cell is charged but not
as much as the first cell. This state lasts To = 1/fo seconds and again
a new update occurs.
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4.2. Control of the parallel-output DC/DC converters
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As explained above, the isolated DC/DC converters are connected to the separate DC links of the CHB rectifier and provide
a low voltage interface with consumer applications. In this stage,
the isolated converters may be paralleled together on the LV side
in order to drive a high power load like a three-phase voltage
source inverter. Therefore, a control strategy is necessary to share
the load current equally and uniformly among the parallel cells.
This controller should also regulate the secondary DC voltage
and attenuate the low frequency voltage ripple at the primary
links (see Fig. 8(a)). In the following part, we provide a model
for the parallel cells, including mismatching effects, and a controller is introduced to maintain current balance among the parallel
cells.
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• Considerable reduction in size and volume of the input inductance Lb ; because the input inductance will not need to tolerate
voltage greater than VC .
• Reduction in THD and EMI at the input side.
• Low switching loss; because at each time only one cell works in
high frequency switching mode.
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The following features are worth noting about the hybrid modulation technique:
• In the proposed controller, there are two modulation mechanisms. One is generated by the analog controller, termed as PWM
mode, and the other is done by the digital controller, termed as
voltage balancing algorithm.
• The PWM mode is used to control the input current and to regulate the sum of DC-link voltages to the reference value, i.e.,
VCi = NVC . This condition besides the voltage balancing condition leads to VCi = VC for i = 1,. . .,N.
• The voltage balancing algorithm is repeated with the sampling
frequency fo .
• During each sampling period, To = 1/fo , the switching functions,
h1 to hN , do not change.
• The switching period TS (or PWM period) is less than the sampling
period To , and the sampling period is less than (tK − tK−1 ).
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for K = 1, . . . , N − 1
OF
Tac
sin−1
KV RO
6
Fig. 5. Flowchart of the DC voltage balancing algorithm in the CHB rectifier (the vector (V1 , V2 ,. . .VN ) is a mapping for the DC-link voltages, sorted in ascending order, i.e.,
V1 < V2 < . . . < VN ).
Please cite this article in press as: H. Iman-Eini, et al., A modular power electronic transformer based on a cascaded H-bridge multilevel
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Fig. 6. Modeling of the parallel-output cells: (a) large signal averaged model of the kth cell, where nk = n + npk , rk = r + rpk , and VCk = VC + Vpk , (b) simplified model when the
parasitic terms and input DC offset of the kth cell are modeled with the equivalent voltage source Veq,k .
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(1) Each power switch in the on state is modeled by a constant
voltage source Von,s and a series resistance rds and in the off
state by an infinite resistance.
(2) Each diode in the on state is modeled by a constant voltage
source Von,d and a series resistance rd , and in the off state by an
infinite resistance.
(3) The parasitic and snubber capacitances are neglected.
(4) The isolation transformer is assumed to be ideal.
(5) The DC/DC converter works in continuous conduction mode
(CCM).
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4.2.1. Modeling of the parallel-output converters
Each DC/DC converter utilized in the isolation stage is modeled
under the following assumptions:
To simplify the representation of the equations, in the remainder
of this manuscript we use the lowercase letter ‘x’ as a large signal
parameter, the capital letter ‘X’ as a DC value, and the ‘x̃’ symbol as
a small signal variable, i.e., x = X + x̃.
According to the above assumptions and the modeling method
discussed in [21,22], the large signal averaged model of the PWM
full-bridge converter is realized and shown in Fig. 6(a). The illustrated transformer in Fig. 6 is an analytical model that is valid in the
entire frequency domain.
In Fig. 6, VCK , VO , and IK are the DC values of the input voltage,
output voltage and the load current, respectively, and vk , vo and
ĩk are the corresponding small signal values. The variable D represents the duty cycle of the full-bridge converter and is defined
as D = ton /Ts ≤ 0.5, where ton is the time duration during which the
diagonal switches are on and Ts is the switching period; d˜ represents the corresponding small signal value of the duty cycle. The
parameters n, rc , VF and r are the transformer ratio, equivalent series
resistance of the capacitor, the equivalent averaged voltage drop
and the equivalent averaged resistance, respectively. VF and r are
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derived as
432
VF = 2(Von,d + Von,s 2nD)
(9)
433
(10)
434
where rL is the equivalent series resistance of the inductor, rt1 is
the resistance of the primary winding and rt2 is the resistance of
the secondary winding. Eqs. (9) and (10) were derived using the
principle of energy conservation [21].
In practice, when M ideal DC/DC converters are paralleled on the
output side, the load current is divided equally among them. However, very small mismatches among the parallel converters can lead
to unequal load-current sharing. The main sources of mismatches
are from the transformers ratio (due to, e.g., leakage flux), the primary DC link offsets, and the equivalent series resistances. Although
this issue will not lead to instability and runaway conditions in
the modular structure because of control by the CHB rectifier, it
will cause unequal thermal stress on the parallel devices and will
decrease the PET performance.
We assume that the sources of mismatches in the kth cell, i.e.,
transformer ratio (nk ), cell input voltage (VCk ), and the equivalent
averaged resistance (rK ) can be written as follows:
435
r = rL + (0.5 + D)(2rd + rt2 ) + 2Dn2 (2rce + rt1 )
nk = n + npk ,
npk n,
k = 1, . . . , M
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(11)
452
(12)
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(13)
454
where n, VC and r are the desired values of each H-bridge and npk ,
Vpk and rpk are the parasitic terms or deviations from the nominal
values. Considering nk , VCk and rk in the large-signal model shown
in Fig. 6(a) and analyzing the circuit, a simplified model is achieved
where the effect of the parasitic terms is modeled with a controlled
DC voltage source, Veq,k , as
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VCk = VC + Vpk ,
rk = r + rpk ,
Vpk VC ,
rpk r,
k = 1, . . . , M
k = 1, . . . , M
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2nD ≈ 1, then an offset of 3 V in the first cell (0.5%) will cause the
following offsets: Ioff1 = +4, and Ioff2 to Ioff5 = −1 A.
Veq,k =
≈
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(14)
where Veq,k is a controlled DC voltage source that represents the
effects of mismatches and the input DC offset of the kth converter
cell. Fig. 6(b) shows the simplified model of the kth cell according
to (14). In the simplified scheme, the controlled current source is
removed because it is parallel with the input voltage and does not
affect the output voltage, vo , and the cell current, ik .
The DC voltage, Veq,k , acts as a DC offset and causes a current
offset among the parallel cells. The amount of current offset for
each cell, Ioff,k (k = 1,. . .,M), is obtained as follows:
⎡
⎤
Ioff 1
⎢ Ioff 2 ⎥ 2nD
⎢ . ⎥=
⎣ .. ⎦ Mr
Ioff M
⎡
( M − 1) −1 · · · −1
⎢ −1 (M − 1) −1 −1
⎢
..
⎣
.
−1 −1 −1 (M − 1)
⎤⎡
⎤
Veq1
⎥ ⎢ Veq2 ⎥
⎥⎢ . ⎥
⎦ ⎣ .. ⎦
Veq M
(15)
From (15), it is concluded that a small voltage offset in an Hbridge cell will cause large current offsets among the parallel cells.
For example, if the number of parallel cells is M = 5, r = 0.6 , and
4.2.2. Control of the parallel-output converters
To guarantee equal load-current sharing and voltage regulation,
we employ the controller shown in Fig. 7. This controller uses a
voltage control loop and M similar current control loops.
In Fig. 7, the current controllers are designed to provide equal
load-current sharing among the parallel cells. As can be seen, the
inductor current of the kth cell is sensed and scaled to the proper
magnitude. Then, it passes through a low pass filter. This filter is utilized to limit the loop bandwidth and to decrease the noise power.
The filter output is compared with the reference current iref generated by the voltage controller. The error signal is entered to the
PI regulator and its output determines the switching duty cycle dk .
The duty cycle expression is written as follows:
dk = D + Doff,k + d̃,
k = 1, . . . , M
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(16)
492
where dk is the duty cycle of the kth cell, D is the DC term, and d˜is
a small signal term that corresponds to the input voltage and load
current variations. This term controls the dynamical behavior of the
parallel cells. In addition, Doff,k is a small DC term that is generated
by the kth current controller to cancel the offset term defined in
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, k = 1, . . . , M
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467
2nD
+ Vpk
EC
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n
VC +
rpk Ik
RR
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2nD
npk
+ Vpk
CO
464
(2npk (D + d̃k )VCk + rpk Ik )
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OF
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RO
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Fig. 7. Proposed scheme for control of parallel-output converter cells.
Please cite this article in press as: H. Iman-Eini, et al., A modular power electronic transformer based on a cascaded H-bridge multilevel
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2n(D + Doff,k )(VC + Veq,k ) = 2n(DVC + Doff,k VC + DVeq,k + Doff,k Veq,k )
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(17)
501
In (17), the last term is negligible in comparison with the other
terms. As the desired voltage is 2nDVC , the remaining terms are set
to zero. So, it is obtained:
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2n(Doff,k VC + DVeq,k ) = 0 → Doff,k = −
DVeq,k
(18)
VC
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As a result, the effects of mismatches and the input voltage offsets
(modeled as a part of Veq,k ) are cancelled by the inner current loops
and equal DC operating points are achieved for all cells, as follows:
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Ik =
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IL
,
M
VCk = VC ,
D≈
VO 1 RL + r/M
VC 2n
RL
(19)
513
where RL is the equivalent load attached to the parallel-output cells.
It is worth noting that the external loop shown in Fig. 7 is used to
regulate the output voltage of parallel cells to the reference value
Vo,ref . The PID controller output then is used as a reference current
for all parallel cells.
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5. Simulation results
515
5.1. Verifying the performance of controllers
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The first simulation investigates the behavior of the CHB rectifier control, where the isolated converters are modeled as resistive
loads. This simulation verifies the controller performance when the
series converters extract different amounts of electric power due to
connection of unequal loads. The selected configuration has N = 5
series-connected H-bridges on the MV side (Ph–N voltage is 2.7 kV)
and the reference voltage for the DC buses VC1 to VC5 , is 600 V.
The sampling and PWM switching frequencies are also set to 3 and
15 kHz, respectively.
In the first simulation, it is assumed that the H-bridge loads are
P1 = 7 kW, P2 = 6.5 kW, P3 = 6 kW, P4 = 5.5 kW, and P5 = 5 kW. Addi-
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tionally, to investigate the dynamical behavior of the controller, a
50% voltage sag appears in the input voltage at t = 0.2 s and lasts
200 ms. The simulation results are shown in Fig. 8(a) and (b).
Fig. 8(a) shows the waveforms of the input voltage Vin and the
primary DC-link voltages, VC1 to VC5 . It is observed that all DC buses
follow the reference voltage VC = 600 V in both the transient and
steady-state conditions, although the attached loads are not equal.
At transient times t = 0.2 s and t = 0.4 s, the capacitor voltages return
to the initial values in less than 60 ms. The low frequency ripple,
which is observed at the DC buses, is inherent to the power factor
correction and will be eliminated by the isolation stage.
Fig. 8(b) shows the waveforms of the input current Iin and the
cells’ currents, Ih1 to Ih5 , over a mains period (Ihi is defined in Fig. 2).
The input current is a sinusoidal waveform with a high frequency
ripple generated by the PWM method. The plurality of the seriesconnected cells leads to an effective switching frequency that is
many times the switching frequency of the individual cells. The
input current is also in phase with the input voltage and increases
from 22.3 to 44.5 A in sag period.
Additionally, in Fig. 8(b), each cell current Ihi (i = 1,. . .,5) contains
a DC term, a low frequency harmonic (2fline ) and a high frequency
switching ripple. At steady-state, the low and high frequency components flow into the ith capacitor and the DC term (the cell average
current over a half-cycle) is equal to the ith load current. The results
shown in Fig. 8(b) confirm the validity of the above discussion,
where the cells’ average currents are proportional to the attached
load powers.
In the second simulation, the performance of the active loadcurrent sharing method is verified. It is assumed that M = 5 parallel
cells are connected to the CHB converter and the total load
power is 30 kW. Additionally, the primary DC links have very
small offsets such as Voff1 = −3 V, Voff2 = −2 V, Voff3 = 0 V, Voff4 = +1.5 V,
and Voff5 = +2.5 V, which are much lower than DC bus voltages
(VCi = 600 V). These offsets, in practice, may be caused by small mismatches in the path of voltage feedbacks. If the proposed controller
in Fig. 7 is not used, the voltage offsets will cause a large current
deviation among the parallel cells. This situation is determined by
OF
(15). According to Fig. 6(b), Doff,k is derived as follows:
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Fig. 8. Verifying the CHB converter control: (a) input Ph–N voltage (top) and primary DC link waveforms, VC1 to VC5 , in sag period and (b) a line-period of input current (top)
and cells’ currents, Ih1 to Ih5 , before sag condition.
Please cite this article in press as: H. Iman-Eini, et al., A modular power electronic transformer based on a cascaded H-bridge multilevel
converter, Electr. Power Syst. Res. (2009), doi:10.1016/j.epsr.2009.06.010
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Table 2
Simulation data used for verifying the PET performance.
Table 1
Simulation data in modeling of DC/DC converters.
Value
Parameter
Symbol
Value
Nominal power of each cell
Primary DC-link voltages
Output DC bus voltage
Transformer turn ratio
Steady-state duty cycle
Output capacitor
Output inductor
Equivalent average series resistance
Equivalent forward voltage
Switching frequency
P
VCi
Vo1
n
D
C
L
r
VF
fs
6 kW
600 V
600 V
1:1.2
0.43
47 ␮F
500 ␮H
0.6 5V
15 kHz
Number of series H-bridges
Number of parallel cells
Rated power
Nominal Ph–Ph input voltage
Primary DC-link voltages
Inverter DC bus voltage
DC load voltage
Output Ph–N voltages
Primary DC link capacitors
Input inductance
CHB sampling frequency
CHB switching frequency
N
M
Pt
Vin
VCi
Vo1
Vo2
Va , Vb , Vc
Ci
Lb
fo
fs
5
4
30 kW
3.3 kV
600 V
600 V
400 V
220 V rms
470 ␮F
10 mH
3 kHz
15 kHz
Eq. (15), for the simulation data given in Table 1, and is shown in
Fig. 9(a):
⎡I
⎡ +4 −1 −1 −1 −1 ⎤ ⎡ −3 ⎤ ⎡ −4.67 ⎤
⎢ Ioff 2 ⎥
⎢ −1 +4 −1 −1 −1 ⎥ ⎢ −2 ⎥ ⎢ −3 ⎥
⎢ Ioff 3 ⎥ = 1 ⎢ −1 −1 +4 −1 −1 ⎥ ⎢ 0 ⎥ = ⎢ +0.33 ⎥
⎣
⎦ 5 × 0.6 ⎣
⎦⎣
⎦ ⎣
⎦
off 1
566
Ioff 4
Ioff 5
⎤
−1
−1
−1
−1
−1
−1
+4
−1
−1
+4
+2.83
+4.5
(A)
1.5
2.5
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5.2. Verifying the PET performance and its features
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In this part, the performance of the designed PET is verified by
simulation. The simulated configuration is as shown in Fig. 2(b).
It is a step-down transformer (3.3 kV to 380 V) with N = 5 seriesconnected H-bridges on the input side. In addition, M = 4 cells are
paralleled at the isolation stage to supply a three-phase 25 kW
inverter, and a cell is dedicated to supply a 5 kW DC load. The
computer simulations are carried out using the MATLAB/SIMULINK
program, using the system data given in Table 2.
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Fig. 10. Verifying the PET performance under sag conditions: input voltage (top),
output 3-phase voltages (middle), and the voltage of DC load Vo2 (bottom).
The first simulation investigates the PET performance under
voltage sag conditions. In this simulation, a 50% voltage sag appears
in the primary voltage at t = 0.2 s and lasts for 200 ms. The simulation results for this study are shown in Figs. 10 and 11.
Fig. 10 illustrates the waveforms of the input voltage (Vin ), the
output three-phase voltages (Vab , Vbc , Vca ), and the voltage of the DC
load (Vo2 ). It is observed that the PE-based transformer mitigates
the voltage sag and generates a balanced three-phase voltage from
the energy still available at reduced voltage during the sag. The
voltage of the DC load is also kept constant and transient behavior
does not affect the PET performance.
Fig. 11 shows the enlarged waveforms of the AC terminal voltage and the PET input current, respectively. Verifying the results
confirms that the input current is sinusoidal and in phase with the
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Comparison between the analytical results with the simulation
result in Fig. 9(a) confirms good agreement between the two results.
Without the current controllers, the cells’ currents are divided
unequally among the parallel cells. This can bring unequal use of the
power switches and increases the complexity of the cooling system
and the design.
Fig. 9(b) shows the cells’ average currents (Iav1 to Iav5 ) when
the current controllers are used. It is observed that the current controllers provide equal load-current sharing among the parallel cells,
even in the start up period. In fact, each current controller generates
a compensating duty cycle, according to (18), to cancel the primary
voltage offset. The result shown in Fig. 9(b) confirms the validity of
the above approach.
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Parameter
Fig. 9. Verifying the active load-current sharing method: (a) cells average currents without the current controllers, and (b) cells average currents in presence of current
controllers.
Please cite this article in press as: H. Iman-Eini, et al., A modular power electronic transformer based on a cascaded H-bridge multilevel
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Fig. 13. Evaluation of PET performance when the AC load is non-linear: input voltage
and current (top) and the output phase current (bottom).
inated harmonic content and the power factor is close to 1. This
feature improves the system performance and avoids unwanted
tripping of the circuit breakers.
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6. Experimental results
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input voltage, and the number of voltage regions is automatically
adjusted to the change in Vm . During the sag event, a 7-level waveform was synthesized on the AC side and the current amplitude
increased from 16.5 to 33 A rms.
The second simulation investigates the PET performance under
voltage flicker conditions. In this simulation the input voltage is
distorted with a flicker whose frequency is 8 Hz and whose modulation index is 10%. The result is shown in Fig. 12. As can bee seen
from Fig. 12, the PET corrects the voltage flicker on the load side
around a voltage set point, which tracks the steady-state voltage
level. Also, the voltage of DC load is well regulated around the DC
reference and is ripple free.
Fig. 13 shows the situation where the load is non-linear (a fullwave diode rectifier was paralleled with a 1 mF capacitor and a 10 resistor), such as the input stage of variable speed drives, UPS units
and DC/DC converters. In a conventional transformer, the distorted
load current drawn by the non-linear load can cause a distorted
voltage drop in the cable impedance. The resultant distorted voltage
waveform is applied to all other loads connected to the same circuit,
causing harmonic currents to flow in them—even if they are linear
loads. Therefore, this simulation verifies the PET behavior under
non-linear load condition and shows its capability to mitigate the
current harmonics.
The bottom trace in Fig. 13 shows the load current, which has
been distorted by the non-linear load (73.96% THD) and the top
trace shows the PET input current, which is sinusoidal and in phase
with the input voltage. It is observed that PET significantly elim-
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Fig. 11. Details of AC terminal voltage and input current when a 50% voltage sag
happens at t = 0.2 s.
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Fig. 12. Evaluation of PET performance under voltage flicker condition: input voltage
(top), output phase voltage (middle), and voltage of DC load Vo2 (bottom).
The validity of the proposed PET and the designed controllers
are verified by experimental results on a laboratory scale prototype.
The prototype is a 1500 W, single-phase to three-phase transformer
based on a 7-level CHB rectifier. The rated Ph–N input and output
voltages are 230 and 39 V rms, respectively. The digital control unit
was implemented based on a TMS 320F2812 DSP controller. Other
principal parameters of the prototype are given in Table 3.
It is worth noting that low voltage power MOSFETs (MOSFET + internal body diode with the break down voltage 200 V) were
intentionally used in the prototype to demonstrate a scale down
of the real situation. However, in the medium voltage levels, the
IGBTs would be the best choice due to better voltage and current
ratings. Fig. 14 demonstrates the implemented hardware setup for
the experimental study.
The first experiment investigates the PET performance in steadystate and sag ride-through conditions. In this experiment, the input
voltage drops 50% from the rated value and again recovers to the
initial value after 1000 ms. The load power is constant and equal
to 1000 W. The corresponding input and output voltage waveforms
are shown in Fig. 15.
From Fig. 15, it is observed that the output Ph–N voltages are kept
constant, regardless of the input voltage variations. In fact, during
Table 3
Principal parameters in the hardware prototype.
Parameter or component
Symbol
Value
Number of series H-bridges at the input
Rated power
Nominal peak input voltage
Primary DC-link voltages
Secondary DC-link voltage
Output Ph–N voltages
Transformers turn ratio
Primary DC link capacitors
Input inductance
Secondary DC link capacitor
Secondary inductors
Steady-state duty cycle
Cell equivalent average series resistance
Sampling frequency
Switching frequency
N
Pt
Vm
VCi
Vo
Va , Vb , Vc
n
Ci
Lb
CO
L
D
r
fo
fs
3
1.5 kW
310 V
125 V
100 V
39 V rms
1:1
1 mF, 250 V
2 mH
470 ␮F, 160 V
220 ␮H
0.4
0.26 3 kHz
15 kHz
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and the voltage source inverter. In this experiment the line side
and the load side power frequencies are 50 and 60 Hz, respectively.
Fig. 16 shows the experimental results for these conditions. It is seen
that the symmetrical three-phase output voltages remain constant
and their frequencies are 60 Hz.
Fig. 17 illustrates the input and output phase currents when
the load is non-linear. In this experiment, the non-linear load is
constructed by a three-phase diode rectifier and a resistive load
EC
660
the sag period, the CHB rectifier forces the primary DC buses to
follow the reference value, and the isolation stage attenuates the
low frequency harmonic generated by the first stage. Therefore a
clean sinusoidal and balanced voltage is generated by the threephase inverter on the load side.
The second experiment verifies the PET performance as a frequency converter. It is possible to supply the load with the desired
amplitude and frequency due to the presence of DC link capacitors
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Fig. 17. PET performance under a non-linear load: input current (top) and the output
phase current (bottom).
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Fig. 15. PET response to a 50% sag ride-through: input voltage (top) and the output
three-phase voltages (bottom).
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Fig. 14. Laboratory scale prototype of PET converter (with N = 3, M = 3, and 200 V power MOSFETs).
Fig. 16. PET as a frequency converter: 50 Hz input voltage (top) and the 60 Hz threephase output (bottom).
Fig. 18. PET as a VAR compensator: input voltage and current waveforms (top) and
the output voltage and current curves (bottom).
Please cite this article in press as: H. Iman-Eini, et al., A modular power electronic transformer based on a cascaded H-bridge multilevel
converter, Electr. Power Syst. Res. (2009), doi:10.1016/j.epsr.2009.06.010
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H. Iman-Eini et al. / Electric Power Systems Research xxx (2009) xxx–xxx
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In this paper a modular PE-based transformer for feeding
critical loads was presented. The modular structure offers important advantages during design, testing, manufacturing and service
stages. The same modules can be used for different voltages (or
currents) by stacking (or paralleling) the appropriate number of
modules depending on the working voltage (or power). The proposed design consists of three stages; CHB rectifier, isolation stage,
and voltage source inverter. Using the CHB rectifier, a direct connection to the medium voltage levels is realized. This rectifier controls
the input power factor and reduces the high AC input voltage level
to low DC voltages. The isolated DC/DC converters then provide
good voltage isolation between HV and LV sides and attenuate the
low frequency voltage ripples of the primary DC links. Additionally,
new control strategies were presented to ensure that the primary
capacitor voltages converge to the reference value, and equal loadcurrent sharing is achieved between the parallel-output cells. The
validity of the proposed controllers and analytical formulas were
verified by simulation and experimental results. The experimental results also confirmed the usefulness of the PET converter in
removing power quality disturbances. Interesting future questions
include investigating ways to increase the efficiency, particularly in
the isolation and output stages.
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(Pin = 1000 W). The current waveforms in Fig. 17 confirm that the
input current is sinusoidal and has a unity power factor, regardless
of the output current wave-shape. With the closed-loop control, the
output voltage is also maintained sinusoidal under non-linear load
condition. The THD of the input current, output voltage, and output
current are 3.9, 7.8, and 31%, respectively. It is evident that a conventional transformer cannot perform this function and harmonics
may propagate onto the network and so affect other customers.
The last experiment verifies the PET capability in reactive power
compensation. As may be seen from Fig. 18, the line current leads
the input voltage with the power factor PFin = 0.8. In this case, the
PET injects 750 VA reactive power into the input line and absorbs
1000 W active power from it. The functions of injecting or absorbing reactive power can be used to control power flow and improve
transient stability on power grids.
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Please cite this article in press as: H. Iman-Eini, et al., A modular power electronic transformer based on a cascaded H-bridge multilevel
converter, Electr. Power Syst. Res. (2009), doi:10.1016/j.epsr.2009.06.010
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