Binary Adders and Subtractors
Name: __________________________
Objective: The purpose of this experiment is to study the design and implementation of
combinational adder and subtractor circuits. This includes half and full adders and an
externally controlled full-adder/subtractor combination circuit.
Equipment: One standard Logic Lab Kit and TTL chips.
Procedure:
1.0 Half-Adder Design
1.1 Complete the C (carry) and S (sum) columns in Table 1.1 below for a halfadder circuit. Derive the minimal AND-OR equations for C and S and write
them below in the spaces provided.
x
0
y
0
0
1
1
1
0
1
C
C-LAMP
S
S-LAMP
Table 1.1: Half-adder truth table
S = _______________
C = _______________
1.2. Connect your circuit using NAND gates and verify that it operates properly
by completing the appropriate lamp columns above in Table 1.1. Draw your
final circuit implementation below in double-rail form.
2.0 Half-Subtractor Design
2.1 Complete the B (borrow) and D (difference) columns in Table 1.2 below for
a half-subtractor circuit. Derive the minimal AND-OR equations for B and D
and write them below in the spaces provided.
x
0
y
0
0
1
1
1
0
1
B
B-LAMP
D
D-LAMP
Table 1.2: Half-subtractor truth table
B = _______________
D = _______________
2.2 Connect your circuit using NAND gates and verify that it operates properly
by completing the appropriate lamp columns above in Table 1.2. Draw your
final circuit implementation below in double-rail form.
3.0 Full-Adder/Subtractor Circuit Design
3.1 Design a combinational logic circuit to implement a full-adder when an
external control input, E, is logical zero; or a full-subtractor when E is logical
one. Include two additional indicator lamps, one for "ADD" mode and one for
"SUBTRACT" mode.
3.2 Complete the C, B, and S/D columns in Table 1.3 below for your combination
full-adder/subtractor circuit. Derive the minimal AND-OR equations for C, B, S
and D and write them below in the space provided
x
0
0
0
0
1
1
1
1
y
0
0
1
1
0
0
1
1
z
0
1
0
1
0
1
0
1
C
C-LAMP
B
B-LAMP
Table 1.3
S = ________________________________________
D = ________________________________________
C = ________________________________________
B = ________________________________________
Draw your K-maps for S/D, C, and B in the space below.
S/D
S/D-LAMP
3.3 Connect your circuit using NAND gates and verify that it operates properly by
completing the appropriate lamp columns in Table 1.3. Draw your final circuit
implementation below in double-rail form.
3.4 When you have completed all the above, have your instructor sign below.
_______________________________
Instructor's Signature
Questions
Design a full-adder circuit that has two two-bit input words A, B and C, D and
one three-bit sum output word EFG as shown below. Using the complete truth
table method, and K-maps as appropriate, write the minimal AND-OR equations
in the spaces provided below.
AB
+ CD
E F G
(A, C, and E = MSB for each word)
E = ____________________________________
F = ____________________________________
G = ____________________________________
Show your work and K-maps below.
(5 points)