Multiphase Voltage-Mode Hysteretic Controlled VRM With DSP Control
and Novel Current Sharing
J. A. Abu-Qahouq, N. Pongratananukul, I. Batarseh, and T. Kasparis
School of Electrical Engineering and Computer Science
University of Central Florida
Orlando, Florida 32816, USA
batarseh@mail.ucf.edu
ABSTRACT - Applying the voltage-mode hysteretic control
to multiphase Voltage Regulator Modules (VRMs) can satisfy
many of the new and future generation of microprocessors and
ICs powering requirements. This is because of the numerous
advantages that can be obtained when both techniques are used.
However, several challenges arise that include current sharing,
multiphase control signals distribution, high-speed comparators
noise sensitivity, hysteretic band accuracy and stability, VRM
operation startup, and the stability of the controller operation at
large load transients. Addressing these challenges cannot be
easily achieved using analog and discrete components but rather
DSP can be used to solve these problems. In this paper,
multiphase voltage-mode hysteretic controlled VRM with DSP
control and novel current sharing is proposed.
I. INTRODUCTION
The increasing demand for lowering the new generation
microprocessors operating voltages to achieve high
performance and high power density has never been greater
[1-8]. As a result, the steady state and dynamic requirements
are becoming stricter, which makes the power supply design
process a non-easy task. It is expected that the required
operating voltages in the next few years will decrease below
1V while increasing the current drawn from the power supply
in order to reduce the power consumption while increasing
the microprocessor speed and its integration density [5-9].
Moreover, the slew rate at the Voltage Regulator Module
(VRM) output will be much higher than 50A/µs in the future
when the microprocessor switches from one state to the other.
This causes voltage spikes at the processor power supply.
These transient spikes must be limited to a certain maximum
value such as 2%~3% or even lower. As the processor supply
voltage becomes lower, the allowed voltage deviation during
the load transient becomes tighter [1-8]. Distributed Power
System (DPS) can be used to satisfy overall system
requirements by using on-board VRM located near the
processor.
Most of today’s non-isolated Low-Voltage Regulator
Modules (LVRMs) are buck derived such as the conventional
buck, the synchronous buck and the Quasi-Square-Wave
(QSW) buck [1,3,5,9]. While the isolated LVRMs are such as
symmetrical and asymmetrical half-bridge, active clamped
forward, flyback forward and push-pull [6,9]. The secondary
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side of the isolated topology can have different schemes such
as forward, center-tapped, or current-doubler as discussed in
[6].
To achieve high current slew rate at load transients,
assuming that the closed loop has sufficient bandwidth, the
LVRM output inductor ( Lo ) should be as small as possible.
Unfortunately, using small output inductor to achieve faster
transient response will cause the output voltage ripple to
increase and pushes the LVRM operation towards
discontinuous mode of operation. In order to reduce output
voltage ripple, it is required that the switching frequency be
increased. However, the higher the switching frequency, the
lower the efficiency, making the selection of the switching
devices very important step in the converter design process. It
is also possible to reduce the output voltage ripple by
increasing the output capacitor, resulting in a physically large
size for practical design.
In practical designs, typically the crossover frequency is
designed in the range of 20%-30% of the switching
frequency. Hence, the higher the switching frequency, the
faster the closed loop response, resulting in smaller output
capacitor and smaller critical output inductor value required
to operate in the Continuous Conduction Mode (CCM).
Another requirement in the design of LVRM is to have
high input current slew rate that in turns requires large input
capacitor ( C in ). In order to decrease C in , the input voltage,
Vin , must be increased. This means DPS with high-voltage
bus is needed. This makes the isolated LVRMs more
attractive than the non-isolated ones because it includes a
transformer that can be used to step-down the input voltage as
mentioned before.
Applying the voltage-mode hysteretic control to
multiphase VRMs can satisfy many of the new and future
generation of microprocessors and ICs powering
requirements due to the numerous advantages that can be
obtained when both techniques are used. However, there are
several challenges arise. These include current sharing
between the phases, multiphase control signals distribution,
high-speed comparators noise sensitivity, hysteretic band
accuracy and stability, the VRM operation startup, and the
stability of the controller operation at large load transients.
Addressing these challenges cannot be easily achieved using
analog and discrete components. DSP control can be used to
solve these problems.
In this paper, a DSP control algorithm using a
programmable real time DSP chip is applied to a multiphase
voltage-mode hysteretic controlled buck converters VRM
with current sharing. In the next section, the idea of
interleaving with voltage-mode hysteretic control is
discussed. Section III states some of the challenges in
implementing this idea and possible DSP solution. The block
diagram of the VRM with DSP control and the DSP
algorithm are given in Section IV. Simulation results are
presented in Section V and experimental work is discussed in
Section VI. The conclusion is given in Section VII.
II. INTERLEAVING WITH VOLTAGE-MODE
HYSTERETIC CONTROL
Both the interleaving and the single-phase voltage-mode
hysteretic control techniques can reduce the output voltage
ripple. However, the overshoot and undershoot requirements
during large magnitude transients still have to be
investigated. It is known that to obtain low output overshoot,
the multiphase LVRMs require the design of highperformance feedback control that can also provide current
sharing [9-11].
Hence, even though the interleaving
technique reduce the output voltage ripple and helps in
achieving faster current transient response, a careful control
design and/or increase in the output capacitance size will be
needed in order to satisfy the maximum overshoot and
undershoot limits during large load transients.
In the single-phase hysteretic voltage-mode control
technique, the hysteretic window can be set to a certain level
such that the controller will respond quickly to load transients
and correct the voltage before deviating from the maximum
allowed overshoot and undershoot. Even though the output
capacitor size still plays an important role here, its size is
significantly reduced because of the hysteretic window.
On one hand, voltage-mode hysteretic control has many
advantages over many other control techniques that include
simplicity, no feedback loop compensation is needed, near
instantaneous response to load transients, and no limitations
on the switches conduction time. On the other hand, the
interleave technique has several advantages such as the high
frequency output voltage ripple with lower switching
frequency, ripple cancellation, current division (sharing)
between the phases which allows higher current carrying
capability, and also fast transient response which is limited by
the feedback control loop. From this, it is clear that by
combining the voltage-mode hysteretic control technique
with the interleave technique will result in a VRM that has
the advantages of both techniques.
When applying the hysteretic voltage-mode control to
interleaved buck converters, one must note that: 1) The
derived control signal from the output ripple (hysteretic
control) must be frequency divided while keeping the same
control-signal ON-time (interleaving) and 2) During
transients, multiphase control operation must be disabled so
that all the phases' switches will switch ON and OFF at the
same time. The first note is to keep the switching frequency
low (lower than the output voltage ripple frequency) so that
the interleaving can be achieved. The second note is to
achieve faster transient response and synchronization
between the phases during transients.
Figure (1) shows the basic block diagram of N interleaved
synchronous buck phases with voltage-mode hysteretic
control, while Figure (2) shows the example of control
signals for two interleaved phases (N=2) for illustration
purposes.
The main control signal ( Cm ) is generated by comparing
the input voltage to a minimum value ( VL ) and a maximum
value ( VH ). Then, the generated pulses are distributed
between the phases interchangeably so that one phase highside switch is ON at a time whereas all the other switches are
OFF at that time. This will generate the required multiphase
control-signals C1 , C2 , …., C N .
At transients, another hysteretic comparator with wider
window that has smaller lower value and higher upper value,
i.e. VLT < VL and VHT > VH is required. If these new limits are
reached, then the controller turns ON all the high-side
MOSFETS and turns OFF all the low-side MOSFETS in lowto-high load transient and to opposite manner in high-to-low
load transient. Figure (3) shows how the multiphase control
signals can be generated from the main control signal using
discrete components for two and four phases along with their
corresponding waveforms.
III. IMPLEMENTATION CHALLENGES AND THE DSP
SOLUTION
There are several challenges to efficiently implement the
multiphase voltage-mode hysteretic-controlled VRM with
analog and discrete components. These challenges along with
the DSP solution are as follows:
A. Current Sharing Between the Interleaved Phases:
It is very important that the current be distributed almost
equally between the interleaved phases. Unfortunately,
component and connections differences from phase-to-phase
to the load and other non-idealities may cause the current
distribution (sharing) to be unequal especially at large load
transients [10,11].
Current sharing between the interleaved converters can be
achieved by controlling the ON-time of each converter phase
such that the ON-time of the phase that carry larger current
from the other phases is less than the ON-time of the other
phases and the phase that carries the smallest current has the
largest ON-time. Unfortunately, in the voltage-mode
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Figure (1): Block Diagram of N Interleaved Buck Converters with
Voltage-Mode Hysteretic Control
Figure (3): Multiphase Logic Circuits to Generate Multiphase
Control Signals
Another more efficient way, which will be implemented
here, is to compare the current values in each phase and turn
ON the phase that carry the smallest current. This technique
results in more accurate current sharing between the phases
than the first technique. Moreover, sensing the load current
and generating the current reference for each phase
depending on the load changes is not required here for the
current sharing purposes (It may be required for other
functions such as protection) since the current value of the
phases are compared directly with each other not to a
reference value that need to be generated dynamically
following the load changes as in the first technique. This
results in better and more stable current sharing.
This current sharing functionality can be more easily
implemented using programmable fast DSP than using
discrete components even with large number of phases. As an
example, if four phases are to be interleaved, Phase 1 current
will be compared to Phase 2 current and Phase 3 current will
be compared with Phase 4 current and the smallest of both
comparisons will be compared again to find the phase that
Figure (2): Example of Control Signals for Two Interleaved Phases
(N=2)
hysteretic control the ON-time mainly depends on the
previously set hysteresis window. Hence, another technique
of current sharing must be employed.
One way is to check the current of the phase that has the
turn to be turned ON and pass the ON-signal to the next
phase if the current in that phase is larger than a reference
value.
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positioning, and voltage identification coding that require
voltage reference and band changing can be easily
implemented using DSP by simply changing the numerical
value of the reference and the band limits.
In summary, the DSP has several advantages, among
them: simplicity in applying sophisticated control algorithms
and modifying them via software revision, lower
environmental and noise sensitivity, and less component
count.
carries the smallest current and turn it ON when the output
voltage hits (reaches) the low hysteretic window limit.
B. Multiphase Control Signals Distribution:
As the number of interleaved phases increases, the design
and logic of the phases control signals distribution part
becomes more complicated and unstable, and the delay time
increases, especially when a current sharing technique is
implemented.
However, using a fast programmable DSP, the pulse
distribution between the phases will be easier since the
control pulse can be programmed to pass to the correct phase
at the correct time by sending it to the digital output port of
the DSP. Hence, the design complication will not be affected
by increasing the interleaved phases.
IV. DSP CONTROLLED VRM BLOCK DIAGRAM AND
DSP PROGRAMMING ALGORITHM
Figure (4) shows the block diagram of four-phase
interleaved VRM with voltage-mode hysteretic control and
current sharing using a fast DSP processor. The VRM output
voltage and the current in each phase are being sensed to
generate the required interleaved control signals through a
programmed real-time fast DSP.
C. High-Speed Comparators Noise Sensitivity and Band
Accuracy:
One of the complications that may face the designer is the
high-speed hysteretic comparators noise sensitivity and
hysteresis band accuracy, especially at large load transients. It
is very important that the hysteretic comparators respond very
fast and at the required time. Moreover, the high noise
sensitivity of the high-speed comparators may cause the
comparators to give wrong output signals if not well designed
and to cause the controller operation to be unstable especially
that the whole controller operation of the voltage-mode
hysteretic control depends on the comparison process.
Using programmable real-time fast DSP, the VRM output
voltage can be converted to digital by ADC (Analog-toDigital-Converter) with high speed and high resolution and
then compared to reference values previously set in the DSP
program. This will eliminate the use of analog comparators
and make the controller immune to noise and more stable,
especially at transients. Moreover, accurate and stable
hysteresis band can be achieved since the comparison is
being done numerically.
D. VRM Operation Startup and Other Functions:
Many other functions may need to be added to the VRM
controller, such as operation startup, active voltage
positioning, and voltage identification coding [14-16]. These
functions can be easily implemented by DSP without
increasing the design complication.
As an example, the VRM operation startup can be
implemented by turning ON and OFF the switches with a
certain constant frequency, all the phases at the same time,
starting with a small duty ratio. The program automatically
will keep checking the output voltage and increase the duty
ratio of the signal until the output voltage enters the
hysteresis band. When the output voltage enters the hysteresis
band, the program will switch to the normal multiphase
voltage-mode hysteretic operation. The active voltage
Figure (4): Block Diagram of Four-phases Voltage-Mode HystereticControlled Interleaved Converters with DSP Control
Figure (5) shows s simplified controller flowchart. The
program operation starts with a soft start operation after
reading the required output voltage from the Voltage
Identification Coding (VID) [16]. During this period, all
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phases receive the same control signal without multiphase
operation with a preset frequency f and duty ratio D. At the
beginning, D is set to be small and it is slowly increased until
the output voltage reaches a voltage equal to a percentage of
the required output voltage. When this condition is met, the
controller enters the multiphase voltage-mode hysteretic
control algorithm described in the previous sections and as
shown in Figure (5).
V. SIMULATION RESULTS
Figure (6) shows simulation results for four-phase VRM
with the following design parameters: Vin = 12V , Vo = 1.5V ,
I o = 80 A at full load steps to 40A at transient,
L phase1 = L phase 2 = L phase 3 = L phase 4 = 1µH , and Co = 1.5mF , with
steady-state hysteretic band of ±10mV and transient
hysteretic band of ±20mV.
S ta rt
R ead R eq u ired
O u tp u t V o lta g e
(V ID C o d in g ) to
In itiate S o ft S tart
O p eratio n
S et V start
=
x% o f T h e R eq u ire d
O u tp u t V o lta g e
S tart T u rn in g O N an d
O F F A ll T h e P h ase s
T o g e th er W ith N o
M u ltip h ase O p eratio n
w ith F req u en cy = f a n d
V ery S m all D u ty Ratio = D
Read
Vo
D =D+ ∆ D
No
V o > V sta rt
?
Figure (6): Four-Phase VRM Simulation Results
Y es
VI. EXPERIMENTAL WORK
In addition to the importance of careful design of the
multiphase power stage, the selection of the real-time DSP
processor chip and the Analog to Digital Converter (ADC) is
very important. Some of the most important parameters in the
selection of the DSP and ADC are their speed and noise
sensitivity and the ADC resolution.
The laboratory availability was for the TI DSP Chip and
Evaluation Module of TMS320LF2407 [12] which has 33ns
Instruction Cycle Time (30 MHz) which is relatively slow for
this application (Refer to [12] for more information on
TMS320LF2407). This chip is geared toward control
applications. However, it lacks the processing speed
(30MHz). In addition, increase in processing power is
necessary for advance control methods in the future.
Hence, even though this DSP chip is used here for initial
experimental verification, the experimental work has to be
and will be implemented in a faster DSP chip to achieve
faster response, lower output voltage ripple, better current
sharing accuracy, higher switching frequency, and better
stability.
A good candidate is the C64x DSP family has a speed
range of 400-600MHz [13], i.e., instruction cycles in the
range of 2.5ns to 1.67ns, will be used in the near future to
repeat the experimental work. Moreover, future DSP chips
speed will break the 1GHz speed limit [17].
R ead R eq u ired
O u tp u t V o lta g e
(V ID C o d in g )
S et T h e
H ysteresis L im its
V L T , V L , V H =V H T
Read
Vo
T u rn O N all h ig h -sid e
sw itch es an d O F F all lo w sid e sw itch e s
V o< V L T
V o=?
V o> V H
T u rn O F F all h ig h -sid e
sw itch es an d O N a ll lo w sid e sw itch e s
V o< V L
R ead P h ases
C u rre n ts
I1 , I2, I3, ...In
W h ic h
P h as e H as T h e
M in im u m
C u rre n t
? = Im in
S to re Im in
P h as e C o n tro l
S ig n al Ad d re ss
= P _tu rn _o n
T u rn O N th e h ig h -sid e
sw itch o f P _tu rn _o n an d
tu rn O F F a ll th e o th e r
sw itch es
Figure (5): DSP Program Flowchart
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The ADC used here is the TI 12-bit 53MHz ADS807 [18]
with OPA642 Op-Amp in its signal conditioning circuitry.
The VRM power stage includes paralleled buck
converters with the following main components:
•
•
•
MOSFETs: SI4410DY.
Output Capacitors: 3 SANYO OSCON of 820uF, 4V.
Output Inductors: 28 A, 1uH, T68-8/90 Core, 7-turns,
16AWG Wire.
• MOSFET Drivers: TPS2836.
• OP-AMP for current sense signal of the MOSFETS
junctions amplification: OPA642.
• Vin=5-12V input voltage source.
Figure (7), (8), and (9) show the experimental results for
two-phase VRM, three-phase VRM, and four-phase VRM,
respectively. All with the slow 30MHz TMS320F2407 DSP
board which limits the switching frequency and the minimum
output voltage ripple.
VII. CONCLUSION
Multiphase VRM with voltage-mode hysteretic control
interleaved buck converters is proposed. On one hand,
voltage-mode hysteretic control has many advantages over
other control techniques, which include circuit simplicity, no
feedback loop compensation is needed, near instantaneous
response to load transients, and no limitations on the switches
conduction time. On the other hand, the interleave technique
has several advantages such as high frequency output voltage
ripple with lower switching frequency, ripple cancellation,
current division between the phases, and also fast transient
response which is limited by the feedback control loop. It is
shown here that by combining the voltage-mode hysteretic
control technique with the interleave technique will result in a
VRM that has the advantages of both techniques. The
implementation method and considerations of such VRM
were explained.
The proposed controller and the current sharing methods
were implemented using programmable real-time DSP.
Preliminary experimental setup and results were presented.
Future work will include using faster DSP to implement
the proposed VRM technique, adding more functions to the
current program, and develop new control algorithms.
Figure (7): Experimental Results for Two-Phase VRM
Figure (8): Experimental Results for Three-Phase VRM
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