INTEGRATION OF SABER SIMULATION RESULTS
INTO THE CADENCE FRAMEWORK DATABASE
BY USING THE CELL PROPERTY FEATURE
M. PISTAUER and G. BABIN
Siemens Designcenter for Microelectronics
Siemensstrasse 2
A-9500 Villach, AUSTRIA
Email: m.pistauer@ezmvi.siemens.co.at
g.babin@ezmvi.siemens.co.at
ABSTRACT – This paper proposes a method to backannotate simulation
results gained due to an initial point dc-simulation with the analog simulator
SABER® into the Cadence Database and further to display these simulation
values in the schematic editor Composer as part of the Cadence Design
Framework II™.
1 Introduction
At the Siemens Design Center for Microelectronics (EZM Villach) the design tool SABER
V3.x (now starting with V4.0) from Analogy Inc. is widely used in a heterogeneous design
and simulation environment. SABER is a tool for simulation of analog circuits and systems,
digital systems, event-driven analog systems and mixed-mode (analog combined with either
event-driven analog or digital) systems through all levels of description - from highest
structural level down to transistor (or gate) level. With SABER’s MAST language even a
combination of circuit blocks with different description levels in one model description
("template") is possible. SABER provides a library with a number of predefined templates,
which can be used as circuit hierarchy, and a number of predefined components [5].
On the other hand we use the Cadence Design Framework II™ with its database as an
integrated design framework from schematic layout over simulation, routing and design
verification for analog, digital and mixed-mode systems. This framework allows the use of
different design tools with a uniform user interface and a global database. Due to the
mentioned features of the SABER simulator the use of this tool is very common. Further the
integration of Saber is enforced due to the Frameway® Integration for the Cadence Design
Framework II [1].
Our motivation to improve the design work in points of view of efficiency, fault susceptibility
and system integration is based on experiences of the common designer day work as well as
better design documentation. This is mainly the missing backannotation of simulation results
directly on a sheet of the schematic editor (Fig. 2) after circuit parameter selection and circuit
simulation. In the first circuit design phase parameter changes and circuit (re)design are done
after manual reading and searching significant circuit parameter values in the simulator output
file. In general this file is huge and increases after each simulation since simulation results are
appended.
In this realization we focus on the backannotation of simulation results concerning a dcanalysis. These are dc voltage values for nets and specific currents of bipolar and mos
transistors. The realization is a global solution and allows the extension to any other circuit
parameter value.
In this paper we will show the concept of integration (section 2) and implementation (section 3)
in the existing design framework considering a user transparent data flow with easy handling.
Further with this kind of realization it will be shown how to extend this small application even in an extension of the existing Frameway®.
2 System Integration
The concept of a hierarchical database (like the Cadence DFII) does not allow the modification
of single components (cells) as parts of a circuit (which is a cell too) without the influence to
other circuits using the same cell. Therefore cell specific addendums have to be generated to
consider cell specific simulator output information. By creating new userproperties and
displaying them in the schematic window the original database information is not changed and
the simulator results are available as additional values.
With the current database structure there is no easy way to permanently store such simulation
results, with respect to the dynamic use of the circuit in an arbitrary higher ordered cell, as
static representation of the circuit available through a schematic editor. Our current approach is
to allow the designer to backannotate his active simulation values into the schematic easily,
either to create a printout, or to refine his design/simulation interactively.
With the programming language SKILL [3], provided by the Cadence Design Framework,
access to the complex Cadence database is possible. Further the requirements of an easy
integration of this small application in the Cadence Design Framework can be fulfilled with the
aspect of a user transparent data flow.
This yields to following realization:
• installing a control window, displayable with a "hotkey" from the schematic editor
window.
• searching the database entry of the cell and all belonging subcells for selected nets and
instances with its parameters
• creating a list of nets and instances with its parameters
• updating this list with parametervalues gained by searching the SABER outputfile
• creating userproperties for selected nets and instances and setting its values obtained
from simulation results (SABER outputfile)
• displaying these userproperty values in the schematic editor window by setting text
display options
The extraction of instance and net parameter values from the SABER outputfile is performed
with a PERL script [6]. All other parts are written in SKILL. Details are shown in the next
section.
3 Implementation
3.1 SKILL functions
SKILL provides all main functions to
start the control window with a "hotkey"
(hiSetBindKey()), searching for
nets
in
a
specific
cell
(dbFindNetByName())
and
searching for instances in cells
(dbFindAnyInstByName()).
To display parameter values so called
userproperties are defined. The CDF
(Component
Description
Format)
parameters could be used for instances,
but are not defined for nets. With the
SKILL function dbCreateProp() a
user defined property can be created and
a value assigned to it.
Fig. 2: Backannotation control window inside the
Cadence Design Framework
Each net in the schematic editor is in fact
a list of different figures (lines), instances are defined as one single figure. For each figure its
coordinates on the schematic editor are stored in the database. To display each parameter value
in the schematic editor window the position of each figure has to be searched in the database
and a so called "textdisplay" has to be assigned to the parametervalue. The position of this
textdisplay has to be calculated with respect to the position of the figure the parametervalue
belongs to. All this searching in the database takes in fact "some" time, mainly caused by the
fact, that SKILL is only an interpreted language, with all the overhead of the Cadence Design
Framework.
3.2 Hierarchical backannotation
Simulation of analog circuits requires specific testcircuits to characterize them. This results
finally in a hierarchical netlist where the circuit of interest lies hierarchically below the
characterization circuit. Since SABER simulations can be performed from high structural levels
down to transistor levels [5] all significant circuit parameters can be evaluated during one
simulation run. The saber outputfile contains all necessary information for any instance or net
in any or all hierarchies. Therefore a list of nets and instances with respect to their hierarchy
must be generated. Updating of this list is a complex task - simulator outputfiles are huge,
especially in cases of several circuit hierarchies and backannotation of transistor values.
The PERL script successfully performs well in this case to search through the simulator output
file and to update the parameterlist.
4 Results and Conclusion
After a first implementation in the design framework there were some slight changes in the user
interface necessary to improve the handling performance of this application, this means to get
closer to a so called "push-button solution". Further there is a strong demand on the
implementation of more simulation results to be backannotated to overcome the need on time
comparing the simulation results with circuit parameters, e.g. width and length of transistors,
after each simulation during
the circuit design phase.
Now the first releases of this
application are successfully
used at the EZM Villach.
Ongoing work will be done
in interaction with designer
needs as well as some slight
changes for the SABER
simulator version 4.0, where
the Frameway® currently
provides only crossprobing.
Further on we try to use
AIM,
the
Analogy
Incorporated
Macro,
to
directly access the simulator
values instead of using the
SABER outputfile for circuit Fig. 3: Schematic editor window with backannotated values for
parameter evaluation, to dc-voltage of nets and Drain-Source currents of mos transistors
reduce data transfer time.
5 References
[1]
ANALOGY. Frameway® Integration for the Cadence Design Framework II ™. User
Manual Release 4.0-2.8. December 1995.
[2]
ANALOGY. Introduction to the Saber Simulator. Analogy, Inc., Beaverton, OR 970751669. June 1991.
[3]
CADENCE. SKILL for Designers and SKILL for Programmers. Training Manual,
Educational Service Group, Version 4.3. April 1994.
[4]
F. Dielacher. Evaluation of the analog simulation tool SABER. Jessi AC 12 Milestone
Report. Subproject "Simulation", Work Package "Analog Simulation". December 1992.
[5]
H.- O. Meyn. Evaluation and Usage of Selected SABER Facilities. Jessi AC 12 Milestone
Report. Subproject "Simulation", Work Package "Analog Simulation". June 1994.
[6]
L. Wall and R. L Schwarz. Programming Perl. O‘Reilly & Associates Inc., ISBN 0937175-64-1.