Copyright © 2001, GaAs MANTECH, Inc.
Biased, Backside Failure Analysis Techniques for Small Plastic Packages
Steve Brockett and Ting Xiong
TriQuint Semiconductor, Inc.
2300 NE Brookwood Parkway; Hillsboro, Oregon 97124
Phone: 503-615-9303 email: sbrockett@tqs.com
ABSTRACT
We will present three techniques for analysis of GaAs RFICs
in SOT-23 packages. The first is simple acid decapsulation from
the die-side of the device. Next, we will show two methods to
analyze these devices from the backside. One technique utilizes
the light-transmission properties of GaAs to “look” through the
substrate and the other utilizes a GaAs etch to completely
remove the substrate and expose the device metals.
INTRODUCTION
Failure analysis is an integral part of controlling and
improving any integrated circuit manufacturing process.
Before any yield or reliability problem can be solved, it is
first necessary to understand the nature of the failures and,
when working on plastic-packaged parts, this usually
involves deprocessing the package while keeping the failing
circuit intact. As device packages become smaller, the job of
the failure analyst becomes more difficult.
As Received
Leads bent out straight
The SOT-23 package is a die-down, gull-wing package
with up to eight leads. The plastic body measures 2.9 x 1.6 x
1.2 mm high (see figure 1).
Sometimes plastic is thin
enough that leads fall off
After Plastic Etch
Figure 2.
etching.
SOT-23 package drawing before and after topside plastic
Figure 1. SOT-23 eight-leaded packages on a US penny.
TOPSIDE ACID DECAPSULATION
Deprocessing the plastic to expose the die usually involves
bending the leads out straight and using an automated jet
etching system (see figure 2). After etching the plastic, the
device is sometimes not in an easily biased condition, but the
topside die surface is available for visual inspection and
microprobing. (see figure 3).
Figure 3. SOT-23 package after etching the plastic from the die.
Often, as in this case, the package leads are disconnected from the
plastic body, only loosely held by the bond wires.
Another complication for topside decapsulation is the
introduction of new dielectric materials that can be etched by
the same acids used to etch the plastic package. This leads to
potential die damage after the plastic etch that may prevent
further analysis of the die.
BACKSIDE POLISH AND REPACKAGING
One solution to the problem of keeping devices operational
after exposing the die is to polish off the device backside and
use IR microscopy to look through the die. This procedure
includes the following four steps:
1.
2.
3.
4.
Mounting the device to a polishing stud
Polishing the package to expose the die backside
Mounting the polished package in a larger package
Wire bonding the polished die into a larger package
The device is mounted for planar polishing using wax
specially made for cross-sectioning (see figure 4) and the
package backside is polished off removing the top plastic,
leadframe paddle and exposing the backside of the die. This
procedure also exposes the ends of the bondwires around the
die (see figures 5 and 6). At this point, an IR microscope
may be used to inspect the circuitry through the GaAs
substrate. If bias is now needed, the exposed bondwires
could be contacted with microprobes or the following
procedure may be used to make permanent connections.
Backside of Die
1.6 mm
Exposed bondwires
Figure 6. SOT-23 package after backside polishing. With an
optical image in white light, the circuitry on the other side of the die
is not visible.
0.150 in
Figure 7. Optical image of an SOT-23 package after backside
polishing and repackaging in an open-cavity SSOP16 – 150 mil
package. This is the same die as pictured in figure 6.
Figure 4. SOT-23 package mounted on a polishing stud. A small
amount of wax is used to hold the package to the stud.
Material above the line is removed in the polish
Figure 5. SOT-23 package drawing showing level of polishing. Notice all
of the leadframe material is removed during the polish.
The polished package is then mounted into a larger, opencavity package and the exposed bondwires are wire-bonded
to the larger leadframe (see figures 7 and 8). The resulting
assembly is then easily socketed or mounted for electrical
operation, IR microscopy or photon-emission microscopy
(see example images in figures 9 and 10). The superior light
transmission properties of GaAs offer an advantage in using
these inspection techniques. Whereas emission microscopy
has been optimized for the light transmission properties of
silicon, the higher band-gap energy of GaAs makes it nearly
transparent to near infrared light. This method of rebonding
the polished device into a larger package has been described
in recent ISTFA proceedings [1], [2].
BACKSIDE POLISH AND GAAS ETCH
Ballbonds attached to
exposed wires of SOT-23
Backside of Die
Etching away the GaAs substrate from the backside of the
die is useful when the fault is potentially in the interconnect
or metals of the device. The ability to etch away the substrate
and stop on the base dielectric is a major advantage in failure
analysis over silicon devices. The procedure starts with the
same mounting and backside polishing to expose the die.
Then the device is placed in a GaAs etch to remove the
substrate. We use the following recipe for our GaAs etch:
6 parts H2SO4 (Sulfuric Acid)
1 part H2O2 (Hydrogen Peroxide)
1 part DI Water
Figure 8. SEM image of an SOT-23 package after backside
polishing and repackaging in an open-cavity SSOP16 – 150-mil
package.
Enough etch is prepared to cover the device in a small
beaker or test tube. The etch will take some time to remove
the substrate (from as little as ½ hour to as long as a day).
The GaAs etch takes longer as the mixture ages so it is
important to make a fresh GaAs etch for each use.
After the substrate has been removed, the remaining circuit
elements may be inspected (see figures 11 and 12).
FET
Inductor
The device circuitry may now be microprobed to find open
or shorted circuit elements. This technique has been used to
locate shorted capacitors and open metal vias (see example in
figures 13 and 14).
Figure 9. IR microscope image of backside of polished device.
Note the bottom of the device circuitry is visible through the GaAs
substrate.
Emission source
FET Gate
FET Source and Drain
Figure 10. High magnification (1000X) emission microscope
image of backside polished device. Note the resolution is good
enough to locate the emission source to the drain side of the input
gate.
Figure 11. Optical image of polished device after the GaAs
substrate has been etched away.
CONCLUSION
Three techniques have been described to facilitate circuit
inspection, troubleshooting and fault isolation of small
plastic-packaged GaAs RFICs. Two of the techniques
include the advantage of looking from the backside.
The first technique of topside acid decapsulation is the
quickest and easiest method to expose the die surface for
inspection. This is good for simple visual inspection or twopoint microprobing. However, it is difficult to fully bias a
device after decapsulating and some new dielectrics may be
etched by the acid, rendering the circuit inoperable.
Figure 12. High magnification (600X) optical image from the
bottomside of the polished device after the GaAs substrate has been
etched away. The ohmic contacts, gates and interconnect lines may
now be microprobed to troubleshoot failures.
The second technique looks through the GaAs substrate
with infrared or photon-emission microscopy. This technique
avoids the potential acid damage to the topside circuitry and
makes use of the superior light transmission properties of
GaAs. Full electrical operation is maintained, allowing
circuit debug and fault isolation. One disadvantage with this
method is the inability to easily perform in-circuit
microprobing.
The last technique uses a GaAs etch to remove the
substrate completely, allowing unique views of the process
metals. The gate and ohmic metals are exposed for easy
microprobing and the interconnect layers are relatively easy
to probe. The obvious disadvantage to this method is the
inability to operate the device since the FET channels are
missing.
Although these techniques are applicable to most plastic
packages, the small size of the SOT-23 package makes it
more difficult to successfully use topside acid decapsulation.
However, the small size actually facilitates the backside
techniques since it is easier to get an even polish of a smaller
package.
Figure 13. SEM image of a smaller die in a SOT-23 package after
a backside polish and GaAs etch. This circuit was microprobed and
when the fault was found, a Focused Ion Beam (FIB) was used to
cross-section through the failing metal via stack.
Bottom of circuit
Lowest metal layer
With the current trends toward smaller die sizes, heavier,
more complex metal stacks, and flip-chip technologies, these
analysis techniques will become more important. One
encouraging thought is the realization that much more
advanced techniques are already in use for complex silicon
devices and, for many of these techniques, GaAs has better
material properties. This will allow the GaAs industry to
apply these advanced techniques quickly as the need arises.
ACKNOWLEDGMENTS
Metal 1
The authors would like to thank TriQuint management for
their support to prepare this work.
Metal 2
REFERENCES
[1] J. Colvin, BGA and Advanced Package Wire to Wire Bonding for
Backside Emission Microscopy, ISTFA Proceedings, pp.365-375, 1999
[2] S. Liebert, Failure Analysis from the Back Side of a Die, ISTFA
Proceedings, pp.177-185, 2000
Figure 14. SEM image of the FIB cut made into the circuitry from
the backside after the GaAs substrate was removed. This is the
same device as pictured in figure 13. Although not visible at this
magnification, there is a discontinuity between the lowest metal
layer (top of picture) and the metal stack.