Design of a 10 Bit TSMC 0.25µm CMOS Digital to Analog Converter
J. Huynh, B. Ngo, M. Pham, and L. He
San Jose State University
Department of Electrical Engineering
San Jose, CA
lhe@email.sjsu.edu
Abstract
The goal of this project is to implement a 10-bit
segmented current steering TSMC 0.25µm CMOS
digital to analog converter. Binary coded 10-bit data
was input to the converter. The converter will convert
all combinations of ten bits from digital form into
correspondent “staircase” voltage levels. A low pass
filter placed after the output terminal of the converter is
necessary to make the voltage level smooth.
I. Introduction
High resolution digital analog converters (DACs) are
highly demanded in today’s wireless communication
applications. In data communication systems, when
signals are transmitted from one system to another
system, they are often handled in a digital manner.
However, the natural state of signals, such as voltage
and current appears in analog form [1]. Therefore, a
digital to analog converter (DAC) is needed to convert
digital signals into analog signals. The performance of a
digital to analog converter depends heavily on the
circuit architecture. The analog signals should be
recovered at the end of the receiver of the data
communication system. In this work, several digital to
analog architectures for DAC designs were discussed.
Those architectures included resistor string, R-2R ladder
networks, charge scaling, current steering, and
segmented current steering. Most of them could not
avoid glitches because of the change of more than one
digital input bit at a sampling time or can be suffered by
noise problems since resistors are noise sources.
Therefore, the DAC output does not result in the
expected value. Furthermore, the DAC chip is big in
term of area because passive components have large
area and their static characteristics are not good since
more differential nonlinearity (DNL) errors occur at
higher resolution. This DAC project is designed to
resolve the glitch energy, minimize the use of passive
components, and improve static characteristics. After
studying the advantages of segmented current steering
0-7695-2301-3/05 $20.00 (c) 2005 IEEE
architecture, the architecture was employed for this high
resolution DAC. The goal of this project is to
implement a 10-bit segmented current steering TSMC
0.25µm CMOS digital to analog converter. The
operation of the 10-bit DAC was briefly described.
Binary coded 10-bit data was input to the converter.
The converter will convert all combinations of ten bits
from digital form into correspondent “staircase” voltage
levels. A low pass filter placed after the output terminal
of the converter is necessary to make the voltage level
smooth. The strengths and drawbacks of each
architecture are evaluated by criteria such as integral
nonlinearity (INL), differential nonlinearity (DNL),
monotonicity, and chip area [1].
II. Circuit Design
In this project, the proposed 10-bit digital to analog
converter was designed, analyzed, implemented,
simulated, and layout in a 0.25-µm CMOS technology.
The power consumption of this 10-bit converter was
reduced by half compared to the 10-bit converter which
was done by Park, Cho, and Yoon [2]. Segmented
current steering architecture will be employed to design
this project which is a 10-bit segmented current steering
CMOS digital to analog converter. The 10-bit converter
consists of three digital to analog converters. The first
one is an 8-bit thermometer coded DAC. Eight inputs
of this DAC are 8 most significant bits (MSBs) of the
10-bit DAC. An 8-bit thermometer coded DAC is
compared. The second and the third DAC are two 1- bit
binary weighted DACs. In the matrix array of the 8-bit
DAC, there are 16 rows. The first row of this matrix
has 15 current sources with switches. There is a 4-bit
binary to thermometer decoder controlling switches. D
latch circuits synchronize data clocks. Each output of
the decoder works as a controlling signal for the current
source switch. Four least significant bits of the 8-bit
DAC are used as inputs to the decoder to control 15
current switches in the first row. All correct currents of
those 15 current sources, which correspond to an input
combination, are added up. This total current will be
multiplied with the load resistor to produce the correct
output voltage. Four most significant bits of the 8-bit
DAC are used as inputs to the decoder to control 15
rows of the matrix array. Inputs of 16 current switches
are connected together and controlled by the correct
output of the decoder. In the same fashion, all correct
currents will be added up and multiplied with the load
resistor to produce correct voltage outputs. Note that a
maximum number of current sources switching on in the
first row are 15 currents. This number is equivalent to
the digital input 00001111. Since this is a number 15 in
decimal, the thermometer code should be
111111111111111. Each number 1 represents of one
LSB current. For example, if 16 current sources are
needed, then the thermometer code should be
1111111111111111 and the binary inputs of an 8-bit
DAC should be 0001000. Then all 15 current switches
in the first row are off. All 16 current sources in the
second row are on since the 4 MSB binary to
thermometer decoder is triggered by the input 0001000.
The operation of the 8-bit DAC works in this manner.
a) Design of a Current Source Block
A current source block contains a D latch circuit that
determines whether to turn on a current switch or turn
off a current switch based on the signal R from the
output of the decoder.
The external clock is
synchronized by the D latch. The analog part of a
current source block consists of a cascoded current
source and a differential switch. The current source is
biased with a cascoded biasing current scheme [3].
PMOS devices are employed in the current source
because they reduce cross-talk. A current source also
includes buffers to drive a differential switch. To
reduce charge injection and capacitive feed-through,
dummy switches with their drains and sources shorted
are placed in series with a differential switch [4]. When
switch turns off, half the channel charge is injected
toward a dummy switch. Therefore, the size of a
dummy switch is one-half that of the desired switch. A
clock, which is inverted the clock of a differential
switch, is applied to the dummy switch to induce a
channel. When the dummy switch is off, it will inject
half of its charge in both directions. Since the drain and
source are shorted and a differential switch is on, the
charge from the dummy switch will be injected onto the
low impedance source. As a result, charge injection of
the dummy switch will not affect the value of the
voltage on load capacitor.
b) Design of the Two-Stage Operational
Amplifier
The purpose of two stage operational amplifier in the
biasing current scheme is to provide a negative feedback
loop to stabilize the biasing current. When the voltage
drop across resistor 61.8K attempts to go up, then this
voltage drop will feed into the negative terminal of the
two stage op-amp. Therefore, the voltage at the output
of the op-amp goes down. As a result, the voltage drop
across the resistor will go down. Therefore, the biasing
current will be stable. However, its gain is reduced
because of the small mobility of PMOS device. Based
on the specifications of the op-amp and the formulas
[5], transistor sizes are calculated. In order to avoid
system offset, the transistor sizes are chosen to satisfy
the condition:
W
 L
  N2
W
 L
  N0
2
W
 L
  P1
W
 L
  P0
c) Design of the Bandgap Reference Voltage
Circuit
The bandgap reference voltage is used to provide the
temperature invariant voltage for an integrated circuit.
As temperature increasing, VBE is dropped by 2mV per
degree C; however, thermal voltage is increased by
0.085mV per degree C. Therefore, the bandgap
reference voltage is constant with temperature variation.
The basic bandgap equation is
Vref
Vbe + KVPTAT
Vbe is the forward biased voltage of a diode. It is a
negative temperature dependent term.
d) Design of Different Cascoded Current
Sources
This cascoded current cell provides 1LSB current for
a 10-bit DAC. It has the same transistor size as the size
of a biasing current transistor. With L=300nm, it is
suffered from current mismatch. However, it has small
area. The width of this cascoded current source will be
W = 5µm for the initial design. However, after running
simulation, mismatch error is big. Therefore, the width
is changed to 20µm according to the change of the
width of the biasing current transistor.
e) Design the Analog Output Voltage of the 10Bit DAC
The cascoded current source limits its output
voltage [6], but it has high output impedance which can
improve signal free dynamic range. In addition, the
saturation region of each cascoded device must be
preserved. The TSMC 0.25-µm CMOS process allows
the use of 2.5V supply rail to rail. Realizing these
limitations, one output step voltage is designed for
1.5mV. A 10-bit DAC will decode 210 combinations
and produce ( 210-1) or 1023 output voltage steps.
Therefore, the full scale voltage (VFS) of the output is
VFS = 1023x1.5mV/step = 1.5345V. With power
supply 2.5 V and such full scale voltage, the remaining
voltage is .96655V. This amount of the voltage
guarantees the saturation of a cascoded device. The
value of the load resistance at the output of DAC is
calculated by
R
VLSB
1.5m
ILSB
20uA
A low pass filter is needed after the output of a 10 bit
DAC. The function of low pass filter is to filter out
noises at high frequencies.
a) Design of a Low Pass Filter
A low pass filter is needed after the output of a 10
bit DAC. The function of low pass filter is to filter out
noises at high frequencies. Figure 2 shows a low pass
filter with the 3dB bandwidth is 2.1GHz.
75Ohm
Figure 1 showed the op-amp in biasing circuit [2].
Figure 2. A low pass filter
b) Design of a 4-Bit Binary to Thermometer
Decoder
Figure 1. The use of an op-amp in biasing circuit
III. Static Characteristics and Dynamic
Characteristics of the DAC
Static characteristics include integral nonlinearity
(INL), differential nonlinearity (DNL), dynamic range,
and signal to noise ratio (SNR). Dynamic
characteristics are gain error and conversion rate.
Integral nonlinearity (INL) is defined as the maximum
difference between the actual output values and a
reference straight line drawn through the first and last
output values [5]. Differential nonlinearity (DNL) is
defined as the difference between the actual increment
height of a transition and an ideal increment height [5].
Dynamic range (DR) is the ratio of the full scale range
to the smallest difference that can be resolved
The thermometer decoder helps the high resolution
converter getting rid of potential glitches and then
improves nonlinearity. For this purpose, the 4-bit
binary to thermometer decoder is designed.
In
thermometer code, one bit is changed at a given time.
Switch controlling have benefited from this property of
thermometer code. Four inputs of the decoder are
binary, but outputs are thermometer codes. In other
words, this is a code converter. Studying the above
table, it is seen that there is one bit changing when the
output changes from one state to another state.
Boolean algebraic equations are obtained using
Karnaugh-map simplification. In CMOS digital circuit
design, it is not convenient to design an AND or OR
logic. Therefore, DeMorgan’s Law is used for the
decoder implementation.
All Boolean algebraic
equations of the decoder will be complemented by
DeMorgan’s Law. Three logics NAND, NOR, and
NOT are used to implement the decoder. Although
there are 4 inputs, there are only 15 outputs. The first
combination 0000 produces no output. The frequency
of the decoder is about 80MHz. This frequency should
be higher than the speed of the DAC in order to handle
input data.
c) Design of a D Latch Circuit
Each pair of current switches in a cascoded current
cell is driven by a D latch circuit. The function of the D
latch is to synchronize the external clock [7]. For
example, at a given time, three switches are on
simultaneously. Output of the D latch will force those
three switches closing at the same time. Implementing
the D latch includes transmission gates and inverters.
The operation of level-sensitive D latch is controlled
by the clock signal CK. A value of CK = 1 accepts the
input D into the circuit. Switching the control to a
value of CK = 0 allows the circuit to hold the value.
When CK = 1, NMOS transistor of transmission gate
will act as a closed switch, while PMOS transistor of
transmission gate is open. The value of the input data
D enters the circuit and is available at the outputs Q
and QB. Because the output change in response to a
change in input D, the latch is said to be transparent.
The hold operation occurs when CK = 0. The latch
circuit will form a feedback loop between the inverters.
This loop is a bi-stable circuit to store either 1 or 0 [8].
A number of inverters and buffers are used in this
project. Buffers are implemented by two inverters.
They are tested at high frequency. The purpose of
buffers is to drive loads. The function of inverter is
inversion. All transistors of logic gates are sized based
on the dimensions of this inverter.
d) Designs of Inverters and Buffers
A number of inverters and buffers are used in this
project. Buffers are implemented by two inverters.
They are tested at high frequency. The purpose of
buffers is to drive loads. The function of inverter is
inversion. Figure 3 shows the basic inverter. Its size is
standard. All transistors of logic gates are sized based
on the dimensions of this inverter.
e) Clock Issues
In order to avoid interconnect-induced clock skew,
the H-tree structure for clock distribution lines is
employed. The H-tree pattern is one that replicates the
shape of a letter “H” in the interconnect patterning. If
an input signal is applied to the center of the “H” and
the outputs are taken at the tips, then every path length
is the same. This means that the delay between the
input and each output is identical. The clock driver is
placed in the center of the DAC and nested H-trees are
used to distribute the signal to various points on the
chip. If the receivers are placed at the tips of H-tree
line, then all received signals are in phase [8].
We described the operation of the 10 bit segmented
current steering digital to analog converter as well as
its architecture. The “segmented current steering”
architecture used for this project is slightly modified
compared to “standard segmented current steering”
architecture. The difference between the architecture
of this project and the segmented current steering
architecture is that decoding circuit is not used for each
current source block. The key advantage of segmented
current steering architecture is that nonlinearity is
improved for high resolution applications. The bandgap circuit is designed with a fixed voltage of 1.196V.
Cascoded current sources and differential switches are
main parts for the DAC. Area of the DAC is big due to
the matrix array. A 4-bit binary to thermometer
decoder plays an important role in switch controlling.
D latch synchronizes clock. Monotonicity of the DAC
is guaranteed by current steering architecture.
To
prepare for testing characteristics, definitions for static
and dynamic characteristics are discussed. Clock skew
is reduced using H-tree structure. With these design
ideas, circuit implementations will be presented in the
next chapter.
IV.
Project
Implementation
Performance Results
Figure 3. A standard inverter Designed for this work
and
This section describes implementations and
simulation results for sub-circuits in the 10 bit DAC.
Circuit simulation is performed after the
implementation of a sub-circuit in the DAC. The
design tool employed for creating circuits is the
Cadence IC Design program. The partition of a single
DAC is used for the purpose of debugging. It is easier
to run simulation for a single sub-circuit and see
whether correct result or wrong result. If errors occur,
then they are found and debugged quickly. After
performing functionally, all sub-circuits are integrated
into a single DAC. If sub-circuits of the DAC work
properly, then the DAC possibly works. This test
methodology saved time when this project was in
progress. Based on design ideas stated before, circuits
for analog part and digital part are implemented. Each
circuit is tested using SpectreS circuit simulator in
Cadence IC Design program. Plots or graphs for the
desired outputs are obtained after the termination of
simulation. Extracted data from the output log of the
SpectreS simulator will be entered MatLab program to
calculate and plot characteristics of the DAC. The
performance results are from pre-layout tests. Circuit
simulator is set up to run at room temperature.
10 bit DAC is 50f. Each digital input is set 20ns for
the delay time (equal half a period of the previous
input). In addition, each input has 100ps for rise time
and 100ps for fall time. Performance results of the 10
bit DAC are met specifications as expected. However,
due to the excess of account quota, the simulation
result shows up to 2.5µs instead of 20.48µs. Output
data from the SpectreS Output Log of the project are
extracted after simulation. With the aid of the MatLab
program, the transfer curve of the 10-bit DAC is
drawn. Note that inputs are translated from digital
combinations into decimal numbers for the purpose of
convenience. In addition, the MatLab program is used
to draw the plot for gain error calculation, integral
nonlinearity (INL), and differential nonlinearity
characteristics for the 10-bit DAC. One of static
conversion errors of the DAC is gain error. Gain error
is defined as the difference between the ideal slope and
the actual slope measured at the rightmost jump. From
the worst case for gain error plot, the worst case of the
gain error for the 10-bit DAC at 0.002V is about
1.3LSB. This gain error can be represented of the
integral nonlinearity. The gain error is measured at the
high resolution. From this plot, it is shown that the
thermometer coded DAC helps to improve the integral
nonlinearity at the high value of resolution. For this
project, gain error does not depend on the operational
amplifier since the current steering architecture is
employed. Integral nonlinearity error of the 10-bit
DAC is one of the DAC characteristics. It measures
vertically the difference between the actual resolution
characteristic and the ideal resolution characteristic.
Differential nonlinearity (DNL) error of the 10-bit
DAC is another characteristic of the DAC. It measures
the difference between two adjacent steps with the
ideal voltage step.
a) Test Bench for the 10 Bit DAC
Figure 4. The completed 10 bit segmented current
steering TSMC 0.25µm CMOS D/A converter
The test bench includes the biasing current circuit,
the 10 bit DAC, the low pass filter, and the bandgap
circuit. The period of the clock is 20ns which is
equivalent to 50MHz. Data period is doubled the clock
period. The clock needs to have a big buffer in order
to drive big loads. The function of the low pass filter is
to filter out noises at high frequencies and it also makes
the output of the DAC smooth. An output load of the
Figure 5. Test bench for the 10 bit DAC
This test bench includes the biasing current circuit,
the 10 bit DAC, the low pass filter, and the bandgap
circuit. The period of the clock is 20ns which is
equivalent to 50MHz. Data period is doubled the clock
period. The clock needs to have a big buffer in order
to drive big loads. The function of the low pass filter is
to filter out noises at high frequencies and it also makes
the output of the DAC smooth. An output load of the
10 bit DAC is 50f. Each digital input is set 20ns for
the delay time (equal half a period of the previous
input). In addition, each input has 100ps for rise time
and 100ps for fall time. Performance results of the 10
bit DAC are met specifications as expected. However,
due to the excess of account quota, the simulation
result shows up to 2.5µs instead of 20.48µs.
V. Conclusions
Design of a 10-bit segmented current steering
TSMC 0.25-µm CMOS digital to analog converter
(DAC) was done in this project. The DAC performed
well following the specifications. Each output step
voltage is about 1.5mV within +/-2 LSB tolerance.
The characteristics of the DAC are also tested and their
results meet the specifications within a certain amount
of tolerance. The power consumption of the DAC is
about 52mW. The 1 LSB cascoded current cell
conducts 20µA as expected. The 8-bit DAC, which
contains the current source matrix arrays, was
constructed and tested. This is the main part of the
DAC. The analog part of the DAC is the cascoded
current biasing circuit which creates and biases
currents for the current source cells.
The two stage operational amplifier and the 1.196V
reference voltage circuit were designed to give the
reference voltage for the DAC. The layout of the DAC
was also done on ahead of schedule. The post
extraction simulation of each current source block
determines whether the current source has a correct
result or not. The layout for the analog part was
completed except for the bandgap circuit.
VI. References
[1] Alan B. Grebene, Bipolar and MOS Analog Integrated
Circuit Design. Wiley-Interscience. 1984.
[2]. S.Y. Park, H. H. Cho, and K. H. Yoon, “A 3.3V-110MHz
10-Bit CMOS Current Mode DAC,” CATS, 2001.
[3] T. Miki, Y. Nakamura, M. Nakamura, Y. Akasaka, and Y.
Horiba, “An 80MHz 8 bit CMOS D/A Converter,” IEEE J.
Solid-State Circuits, pp.983-998, Dec.1986.
[4] Jacob R. Baker, Harry W. Li, and David E. Boyce, CMOS
Circuit Design, Layout, and Simulation. IEEE,
Press. Prentice-Hall, 1998.
[5] Phillip E. Allen and Douglas R. Holberg, CMOS Analog
Circuit Design. Second Edition. Prentice-Hall, 2002.
[6] Ki-Hong Ryu, “A 3.3V 12-Bit High Speed Current Cell
Matrix CMOS DAC,” JKPS, pp.127-131, July 2001.
[7] Thomas L. Floyd, Digital Fundamentals. Third Edition.
Merrill. 1986.
[8] J.P. Uyemura, CMOS Logic Circuit Design. Kluwer
Academic Publishers, 2002.