TSMC 0.18µm Process 1.8-Volt
SAGE-X TM Standard Cell Library
Databook
October 2001
Release 3.1
 1993-2001 Artisan Components, Inc. All rights reserved.
Printed in the United States of America.
DB-SX-TSM003-3.1/18
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Table of Contents
Preface
Release History ............................................................................................. viii
Customer Support ......................................................................................... viii
Introduction
Global Parameters .............................................................................................9
Specifications ............................................................................9
Propagation Delay ...................................................................10
Derating Factors ......................................................................11
Delay Calculation ....................................................................11
Timing Constraints .................................................................12
Setup Time ..............................................................................12
Hold Time ...............................................................................13
Recovery Time ........................................................................14
Minimum Pulse Width ............................................................14
Power Dissipation ...................................................................15
Power Calculation ...................................................................16
Power-Rail Strapping ..............................................................18
Adding Routing Channels .......................................................19
Special Cells ....................................................................................................20
Antenna-Fix Cell .....................................................................20
Fill Cells ..................................................................................20
Low-Power (XL) Cells ...........................................................21
TIEHI/LO Cells ......................................................................21
Delay Cells ..............................................................................21
1. Cell Name ...........................................................................21
2. Cell Description ..................................................................21
3. Function Table ....................................................................22
4. Logic Symbol ......................................................................22
5. Cell Size ..............................................................................22
6. Functional Schematic ..........................................................22
7. Drive Strength .....................................................................22
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
Table of Contents
8. AC Power ............................................................................22
9. Delay ...................................................................................23
10. Timing Constraints ...........................................................23
11. Pin Capacitance .................................................................23
Base Cells
ADDF ..............................................................................................................29
ADDFH ...........................................................................................................31
ADDH .............................................................................................................33
AND2 ..............................................................................................................35
AND3 ..............................................................................................................37
AND4 ..............................................................................................................39
AOI21 .............................................................................................................42
AOI211 ...........................................................................................................44
AOI22 .............................................................................................................46
AOI221 ...........................................................................................................48
AOI222 ...........................................................................................................50
AOI2BB1 ........................................................................................................52
AOI2BB2 ........................................................................................................54
AOI31 .............................................................................................................56
AOI32 .............................................................................................................58
AOI33 .............................................................................................................60
BUF .................................................................................................................62
CLKBUF .........................................................................................................64
CLKINV .........................................................................................................66
DFF .................................................................................................................68
DFFHQ ...........................................................................................................70
DFFN ..............................................................................................................72
DFFNR ............................................................................................................74
DFFNS ............................................................................................................76
DFFNSR .........................................................................................................78
DFFR ..............................................................................................................81
DFFRHQ .........................................................................................................83
DFFS ...............................................................................................................85
DFFSHQ .........................................................................................................87
DFFSR ............................................................................................................89
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
Table of Contents
DFFSRHQ ......................................................................................................92
DFFTR ............................................................................................................94
DLY1 ..............................................................................................................96
DLY2 ..............................................................................................................98
DLY3 ............................................................................................................100
DLY4 ............................................................................................................102
EDFF .............................................................................................................104
EDFFTR ........................................................................................................106
HOLD ...........................................................................................................108
INV ...............................................................................................................110
JKFF ..............................................................................................................112
JKFFR ...........................................................................................................114
JKFFS ...........................................................................................................116
JKFFSR .........................................................................................................118
MX2 ..............................................................................................................121
MX4 ..............................................................................................................123
MXI2 .............................................................................................................125
MXI4 .............................................................................................................127
NAND2 .........................................................................................................129
NAND2B ......................................................................................................131
NAND3 .........................................................................................................133
NAND3B ......................................................................................................135
NAND4 .........................................................................................................137
NAND4B ......................................................................................................139
NAND4BB ....................................................................................................141
NOR2 ............................................................................................................143
NOR2B .........................................................................................................145
NOR3 ............................................................................................................147
NOR3B .........................................................................................................149
NOR4 ............................................................................................................151
NOR4B .........................................................................................................153
NOR4BB .......................................................................................................155
OAI21 ...........................................................................................................157
OAI211 .........................................................................................................159
OAI22 ...........................................................................................................161
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
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OAI221 .........................................................................................................163
OAI222 .........................................................................................................165
OAI2BB1 ......................................................................................................167
OAI2BB2 ......................................................................................................169
OAI31 ...........................................................................................................171
OAI32 ...........................................................................................................173
OAI33 ...........................................................................................................175
OR2 ...............................................................................................................177
OR3 ...............................................................................................................179
OR4 ...............................................................................................................181
RSLAT ..........................................................................................................183
RSLATN .......................................................................................................185
SDFF .............................................................................................................187
SDFFHQ .......................................................................................................189
SDFFN ..........................................................................................................191
SDFFNR .......................................................................................................193
SDFFNS ........................................................................................................197
SDFFNSR .....................................................................................................201
SDFFR ..........................................................................................................204
SDFFRHQ ....................................................................................................207
SDFFS ...........................................................................................................210
SDFFSHQ .....................................................................................................213
SDFFSR ........................................................................................................216
SDFFSRHQ ..................................................................................................219
SDFFTR ........................................................................................................222
SEDFF ..........................................................................................................225
SEDFFHQ .....................................................................................................228
SEDFFTR .....................................................................................................231
TBUF ............................................................................................................234
TBUFI ...........................................................................................................236
TIEHI ............................................................................................................238
TIELO ...........................................................................................................239
TLAT ............................................................................................................240
TLATN .........................................................................................................242
TLATNR .......................................................................................................244
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
Table of Contents
TLATNS .......................................................................................................246
TLATNSR .....................................................................................................248
TLATR ..........................................................................................................251
TLATS ..........................................................................................................253
TLATSR .......................................................................................................255
TTLAT ..........................................................................................................258
XNOR2 .........................................................................................................260
XOR2 ............................................................................................................262
Synthesis Optimized Arithmetics
AFHCIN ........................................................................................................266
AFHCON ......................................................................................................268
AFCSHCIN ...................................................................................................270
AFCSHCON .................................................................................................273
AHHCIN .......................................................................................................276
AHHCON .....................................................................................................278
BENC ............................................................................................................280
BMX .............................................................................................................283
CMPR22 .......................................................................................................286
CMPR32 .......................................................................................................288
XOR3 ............................................................................................................290
XNOR3 .........................................................................................................292
Advanced Arithmetics
CMPR42 .......................................................................................................296
Register File Cells
RF1R1W .......................................................................................................302
RF2R1W .......................................................................................................305
RFRD ............................................................................................................308
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
Preface
Release History
This section contains the release history for the TSMC 0.18µm Process
1.8-Volt SAGE-X Standard Cell Library Databook. For more detailed
technical information, please contact Artisan Customer support at
support@artisan.com.
Release
Number
Part Number
Date of Release
DB-SX-TSM003-1.0/18
1.0
March 2000
DB-SX-TSM003-2.2/18
2.2
September 2000
DB-SX-TSM003-3.0/18
3.0
July 2001
DB-SX-TSM003-3.1/18
3.1
October 2001
Updates
• Initial Release
• Document updated
• A*CSH* cells redesigned
• Update adder cells
Customer Support
For all customer service or technical support questions, please visit the
Artisan Components Web site at www.artisan.com and click on Customer
Support.
You may also contact Artisan by telephone or email, using the following
information:
■ United States and North America 877-ARTILIB (877-278-4542)
■ International
408-548-3298
■ Email
support@artisan.com
TSMC 0.18µm Process 1.8-Volt SAGE-X Standard Cell Library Databook
viii
Introduction
Artisan’s SAGE-XTM standard cell library builds upon our SAGE architecture,
producing the optimum combination of high-density with high-performance.
The cell line-up is derived from extensive customer design, synthesis, and
place-and-route benchmark analysis. Library optimization is achieved by
carefully matching the library functions and drive strengths to leading
synthesis and place-and-route tools, producing superior RTL-to-GDSII
results.
How This Book Is
Organized
This introduction is organized into three sections:
•
•
•
Global Parameters provides an overview of parameters specific to your
SAGE-X library.
Special Cells details the types of special cells you will find included in
the library.
Reading the Standard Cell Datasheet describes what you will find in
each datasheet.
Datasheets for each cell in this lirbary are provided after the introduction. The
datasheets are included in alphabetical order within the following catgories:
•
•
•
•
•
Global
Parameters
Base Cells
Custom Cells (if your project includes these)
Advancec Arithmetics
Register File Cells
Symthesis Optimized Arithmetics
This section specifies global parameters for the TSMC 0.18µm Process
1.8-Volt SAGE-X Standard Cell Library Databook. It covers physical
specifications, electrical specifications, derating factors, propagation delay
calculation, timing constraints, power calculation, and power-rail strapping.
TSMC 0.18µm Process 1.8-Volt SAGE-X Standard Cell Library Databook
9
Introduction
Physical Specifications
Table 1 shows the physical design specifications of this SAGE-X Standard Cell
Library.
Table 1. Physical Specifications
Drawn Gate Length (µm)
0.18
Layers of Metal
4, 5, or 6
Layout Grid (µm)
0.005
Vertical Pin Grid (µm)
0.56
Horizontal Pin Grid (µm)
0.66
Cell Power and Ground Rail Width (µm)
0.8
In this library, all pins are located on the vertical and horizontal pin grids. Most
place-and-route tools work more efficiently with all pins on grids, and some tools
even require it.
This library also supports designs with 4, 5, or 6 layers of metal. The designer
may need to change the design rules in the technology file, because the top-level
metal has a greater minimum width and greater minimum spacing requirement.
See "Design Rule 0.18µm LOGIC Salicide 1.8V/3.3V Process" design rule
manual. The designer must define these correctly for the place-and-route tool.
Table 2 describes the electrical specifications for this library.
Table 2. Electrical Specifications
Parameter
Minimum
Maximum
DC Supply Voltage (Vdd)
1.62 V
1.98 V
Junction Temperature
0 oC
125oC
Table 3 shows the derating factors for this SAGE-X Standard Cell Library.
Table 3. Derating Factors
KProcess (slow)
1.293
KProcess (typical)
1.000 (by definition)
KProcess (fast)
0.781
KVolt (1.8V to 1.62V)
-0.731/V
KVolt (1.8V to 1.98V)
-0.511/V
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Introduction
Table 3. Derating Factors
KProcess (slow)
o
1.293
o
KTemp (25 C to 0 C)
o
0.00137/˚C
o
KTemp (25 C to125 C)
0.00123/˚C
Propagation Delay
The propagation delay through a cell is the sum of the intrinsic delay, the loaddependent delay, and the input-slew dependent delay. Delays are defined as the
time interval between the input stimulus crossing 50% of Vdd and the output
crossing 50% of Vdd. Figure 1 illustrates propagation delay.
Figure 1. Propagation Delay
Input
50% Vdd
delay
Output
50% Vdd
Factors that affect propagation delays include: temperature, supply voltage,
process variations, fanout loading, interconnect loading, input-transition time,
input-signal polarity, and timing constraints (see below). The timing models
provided with this library include the effects of input-transition time on
propagation delays. Also, all timing models use a table lookup method to
calculate accurate timing. To simplify calculations, the standard cell datasheets
provide all timing numbers for an input slew of 0.03ns and a linearized load
factor, Kload, which is not as accurate as the timing models. All cells have been
characterized with a fully populated metal2 (0.66µm horizontal pitch) and
metal3 (0.56µm vertical pitch) routing grid across the entire cell layout.
The SAGE-X Standard Cell Library may contain negative propagation delays.
Although most third-party verification tools can handle negative propagation
delays, some tools will turn negative delays into a zero value.
TSMC 0.18µm Process 1.8-Volt SAGE-X Standard Cell Library Databook
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Introduction
Derating Factors
Derating factors are coefficients that the typical process characterization data is
multiplied by to arrive at timing data that reflects appropriate operating
conditions. The derating factor table on page 10 provides derating factors for
variations in process case, temperature, and voltage.
Derating factors are derived by averaging the performance of many different
cells in the library. A particular combination of cells may perform better or
worse than indicated by these derating factors.
Delay Calculation
Using the delay data in the datasheets (tintrinsic, Kload, and Cload) and the delay
derating factors, the estimated total propagation delay is
tTPD =
(KProcess) • [1+(KVolt • ∆Vdd)] • [1+(KTemp • ∆T)] • ttypical
ttypical= tintrinsic + (Kload • Cload)
where:
tTPD
=
total propagation delay (ns);
ttypical
=
delay at typical corner—1.8V, 25 oC, typical process (ns);
tintrinsic =
delay through the cell when there is no output load (ns);
Kload
=
load delay multiplier (ns/pF);
Cload
=
total output load capacitance (pF);
KProcess =
process derating factor, where process is slow, typical, or fast;
KVolt
=
voltage derating factor (/V);
∆Vdd
=
Vdd —1.8V;
KTemp
=
temperature derating factor (/oC);
∆T
=
junction temperature — 25 oC.
Timing Constraints
Timing constraints define minimum time intervals during which specific signals
must be held steady in order to ensure the correct functioning of any given cell.
Timing constraints include: setup time, hold time, recovery time, and minimum
pulse width.
TSMC 0.18µm Process 1.8-Volt SAGE-X Standard Cell Library Databook
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Introduction
The sequential-cell timing models provided with this library include the effects
of input-transition time and data-signal and clock-signal polarity on timing
constraints. To simplify calculations, the datasheets specify timing constraint
values for 0.03ns data slew and 0.03ns clock slew. Other factors that affect
timing constraints include temperature, supply voltage, and process case
variations. All cells have been characterized with a fully populated metal2
(0.66µm horizontal pitch) and metal3 (0.56µm vertical pitch) routing grid across
the entire cell layout.
Timing constraints can affect propagation delays. The intrinsic delays given in
the datasheets are measured with relaxed timing constraints (longer than
necessary setup times, hold times, recovery times, and pulse widths). The use
of shorter timing constraint intervals may increase delay. Each cell is considered
functional as long as the actual delay does not exceed the delay given in the
datasheets by more than 10%.
Setup Time
The setup time for a sequential cell is the minimum length of time the data-input
signal must remain stable before the active edge of the clock (or other specified
signal) to ensure correct functioning of the cell. The cell is considered functional
as long as the delay for the output reaching its expected value does not exceed
the reference delay (measured with a large setup time) by more than 10%. Setupconstraint values are measured as the interval between the data signal crossing
50% of Vdd and the clock signal crossing 50% of Vdd. For the measurement of
setup time, the data input signal is kept stable after the active clock edge for an
infinite hold time. Figure 2 illustrates setup time for a positive-edge-triggered
sequential cell.
Figure 2. Setup Time
Input
50% Vdd
setup
Clock
50% Vdd
TSMC 0.18µm Process 1.8-Volt SAGE-X Standard Cell Library Databook
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Introduction
Hold Time
The hold time for a sequential cell is the minimum length of time the data-input
signal must remain stable after the active edge of the clock (or other specified
signal) to ensure correct functioning of the cell. The cell is considered functional
as long as the delay for the output reaching its expected value does not exceed
the reference delay (measured with a large hold time) by more than 10%.
Hold-constraint values are measured as the interval between the clock signal
crossing 50% of Vdd and the data signal crossing 50% of Vdd. For the
measurement of hold time, the data input signal is held stable before the active
clock edge for an infinite setup time. Figure 3 illustrates hold time for a
positive-edge-triggered sequential cell.
Figure 3. Hold Time
Input
50% Vdd
hold
Clock
50% Vdd
TSMC 0.18µm Process 1.8-Volt SAGE-X Standard Cell Library Databook
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Introduction
Recovery Time
Recovery time for sequential cells is the minimum length of time that the activelow set or reset signal must remain high before the active edge of the clock to
ensure correct functioning of the cell. The cell is considered functional as long
as the delay for the output reaching its expected value does not exceed the
reference delay (measured with a large recovery time) by more than 10%.
Recovery constraint values are measured as the interval between the set or reset
signal crossing 50% of Vdd and the clock signal crossing 50% of Vdd. For the
measurement of recovery time, the set or reset signal is held stable after the
active clock edge for an infinite hold time. Figure 4 illustrates recovery time.
Figure 4. Recovery Time
Set or
Reset
50% Vdd
recovery
Clock
50% Vdd
Minimum Pulse Width
Minimum pulse width is the minimum length of time between the leading and
trailing edges of a pulse waveform. Minimum pulse width high (minpwh) is
measured as the interval between the rising edge of the signal crossing 50% of
Vdd and the falling edge of the signal crossing 50% of Vdd. Minimum pulse
width low (minpwl) is measured as the interval between the falling edge of the
signal crossing 50% of Vdd and the rising edge of the signal crossing 50% of
Vdd. Figure 5 illustrates minimum pulse width.
TSMC 0.18µm Process 1.8-Volt SAGE-X Standard Cell Library Databook
15
Introduction
Figure 5. Minimum Pulse Width
minpwh
Signal
50% Vdd
50% Vdd
minpwl
Minimum pulse width is defined to be 0.50ns for all set/reset pins (SN, RN) and
0.18ns for all clock pins (G, GN, CK, CKN). These are the largest minimum
pulse widths measured from all the cells in the library. An input pulse of shorter
duration will produce unpredictable results.
Power Dissipation
The SAGE-X Standard Cell Library is designed to dissipate only AC power,
except for the small reverse-bias leakage currents which are normally present in
all CMOS circuits.
The power dissipation internal to a cell when a given input switches is primarily
dependent upon the cell design itself. The power dissipation of a complete
design, or part of a design, using cells from the SAGE-X Library is primarily a
function of the switching frequency of the design’s internal nets. These nets
include the inputs and outputs of each cell and the capacitive load associated
with the outputs of each cell.
The SAGE-X Library datasheets contain both an AC power table which
documents the internal energy consumption of each cell and a pin capacitance
table which gives input-pin capacitance data used to compute output loading.
This information, coupled with design-specific information, can be used to
estimate the total power dissipation of a cell within a design.
The AC power tables specify the amount of energy consumed within a cell (µW/
MHz) when the corresponding pin changes state at 25 oC, V, and typical process.
The energy data in the tables were measured for an input slew of 0.03ns and no
loading at the outputs.
For combinatorial cells, energy values are provided for only input pins. The
energy value for each input pin is the average of energies associated with the
input transitions which result in an output transition.
TSMC 0.18µm Process 1.8-Volt SAGE-X Standard Cell Library Databook
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Introduction
For sequential cells, the energy associated with each input pin is the average
energy of those input transitions which do not result in an output transition. The
energy associated with the output pin of a sequential cell is the average energy
of all cases where an output transition is the result of a clock-input transition,
minus the energy associated with the clock input pin. In the event that a
sequential cell has multiple outputs, all output energy data will be associated
with only one output pin.
Power Calculation
Power dissipation is dependent upon the power-supply voltage, frequency of
operation, internal capacitance, and output load. The power dissipated by each
cell is:
x
Pavg=
∑
n=1
y
( E in • f in ) +
∑  C on • Vdd
n=1
2
1
• --- f on + E os • f o1

2
where:
Pavg
=
average power (µW);
x
=
number of input pins;
Ein
=
energy associated with the nth input pin (µW/MHz);
fin
=
frequency at which the nth input pin changes state during the
normal operation of the design (MHz);
y
=
number of output pins;
Con
=
external capacitive loading on the nth output pin, including the
capacitance of each input pin connected to the output driver, plus
the route wire capacitance, actual or estimated (pF);
Vdd
=
operating voltage = 1.8V;
fon
=
frequency at which the nth output pin changes state during the
normal operation of the design (MHz);
Eos
=
energy associated with the output pin for sequential cells only
(µW/MHz).
The switching frequency of inputs and outputs of a particular cell in a design
can be obtained from a gate-level logic simulator, for example Verilog, by
applying typical input stimuli and measuring the activity on each node of
interest. The total average power for the design can be computed by adding the
average power for each cell.
TSMC 0.18µm Process 1.8-Volt SAGE-X Standard Cell Library Databook
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Introduction
For example, for a DFFXL cell with clock switching at 133MHz, input and
output pins switching at 20MHz, an external capacitive loading on the output
pin of 0.02pF, and using the power table in the DFF datasheet shown on page
26, the power dissipated by the DFFXL is given by the equation:
x
Pavg
=
y
∑ ( E in • f in ) + ∑  C on • Vdd
n=1
2
1
• --- f on + E os • f o1

2
2
1
• --- f on + E os • f o1

2
n=1
Substituting,
x
=2;
Ei1 = 0.00306 µW/MHz;
Ei2 = 0.0335 µW/MHz;
fi1 = 20 MHz;
fi2 = 133 MHz;
y
=2;
Co1 =0.02 pF;
Co2 =0.02 pF;
Vdd= 1.8V;
fo1 =20 MHz;
fo2 =20 MHz;
Eos =0.0260 µW/MHz
we have:
2
Pavg
=
n=1
Pavg
=
2
∑ ( E in • f in ) + ∑  C on • Vdd
n=1
( E i1 • f i1 ) + ( E i2 • f i2 )
2 1
2 1
+  C o1 • 1.8 • --- f o1 +  C o2 • 1.8 • --- f o2

2  
2 
+ ( E os • f o1 )
TSMC 0.18µm Process 1.8-Volt SAGE-X Standard Cell Library Databook
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Introduction
Pavg
=
( 0.0306 • 20 ) + ( 0.0335 • 133 )
1
1
+  0.02 • 3.24 • --- ( 20 ) +  0.02 • 3.24 • --- ( 20 )

 

2
2
+ ( 0.0260 • 20 )
Pavg
=
6.89 µW
Power-Rail Strapping
The designer must determine the required amount of vertical power-rail
strapping to satisfy all requirements imposed by the design methodology for a
given design. Power-rail strapping should be sized small enough to optimize
standard cell height and maximize router efficiency, yet it must be large enough
to provide sufficient power to the cells.
The following guidelines provide a rough estimate with many simplifying
assumptions. For a given module design, the designer can estimate the amount
of vertical power-rail strapping that is required to fulfill electromigration
requirements.
Given:
Iavg
=
total average current for the module, calculated from previous
section (mA);
wm1
=
VSS/VDD metal1 wire width (µm), see Physical Specifications;
r
=
number of rows in module;
dm1
=
maximum metal1 current density allowed for the process
(mA/µm);
dm2
=
maximum metal2 current density allowed for the process
(mA/µm);
Im1
=
maximum current that can be supported by all horizontal metal1
wires (mA);
Istrap
=
total current that must be supported by the vertical metal2
strapping (mA);
wm2
=
metal2 wire width required for vertical strapping (µm);
c
=
minimum number of metal2 straps;
TSMC 0.18µm Process 1.8-Volt SAGE-X Standard Cell Library Databook
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Introduction
we have:
Im1
=
w m1 • r • 2 • d m1 ,
where multiplying by 2 assumes metal1 wires are supplied from both ends;
Istrap
=
( I avg – I m1 )
---------------------------- ,
2
where dividing by 2 assumes the metal2 vertical strap wires are supplied from
both ends;
wm2
=
I strap
-----------,
d m2
It is recommended that the metal2 wire width, wm2, be divided into c equal
portions which are spaced equidistant across the module, where
c
=
I avg
-------- , rounded up to the next integer.
I m1
The same consideration must be given to the number of vias used to connect the
metal1 and metal2 straps.
Adding Routing Channels
In the SAGE-X Standard Cell Library, each cell is designed with a uniform cell
height of 5.0µm (i.e., 9 tracks tall with 0.56µm per track). The cell layouts allow
neighboring rows of cells to share common power or ground rails when cells
abut each other at the top and bottom edges of the cell bounding box. The seaof-cells layout with no channels between rows will usually yield the minimum
area. In case of extremely congested areas, the designer may want to separate
some rows of cells to increase the number of routing channels within a particular
layout region. Because geometries must overlap cell boundaries, a particular
spacing between the rows may result in DRC violations for layer spacing. It is
recommended that you do not use spacings that cause DRC violations. If these
spacings must be used, the DRC violations must be fixed manually by filling the
void between the rows with the appropriate layer(s). Table 4 indicates which
TSMC 0.18µm Process 1.8-Volt SAGE-X Standard Cell Library Databook
20
Introduction
DRC violations to expect and how to correct them for a separation between rows
of cells.
Table 4. Correcting DRC Violations
Special Cells
Row Separation in
Number of Grids
Expected DRC Violations
Action to Correct
DRC Violations
0 (Rows Abut)
None
None
1
None
None
2
NWELL space < 0.6 µm
Draw NWELL layer
between rows to merge
NWELL regions above and
below row separation.
3
None
None
4
None
None
5 or more
None
None
This section discusses special cells in the SAGE-X Standard Cell Library.
Antenna-Fix Cell
The library contains an antenna-fix cell which must be inserted manually.
However, most place and route tools will indicate which nets require the
antenna-fix cell. The 0.18 TSMC antenna effect prevention guideline, "Design
Rule 0.18mm LOGIC Salicide 1.8V/3.3V Process," specifies a maximum wire
length. During place and route, the router may connect wires to the input gates
of cells that are longer than the maximum length allowable by the guideline. The
antenna cell can be used in this case to add an optional diode on the net close to
the input gates which do not meet the guideline. Pin A on the antenna cell
connects to a diode, reverse biased to ground. A diode can be added to either P
or N.
Fill Cells
The library contains several FILL cells: FILL1, FILL2, FILL4, FILL8, FILL16,
FILL32, FILL64. The number appended to "FILL" in the cell name denotes the
width of the cell in tracks.
During place and route, the FILL cells are used to connect power and ground
rails across an area containing no cells. The FILL cells are also used to ensure
gaps do not occur between well or implant layers which could cause design rule
violations. Using wider cells where appropriate reduces the size of the layout
database.
TSMC 0.18µm Process 1.8-Volt SAGE-X Standard Cell Library Databook
21
Introduction
Low-Power (XL) Cells
The library contains a wide variety of cells, denoted by an "XL" suffix in the
cell name, that are designed specifically for low-power applications. Input
capacitance for the XL cells is much lower than that for corresponding X1 (1x
drive strength) cells. Because XL cells have been designed for the sole purpose
of reducing power consumption, output rise and fall times for these cells may
not be equal, and due to the low-drive capability of the XL cells, these cells are
not intended for use in critical timing paths, or to drive heavily loaded nets.
TIEHI/LO Cells
The library contains a TIEHI cell and a TIELO cell. The outputs of the TIEHI
and TIELO cells are driven through diffusion to provide isolation from the
power and ground rails for better ESD protection. The standard cell abstract
methodology assumes that the TIEHI and TIELO cells are used to tie off any
inputs to power and ground. If these cells are not used and the router is allowed
to drop vias on the power rail, DRC errors or shorts may result.
Delay Cells
The library contains delay cells that have the same width. These delay cells allow
the designer to adjust a given delay path with a simple cell substitution after
place and route.
Reading the
Standard Cell
Datasheet
Please refer to the datasheet for DFF on pages 25 and 26 for the arrangement of
each of the following datasheet sections.
1. Cell Name
The cell name field contains the cell name. The datasheets are presented
alphabetically by cell name.
2. Cell Description
The cell description gives the function of the cell. When applicable, the
equation(s) for the output pins are provided.
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Introduction
3. Function Table
The function table gives all possible combinations of input and output signals
for the cell. Table 5 defines the symbols used in datasheet function tables.
Table 5. Function Table Key
Symbol
Description
0
Logic Low
1
Logic High
High to Low Transition
Low to High Transition
x
Don’t Care
IL
Illegal/Undefined
Z
High Impedance
4. Logic Symbol
The logic symbol is a graphical representation of the cell, similar to the view in
the schematic editor when the cell is instantiated. The symbol shows the name
and location of the input and output pins.
5. Cell Size
This cell size table gives the height and width (µm) for each drive strength of
the cell.
6. Functional Schematic
The functional schematic provides a functional representation of the cell.
7. Drive Strength
The drive strength of each cell is indicated by an “X” followed by the unit
strength.
8. AC Power
The AC power table shows the amount of energy consumed (µW/MHz) within
the cell when the corresponding pin changes state. The energy data for each drive
strength of the cell are calculated at 25 oC, 1.8V, typical process, input slew of
0.03ns, and no external load at the output pins.
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Introduction
9. Delay
The delay table shows the intrinsic delay (ns) which is the delay through the cell
when there is no load on the output, and the load multiplier for load dependent
delay, Kload (ns/pF). The delays and load multiplier for each drive strength of
the cell are calculated at 25 oC, 1.8V, typical process, and input slew of 0.03ns.
10. Timing Constraints
The timing constraints table shows the timing conditions (ns) required at 25 oC,
1.8V, and typical process to maintain proper functionality. Setup constraint
values are measured for 0.03ns data slew and 0.03ns clock slew. Hold constraint
values are measured for 0.03ns data slew and 0.03ns clock slew. Minimum pulse
width is defined to be 0.50ns for all set/reset pins and 0.18ns for all clock pins.
These are the largest minimum pulse widths measured from all the cells in the
library.
11. Pin Capacitance
The pin capacitance table shows the typical loading at the input pins of the cell
(pF) for each drive strength of the cell.
TSMC 0.18µm Process 1.8-Volt SAGE-X Standard Cell Library Databook
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Introduction
DFF
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1
4
2
Cell Description
Logic Symbol
The DFF cell is a positive-edge triggered,
static D-type flip-flop.
3
D
CK
Functions
D
0
CK
QN
Q[n+1] QN[n+1]
0
5
1
1
1
0
x
Q[n]
QN[n]
Cell Size
Drive Strength
6
Q
Height (µm) Width (µm)
DFFXL
5.0
11.2
DFFX1
5.0
11.2
DFFX2
5.0
13.9
DFFX4
5.0
16.5
7
Functional Schematic
c
cn
c
c
cn
cn
D
QN
c
cn
Q
cn
CK
c
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TSMC 0.18µm Process 1.8-Volt SAGE-X Standard Cell Library Databook
25
Introduction
DFF
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11
8
AC Power
7
Pin
9
Pin Capacitance
Power (µW/MHz)
Capacitance (pF)
Pin
XL
X1
X2
X4
XL
X1
X2
X4
D
0.0306
0.0276
0.0368
0.0606
D
0.0033
0.0020
0.0024
0.0038
CK
0.0335
0.0318
0.0396
0.0579
CK
0.0020
0.0026
0.0038
0.0059
Q
0.0260
0.0346
0.0614
0.1091
Delays at 25 oC, 1.8V, Typical Process
Intrinsic Delay (ns)
Kload (ns/pF)
Description
10
XL
X1
X2
X4
XL
X1
X2
X4
CK
→
Q↑
0.219
0.197
0.180
0.155
5.696
4.288
2.261
1.139
CK
→
Q↓
0.179
0.166
0.153
0.132
3.406
2.469
1.234
0.611
CK
→
QN↑
0.238
0.221
0.196
0.179
6.239
4.518
2.259
1.138
CK
→
QN↓
0.304
0.280
0.251
0.219
3.342
2.444
1.219
0.605
Timing Constraints at 25 oC, 1.8V, Typical Process
Interval (ns)
Pin
D
CK
Requirement
XL
X1
X2
X4
0.04
0.06
0.06
0.06
setup↑
→
CK
setup↓
→
CK
0.10
0.15
0.15
0.14
hold↑
→
CK
-0.02
-0.04
-0.04
-0.03
hold↓
→
CK
-0.04
0.01
-0.04
-0.04
minpwh
0.18
0.18
0.18
0.18
minpwl
0.25
0.25
0.25
0.25
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TSMC 0.18µm Process 1.8-Volt SAGE-X Standard Cell Library Databook
26
Base Cells
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
27
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
28
ADDF
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Cell Description
Logic Symbol
The ADDF cell provides the arithmetic sum (S) and
carry out (CO) of two operands (A, B) with carry in
(CI). The two outputs (S, CO) are represented by the
logic equations:
A
S
B
S = ( A ⊕ B ⊕ CI )
CO
CI
CO = ( A ⊕ B ) • CI + ( A • B )
Cell Size
Functions
CI
0
0
0
0
1
1
1
1
A
0
0
1
1
0
0
1
1
B
0
1
0
1
0
1
0
1
S
0
1
1
0
1
0
0
1
CO
Drive Strength
0
0
0
1
0
1
1
1
ADDFXL
ADDFX1
ADDFX2
ADDFX4
Height (µm) Width (µm)
5.0
5.0
5.0
5.0
13.9
13.9
13.9
15.2
Functional Schematic
A
S
B
CI
CO
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
29
ADDF
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AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
A
B
CI
XL
X1
X2
X4
0.1044
0.1668
0.0557
0.1083
0.1378
0.0580
0.1290
0.1771
0.0826
0.1978
0.2502
0.1559
A
B
CI
XL
X1
X2
X4
0.0020
0.0020
0.0062
0.0070
0.0067
0.0061
0.0070
0.0067
0.0061
0.0070
0.0067
0.0061
Delays (25 oC, 1.8V, Typical Process)
Kload (ns/pF)
Intrinsic Delay (ns)
Description
A
A
B
B
CI
CI
A
A
B
B
CI
CI
→
→
→
→
→
→
→
→
→
→
→
→
S↑
S↓
S↑
S↓
S↑
S↓
CO↑
CO↓
CO↑
CO↓
CO↑
CO↓
XL
X1
X2
X4
XL
X1
X2
X4
0.454
0.497
0.720
0.589
0.209
0.153
0.484
0.522
0.555
0.758
0.153
0.211
0.202
0.271
0.236
0.308
0.159
0.141
0.247
0.244
0.284
0.263
0.128
0.168
0.220
0.300
0.250
0.337
0.186
0.168
0.275
0.272
0.312
0.286
0.155
0.196
0.269
0.362
0.289
0.400
0.249
0.226
0.338
0.324
0.374
0.330
0.217
0.252
6.395
4.155
6.364
4.188
6.329
4.070
6.239
3.591
6.239
3.666
6.272
3.637
4.529
2.584
4.535
2.583
4.531
2.585
4.515
2.502
4.513
2.458
4.527
2.521
2.253
1.335
2.256
1.336
2.254
1.343
2.245
1.297
2.244
1.265
2.251
1.305
1.117
0.688
1.119
0.687
1.118
0.698
1.110
0.668
1.110
0.641
1.115
0.672
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
30
ADDFH
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Cell Description
Logic Symbol
The ADDFH cell is a high-speed cell providing the
arithmetic sum (S) and carry out (CO) of two
operands (A, B) with carry in (CI). The two outputs
(S, CO) are represented by the logic equations:
A
S
B
S = ( A ⊕ B ⊕ CI )
CO
CI
CO = ( A ⊕ B ) • CI + ( A • B )
Cell Size
Functions
CI
0
0
0
0
1
1
1
1
A
0
0
1
1
0
0
1
1
B
0
1
0
1
0
1
0
1
S
0
1
1
0
1
0
0
1
CO
Drive Strength
0
0
0
1
0
1
1
1
ADDFHXL
ADDFHX1
ADDFHX2
ADDFHX4
Height (µm) Width (µm)
5.04
5.04
5.04
5.04
14.52
15.18
22.44
23.10
Functional Schematic
A
S
B
CI
CO
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
31
ADDFH
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AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
A
B
CI
XL
X1
X2
X4
0.1006
0.0889
0.0574
0.1259
0.1151
0.0673
0.2494
0.2144
0.1162
0.2886
0.2538
0.1551
A
B
CI
XL
X1
X2
X4
0.0039
0.0079
0.0021
0.0061
0.0138
0.0041
0.0116
0.0260
0.0080
0.0116
0.0260
0.0081
Delays (25 oC, 1.8V, Typical Process)
Kload (ns/pF)
Intrinsic Delay (ns)
Description
A
A
B
B
CI
CI
A
A
B
B
CI
CI
→
→
→
→
→
→
→
→
→
→
→
→
S↑
S↓
S↑
S↓
S↑
S↓
CO↑
CO↓
CO↑
CO↓
CO↑
CO↓
XL
X1
X2
X4
XL
X1
X2
X4
0.322
0.313
0.229
0.293
0.282
0.249
0.324
0.324
0.196
0.311
0.130
0.208
0.217
0.245
0.159
0.193
0.179
0.177
0.217
0.242
0.140
0.182
0.101
0.145
0.221
0.240
0.147
0.179
0.154
0.150
0.224
0.242
0.135
0.173
0.087
0.128
0.236
0.266
0.166
0.208
0.177
0.182
0.238
0.266
0.150
0.196
0.098
0.151
6.245
3.476
6.262
3.488
6.252
3.517
6.251
3.576
6.272
3.601
6.267
3.695
4.519
2.476
4.522
2.475
4.522
2.482
4.520
2.478
4.517
2.455
4.523
2.498
2.249
1.222
2.249
1.222
2.250
1.225
2.249
1.224
2.249
1.219
2.250
1.234
1.063
0.671
1.064
0.671
1.064
0.673
1.064
0.672
1.063
0.667
1.064
0.676
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
32
ADDH
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Cell Description
Logic Symbol
The ADDH cell provides the arithmetic sum (S) and
carry out (CO) of two operands (A, B). The two
outputs (S, CO) are represented by the logic
equations:
S = ( A • B) + ( A • B)
A
S
B
CO
CO = A • B
Functions
Cell Size
A
B
S
CO
Drive Strength
0
0
1
1
0
1
0
1
0
1
1
0
0
0
0
1
ADDHXL
ADDHX1
ADDHX2
ADDHX4
Height (µm) Width (µm)
5.0
5.0
5.0
5.0
Functional Schematic
A
B
S
CO
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
33
7.3
7.9
11.9
18.5
ADDH
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AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
A
B
XL
X1
X2
X4
0.0576
0.0423
0.1026
0.0540
0.1844
0.1018
0.3550
0.1779
A
B
XL
X1
X2
X4
0.0047
0.0059
0.0104
0.0082
0.0213
0.0126
0.0415
0.0241
Delays (25 oC, 1.8V, Typical Process)
Kload (ns/pF)
Intrinsic Delay (ns)
Description
A
A
B
B
A
A
B
B
→
→
→
→
→
→
→
→
S↑
S↓
S↑
S↓
CO↑
CO↓
CO↑
CO↓
XL
X1
X2
X4
XL
X1
X2
X4
0.124
0.129
0.060
0.076
0.070
0.091
0.068
0.083
0.077
0.081
0.052
0.070
0.081
0.117
0.081
0.111
0.065
0.073
0.049
0.066
0.074
0.102
0.072
0.096
0.062
0.068
0.043
0.061
0.068
0.097
0.065
0.090
7.069
3.917
6.981
3.716
6.242
3.308
6.242
3.303
2.756
1.629
2.732
1.558
4.520
2.619
4.520
2.616
1.348
0.803
1.337
0.770
2.219
1.222
2.219
1.221
0.671
0.397
0.665
0.382
1.110
0.612
1.110
0.611
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
34
AND2
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Cell Description
Logic Symbol
The AND2 cell provides the logical AND of two inputs
(A, B). The output (Y) is represented by the logic
equation:
A
Y
B
Y = ( A • B)
Cell Size
Functions
A
0
x
1
B
x
0
1
Y
Drive Strength
0
0
1
AND2XL
AND2X1
AND2X2
AND2X4
Height (µm) Width (µm)
5.0
5.0
5.0
5.04
Functional Schematic
A
B
Y
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
35
2.6
2.6
2.6
3.30
AND2
Your logo here
AC Power
Power (µW/MHz)
Pin
XL
A
B
0.0176
0.0199
X1
0.0200
0.0228
X2
X4
0.0286
0.0315
0.0503
0.0598
Pin Capacitance
Capacitance (pF)
Pin
XL
A
B
0.0021
0.0021
X1
0.0019
0.0020
X2
X4
0.0032
0.0033
0.0058
0.0063
Delays at 25 oC, 1.8V, Typical Process
Intrinsic Delay (ns)
Kload (ns/pF)
Description
A
A
B
B
→
→
→
→
Y↑
Y↓
Y↑
Y↓
XL
X1
X2
X4
XL
X1
X2
X4
0.079
0.092
0.083
0.101
0.084
0.112
0.088
0.123
0.068
0.090
0.072
0.099
0.065
0.100
0.069
0.112
6.250
3.318
6.247
3.324
4.523
2.448
4.521
2.451
2.261
1.220
2.261
1.221
1.034
0.737
1.034
0.737
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
36
AND3
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Cell Description
Logic Symbol
The AND3 cell provides the logical AND of three
inputs (A, B, C). The output (Y) is represented by the
logic equation:
A
B
C
Y = ( A • B • C)
Y
Cell Size
Functions
A
B
C
Y
Drive Strength
0
x
x
1
x
0
x
1
x
x
0
1
0
0
0
1
AND3XL
AND3X1
AND3X2
AND3X4
Height (µm) Width (µm)
5.0
5.0
5.0
5.0
Functional Schematic
A
B
Y
C
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
37
3.3
3.3
3.3
4.0
AND3
Your logo here
AC Power
Power (µW/MHz)
Pin
A
B
C
XL
X1
X2
X4
0.0187
0.0210
0.0241
0.0209
0.0229
0.0250
0.0319
0.0359
0.0405
0.0606
0.0688
0.0763
Pin Capacitance
Capacitance (pF)
Pin
A
B
C
XL
X1
X2
X4
0.0026
0.0024
0.0024
0.0023
0.0022
0.0022
0.0035
0.0036
0.0037
0.0068
0.0074
0.0081
Delays at 25 oC, 1.8V, Typical Process
Intrinsic Delay (ns)
Kload (ns/pF)
Description
A
A
B
B
C
C
→
→
→
→
→
→
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
XL
X1
X2
X4
XL
X1
X2
X4
0.095
0.111
0.104
0.122
0.107
0.134
0.105
0.129
0.113
0.140
0.117
0.151
0.087
0.109
0.096
0.120
0.099
0.131
0.075
0.094
0.084
0.106
0.088
0.117
6.260
3.135
6.258
3.145
6.259
3.156
4.530
2.633
4.530
2.636
4.530
2.642
2.242
1.228
2.241
1.230
2.242
1.232
1.141
0.608
1.141
0.609
1.141
0.610
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
38
AND4
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Cell Description
Logic Symbol
The AND4 cell provides the logical AND of four inputs
(A, B, C, D). The output (Y) is represented by the logic
equation:
A
B
C
D
Y = ( A • B • C • D)
Functions
Y
Cell Size
A
B
C
D
Y
Drive Strength
0
x
x
x
1
x
0
x
x
1
x
x
0
x
1
x
x
x
0
1
0
0
0
0
1
AND4XL
AND4X1
AND4X2
AND4X4
Height (µm) Width (µm)
5.0
5.0
5.0
5.0
Functional Schematic
A
B
C
D
Y
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
39
4.0
4.0
4.0
7.3
AND4
Your logo here
AC Power
Power (µW/MHz)
Pin
XL
A
B
C
D
0.0184
0.0208
0.0242
0.0266
X1
X2
0.0198
0.0233
0.0253
0.0276
X4
0.0340
0.0388
0.0433
0.0480
0.0606
0.0688
0.0803
0.0889
Pin Capacitance
Capacitance (pF)
Pin
XL
A
B
C
D
0.0025
0.0024
0.0025
0.0025
X1
X2
0.0023
0.0021
0.0022
0.0023
X4
0.0037
0.0036
0.0038
0.0038
0.0068
0.0069
0.0075
0.0082
Delays at 25 oC, 1.8V, Typical Process
Intrinsic Delay (ns)
Kload (ns/pF)
Description
A
A
B
B
C
C
D
D
→
→
→
→
→
→
→
→
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
XL
X1
X2
X4
XL
X1
X2
X4
0.102
0.109
0.114
0.122
0.121
0.135
0.125
0.145
0.120
0.126
0.131
0.138
0.138
0.151
0.142
0.161
0.097
0.107
0.108
0.119
0.114
0.131
0.117
0.141
0.087
0.106
0.097
0.120
0.104
0.133
0.108
0.146
6.272
3.353
6.273
3.364
6.271
3.376
6.272
3.393
4.540
2.463
4.538
2.467
4.541
2.473
4.538
2.480
2.284
1.217
2.284
1.219
2.284
1.222
2.284
1.225
1.122
0.610
1.122
0.611
1.121
0.612
1.122
0.614
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
40
Your logo here
Delays at 25 oC, 1.8V, Typical Process
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
41
AND4
AOI21
Your logo here
Cell Description
Logic Symbol
The AOI21 cell provides the logical inverted OR of
one AND group and an additional input. The output
(Y) is represented by the logic equation:
Y = ( A0 • A1 ) + B0
A0
A1
Y
B0
Functions
A0
A1
B0
Y
0
x
x
1
x
0
x
1
0
0
1
x
1
1
0
0
Cell Size
Drive Strength
AOI21XL
AOI21X1
AOI21X2
AOI21X4
Height (µm) Width (µm)
5.0
5.0
5.0
5.0
Functional Schematic
A0
A1
Y
B0
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
42
2.6
2.6
4.6
6.6
AOI21
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
A0
A1
B0
XL
X1
X2
X4
0.0142
0.0182
0.0137
0.0196
0.0238
0.0185
0.0395
0.0505
0.0368
0.0737
0.0895
0.0679
A0
A1
B0
XL
X1
X2
X4
0.0032
0.0032
0.0032
0.0045
0.0044
0.0043
0.0094
0.0088
0.0083
0.0174
0.0174
0.0154
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
A0
A0
A1
A1
B0
B0
→
→
→
→
→
→
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
XL
X1
X2
X4
XL
X1
X2
X4
0.065
0.032
0.077
0.037
0.050
0.020
0.058
0.029
0.070
0.034
0.051
0.020
0.055
0.028
0.067
0.032
0.047
0.018
0.050
0.026
0.062
0.030
0.045
0.017
9.471
3.945
9.461
3.947
9.469
3.248
6.838
2.729
6.832
2.730
6.836
2.405
3.420
1.365
3.416
1.365
3.418
1.196
1.714
0.684
1.712
0.684
1.713
0.602
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
43
AOI211
Your logo here
Cell Description
Logic Symbol
The AOI211 cell provides the logical inverted OR of
one AND group and two additional inputs. The output
(Y) is represented by the logic equation:
A0
A1
Y = ( A0 • A1 ) + B0 + C0
B0
Y
C0
Functions
A0
A1
B0
C0
Y
0
x
x
x
1
x
0
x
x
1
0
0
x
1
x
0
0
1
x
x
1
1
0
0
0
Cell Size
Drive Strength
AOI211XL
AOI211X1
AOI211X2
AOI211X4
Height (µm) Width (µm)
5.0
5.0
5.0
5.0
Functional Schematic
A0
A1
B0
Y
C0
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
44
3.3
3.3
5.9
6.6
AOI211
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
A0
A1
B0
C0
XL
X1
X2
X4
0.0225
0.0254
0.0165
0.0203
0.0317
0.0358
0.0220
0.0276
0.0629
0.0741
0.0451
0.0571
0.0751
0.0823
0.0743
0.0779
A0
A1
B0
C0
XL
X1
X2
X4
0.0036
0.0035
0.0034
0.0033
0.0049
0.0048
0.0047
0.0045
0.0098
0.0094
0.0089
0.0093
0.0032
0.0032
0.0033
0.0031
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
A0
A0
A1
A1
B0
B0
C0
C0
→
→
→
→
→
→
→
→
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
XL
X1
X2
X4
XL
X1
X2
X4
0.104
0.040
0.121
0.045
0.077
0.024
0.101
0.030
0.098
0.039
0.113
0.044
0.071
0.024
0.095
0.030
0.094
0.038
0.110
0.042
0.067
0.022
0.093
0.029
0.262
0.162
0.281
0.167
0.237
0.135
0.262
0.143
12.248
3.980
12.234
3.985
12.249
3.246
12.237
3.261
8.497
2.754
8.491
2.756
8.496
2.402
8.495
2.409
4.269
1.375
4.265
1.378
4.269
1.194
4.267
1.198
1.109
0.606
1.109
0.606
1.109
0.606
1.109
0.606
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
45
AOI22
Your logo here
Cell Description
Logic Symbol
The AOI22 cell provides the logical inverted OR of
two AND groups. The output (Y) is represented by
the logic equation:
A0
A1
Y = ( A0 • A1 ) + ( B0 • B1 )
Y
B0
B1
Functions
A0
A1
B0
B1
Y
0
0
x
x
x
1
x
x
0
0
x
1
0
x
0
x
1
x
x
0
x
0
1
x
1
1
1
1
0
0
Cell Size
Drive Strength
AOI22XL
AOI22X1
AOI22X2
AOI22X4
Height (µm) Width (µm)
5.0
5.0
5.0
5.0
Functional Schematic
A0
A1
Y
B0
B1
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
46
3.3
3.3
5.9
9.2
AOI22
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
A0
A1
B0
B1
XL
X1
X2
X4
0.0155
0.0187
0.0207
0.0238
0.0204
0.0255
0.0278
0.0324
0.0406
0.0485
0.0543
0.0639
0.0815
0.0975
0.1105
0.1269
A0
A1
B0
B1
XL
X1
X2
X4
0.0035
0.0035
0.0033
0.0032
0.0047
0.0046
0.0044
0.0044
0.0091
0.0096
0.0088
0.0090
0.0177
0.0181
0.0173
0.0174
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
A0
A0
A1
A1
B0
B0
B1
B1
→
→
→
→
→
→
→
→
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
XL
X1
X2
X4
XL
X1
X2
X4
0.058
0.025
0.072
0.030
0.090
0.043
0.102
0.048
0.055
0.023
0.068
0.028
0.085
0.041
0.097
0.046
0.055
0.022
0.068
0.027
0.079
0.038
0.092
0.042
0.055
0.022
0.065
0.027
0.074
0.037
0.086
0.041
9.473
3.895
9.466
3.910
9.469
3.933
9.458
3.941
6.726
2.717
6.722
2.719
6.725
2.731
6.720
2.734
3.419
1.358
3.417
1.360
3.418
1.364
3.417
1.366
1.697
0.681
1.648
0.682
1.648
0.683
1.647
0.684
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
47
AOI221
Your logo here
Cell Description
Logic Symbol
The AOI221 cell provides the logical inverted OR of
two AND groups and a third input. The output (Y) is
represented by the logic equation:
Y = ( A0 • A1 ) + ( B0 • B1 ) + C0
A0
A1
B0
B1
Functions
Y
C0
A0
A1
B0
B1
C0
Y
0
0
x
x
x
x
1
x
x
0
0
x
x
1
0
x
0
x
x
1
x
x
0
x
0
x
1
x
0
0
0
0
1
x
x
1
1
1
1
0
0
0
Cell Size
Drive Strength
Height (µm) Width (µm)
AOI221XL
AOI221X1
AOI221X2
AOI221X4
5.0
5.0
5.0
5.0
Functional Schematic
A0
A1
B0
B1
Y
C0
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
48
4.6
4.6
7.9
7.3
AOI221
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
A0
A1
B0
B1
C0
XL
X1
X2
X4
0.0228
0.0257
0.0291
0.0321
0.0204
0.0304
0.0350
0.0392
0.0429
0.0270
0.0577
0.0665
0.0754
0.0837
0.0510
0.0759
0.0806
0.0812
0.0854
0.0746
A0
A1
B0
B1
C0
XL
X1
X2
X4
0.0036
0.0036
0.0036
0.0036
0.0035
0.0050
0.0050
0.0049
0.0048
0.0048
0.0095
0.0098
0.0096
0.0097
0.0091
0.0034
0.0032
0.0033
0.0032
0.0032
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
A0
A0
A1
A1
B0
B0
B1
B1
C0
C0
→
→
→
→
→
→
→
→
→
→
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
XL
X1
X2
X4
XL
X1
X2
X4
0.127
0.045
0.144
0.049
0.149
0.050
0.164
0.054
0.082
0.025
0.113
0.039
0.128
0.043
0.130
0.046
0.145
0.050
0.085
0.025
0.104
0.035
0.119
0.040
0.121
0.041
0.137
0.046
0.075
0.022
0.284
0.164
0.302
0.169
0.306
0.173
0.324
0.178
0.241
0.136
12.018
3.949
12.004
3.955
12.019
4.043
12.004
4.050
12.012
3.253
8.621
2.730
8.614
2.732
8.623
2.770
8.614
2.774
8.620
2.405
4.311
1.366
4.307
1.367
4.311
1.387
4.308
1.388
4.309
1.196
1.138
0.606
1.139
0.605
1.138
0.606
1.139
0.606
1.139
0.605
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
49
AOI222
Your logo here
Cell Description
Logic Symbol
The AOI222 cell provides the logical inverted OR of
three AND groups. The output (Y) is represented by
the logic equation:
Y = ( A0 • A1 ) + ( B0 • B1 ) + ( C0 • C1 )
A0
A1
B0
B1
Y
Functions
A0
A1
B0
B1
C0
C1
Y
0
0
0
0
x
x
x
x
x
x
1
x
x
x
x
0
0
0
0
x
x
1
0
0
x
x
0
0
x
x
x
1
x
x
x
0
0
x
x
0
0
x
1
x
0
x
0
x
0
x
0
x
1
x
x
x
0
x
0
x
0
x
0
1
x
x
1
1
1
1
1
1
1
1
0
0
0
C0
C1
Cell Size
Drive Strength
AOI222XL
AOI222X1
AOI222X2
AOI222X4
Height (µm) Width (µm)
5.0
5.0
5.0
5.0
Functional Schematic
A0
A1
B0
B1
Y
C0
C1
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
50
5.3
5.3
9.2
7.9
AOI222
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
A0
A1
B0
B1
C0
C1
XL
X1
X2
X4
0.0242
0.0271
0.0303
0.0338
0.0364
0.0396
0.0324
0.0366
0.0410
0.0455
0.0490
0.0533
0.0575
0.0669
0.0758
0.0835
0.0922
0.1028
0.0791
0.0814
0.0851
0.0888
0.0877
0.0918
A0
A1
B0
B1
C0
C1
XL
X1
X2
X4
0.0037
0.0037
0.0035
0.0035
0.0035
0.0034
0.0051
0.0051
0.0050
0.0049
0.0049
0.0048
0.0100
0.0103
0.0096
0.0098
0.0096
0.0097
0.0034
0.0034
0.0032
0.0031
0.0032
0.0032
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
A0
A0
A1
A1
B0
B0
B1
B1
C0
C0
C1
C1
→
→
→
→
→
→
→
→
→
→
→
→
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
XL
X1
X2
X4
XL
X1
X2
X4
0.091
0.032
0.108
0.037
0.177
0.057
0.196
0.063
0.201
0.068
0.217
0.074
0.091
0.030
0.108
0.035
0.153
0.049
0.169
0.054
0.171
0.061
0.186
0.067
0.086
0.028
0.102
0.033
0.139
0.045
0.154
0.050
0.157
0.057
0.172
0.063
0.237
0.155
0.256
0.159
0.328
0.181
0.346
0.187
0.350
0.194
0.367
0.200
12.500
3.906
12.490
3.921
12.498
3.948
12.490
3.956
12.495
4.030
12.484
4.024
8.646
2.715
8.641
2.724
8.645
2.729
8.638
2.733
8.644
2.766
8.638
2.765
4.311
1.358
4.309
1.361
4.310
1.364
4.307
1.366
4.311
1.383
4.307
1.382
1.130
0.610
1.130
0.610
1.130
0.610
1.130
0.610
1.130
0.610
1.131
0.610
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
51
AOI2BB1
Your logo here
Cell Description
Logic Symbol
The AOI2BB1 cell provides the logical inverted OR
of one AND group of two inverted inputs (A0N, A1N)
and an additional non-inverted input (B0). The output
(Y) is represented by the logic equation:
Y = ( A0N • A1N ) + B0
Functions
A0N A1N
1
x
x
0
x
1
x
0
A0N
A1N
Y
B0
Cell Size
B0
Y
Drive Strength
0
0
1
x
1
1
0
0
AOI2BB1XL
AOI2BB1X1
AOI2BB1X2
AOI2BB1X4
Height (µm) Width (µm)
5.0
5.0
5.0
5.0
Functional Schematic
A0N
A1N
Y
B0
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
52
3.3
3.3
4.6
7.3
AOI2BB1
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
A0N
A1N
B0
XL
X1
X2
X4
0.0195
0.0212
0.0132
0.0225
0.0244
0.0175
0.0343
0.0401
0.0332
0.0689
0.0778
0.0664
A0N
A1N
B0
XL
X1
X2
X4
0.0025
0.0022
0.0032
0.0024
0.0024
0.0041
0.0042
0.0043
0.0084
0.0079
0.0079
0.0156
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
A0N
A0N
A1N
A1N
B0
B0
→
→
→
→
→
→
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
XL
X1
X2
X4
XL
X1
X2
X4
0.079
0.135
0.084
0.145
0.050
0.021
0.080
0.154
0.083
0.166
0.048
0.023
0.072
0.130
0.078
0.141
0.042
0.020
0.069
0.126
0.075
0.135
0.040
0.020
9.482
3.187
9.483
3.188
9.460
3.041
6.838
2.566
6.838
2.566
6.828
2.494
3.363
1.229
3.364
1.229
3.361
1.199
1.649
0.613
1.649
0.613
1.647
0.600
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
53
AOI2BB2
Your logo here
Cell Description
Logic Symbol
The AOI2BB2 cell provides the logical inverted OR
of one AND group of two inverted inputs (A0N, A1N)
and one AND group of two non-inverted inputs (B0,
B1). The output (Y) is represented by the logic
equation:
Y = ( A0N • A1N ) + ( B0 • B1 )
A0N
A1N
Y
B0
B1
Functions
A0N A1N
1
1
x
x
x
0
x
x
1
1
x
0
B0
B1
Y
0
x
0
x
1
x
x
0
x
0
1
x
1
1
1
1
0
0
Cell Size
Drive Strength
AOI2BB2XL
AOI2BB2X1
AOI2BB2X2
AOI2BB2X4
Height (µm) Width (µm)
5.0
5.0
5.0
5.0
Functional Schematic
A0N
A1N
Y
B0
B1
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
54
4.6
4.6
5.9
9.9
AOI2BB2
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
A0N
A1N
B0
B1
XL
X1
X2
X4
0.0192
0.0211
0.0154
0.0192
0.0205
0.0225
0.0205
0.0249
0.0334
0.0381
0.0413
0.0498
0.0643
0.0736
0.0774
0.0934
A0N
A1N
B0
B1
XL
X1
X2
X4
0.0025
0.0023
0.0034
0.0033
0.0024
0.0021
0.0046
0.0046
0.0043
0.0041
0.0092
0.0098
0.0077
0.0081
0.0171
0.0176
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
A0N
A0N
A1N
A1N
B0
B0
B1
B1
→
→
→
→
→
→
→
→
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
XL
X1
X2
X4
XL
X1
X2
X4
0.074
0.143
0.078
0.152
0.064
0.032
0.077
0.037
0.071
0.148
0.076
0.157
0.061
0.030
0.074
0.034
0.070
0.133
0.076
0.142
0.053
0.026
0.066
0.031
0.065
0.120
0.072
0.130
0.051
0.026
0.062
0.031
7.061
3.410
7.059
3.410
9.473
3.933
9.460
3.935
5.134
2.475
5.136
2.475
6.892
2.729
6.888
2.731
2.547
1.268
2.547
1.267
3.419
1.363
3.415
1.364
1.229
0.610
1.229
0.610
1.648
0.684
1.647
0.684
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
55
AOI31
Your logo here
Cell Description
Logic Symbol
The AOI31 cell provides the logical inverted OR of
one AND group and an additional input. The output
(Y) is represented by the logic equation:
Y = ( A0 • A1 • A2 ) + B0
A0
A1
A2
Y
B0
Functions
A0
A1
A2
B0
Y
0
x
x
x
1
x
0
x
x
1
x
x
0
x
1
0
0
0
1
x
1
1
1
0
0
Cell Size
Drive Strength
Height (µm) Width (µm)
AOI31XL
AOI31X1
AOI31X2
AOI31X4
5.0
5.0
5.0
5.0
Functional Schematic
A0
A1
A2
Y
B0
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
56
3.3
3.3
5.9
5.9
AOI31
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
A0
A1
A2
B0
XL
X1
X2
X4
0.0162
0.0200
0.0236
0.0179
0.0210
0.0269
0.0321
0.0247
0.0478
0.0562
0.0654
0.0497
0.0693
0.0740
0.0771
0.0704
A0
A1
A2
B0
XL
X1
X2
X4
0.0035
0.0035
0.0034
0.0032
0.0048
0.0048
0.0047
0.0044
0.0107
0.0099
0.0095
0.0083
0.0033
0.0032
0.0032
0.0031
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
A0
A0
A1
A1
A2
A2
B0
B0
→
→
→
→
→
→
→
→
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
XL
X1
X2
X4
XL
X1
X2
X4
0.066
0.036
0.082
0.043
0.096
0.046
0.071
0.020
0.063
0.033
0.079
0.041
0.092
0.043
0.071
0.021
0.064
0.033
0.079
0.039
0.093
0.042
0.066
0.019
0.199
0.160
0.216
0.168
0.232
0.171
0.209
0.133
9.474
4.442
9.466
4.444
9.468
4.444
9.475
3.264
6.727
3.025
6.723
3.026
6.723
3.026
6.729
2.413
3.421
1.515
3.418
1.516
3.419
1.516
3.421
1.200
1.109
0.610
1.109
0.610
1.109
0.610
1.108
0.609
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
57
AOI32
Your logo here
Cell Description
Logic Symbol
The AOI32 cell provides the logical inverted OR of
two AND groups. The output (Y) is represented by
the logic equation:
A0
A1
A2
Y = ( A0 • A1 • A2 ) + ( B0 • B1 )
Y
B0
B1
Functions
A0
A1
A2
B0
B1
Y
0
0
x
x
x
x
x
1
x
x
0
0
x
x
x
1
x
x
x
x
0
0
x
1
0
x
0
x
0
x
1
x
x
0
x
0
x
0
1
x
1
1
1
1
1
1
0
0
Cell Size
Drive Strength
Height (µm) Width (µm)
AOI32XL
AOI32X1
AOI32X2
AOI32X4
5.0
5.0
5.0
5.0
Functional Schematic
A0
A1
A2
Y
B0
B1
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
58
4.6
4.6
7.3
6.6
AOI32
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
A0
A1
A2
B0
B1
XL
X1
X2
X4
0.0227
0.0269
0.0294
0.0199
0.0240
0.0300
0.0349
0.0393
0.0272
0.0310
0.0594
0.0686
0.0784
0.0536
0.0613
0.0754
0.0797
0.0813
0.0710
0.0771
A0
A1
A2
B0
B1
XL
X1
X2
X4
0.0036
0.0036
0.0034
0.0035
0.0036
0.0048
0.0048
0.0047
0.0046
0.0047
0.0094
0.0098
0.0100
0.0092
0.0095
0.0033
0.0033
0.0032
0.0033
0.0032
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
A0
A0
A1
A1
A2
A2
B0
B0
B1
B1
→
→
→
→
→
→
→
→
→
→
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
XL
X1
X2
X4
XL
X1
X2
X4
0.095
0.050
0.111
0.058
0.125
0.061
0.077
0.026
0.090
0.031
0.090
0.046
0.105
0.053
0.119
0.056
0.074
0.024
0.087
0.029
0.089
0.045
0.104
0.052
0.119
0.055
0.074
0.023
0.087
0.028
0.227
0.174
0.245
0.183
0.260
0.186
0.210
0.149
0.224
0.152
9.475
4.443
9.462
4.450
9.468
4.451
9.482
3.912
9.474
3.928
6.727
3.026
6.721
3.030
6.722
3.030
6.731
2.725
6.726
2.729
3.434
1.513
3.432
1.515
3.432
1.515
3.435
1.363
3.433
1.364
1.109
0.606
1.109
0.606
1.109
0.606
1.108
0.606
1.109
0.606
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
59
AOI33
Your logo here
Cell Description
Logic Symbol
The AOI33 cell provides the logical inverted OR of
two AND groups. The output (Y) is represented by
the logic equation:
A0
A1
A2
Y = ( A0 • A1 • A2 ) + ( B0 • B1 • B2 )
Y
B0
B1
B2
Functions
A0
A1
A2
B0
B1
B2
Y
0
0
0
x
x
x
x
x
x
x
1
x
x
x
0
0
0
x
x
x
x
1
x
x
x
x
x
x
0
0
0
x
1
0
x
x
0
x
x
0
x
x
1
x
x
0
x
x
0
x
x
0
x
1
x
x
x
0
x
x
0
x
x
0
1
x
1
1
1
1
1
1
1
1
1
0
0
Cell Size
Drive Strength
Height (µm) Width (µm)
AOI33XL
AOI33X1
AOI33X2
AOI33X4
5.0
5.0
5.0
5.0
Functional Schematic
A0
A1
A2
Y
B0
B1
B2
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
60
5.3
5.3
8.6
7.3
AOI33
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
A0
A1
A2
B0
B1
B2
XL
X1
X2
X4
0.0213
0.0254
0.0288
0.0284
0.0325
0.0361
0.0305
0.0353
0.0398
0.0389
0.0445
0.0494
0.0610
0.0701
0.0793
0.0784
0.0914
0.1016
0.0746
0.0782
0.0833
0.0866
0.0880
0.0916
A0
A1
A2
B0
B1
B2
XL
X1
X2
X4
0.0036
0.0036
0.0036
0.0034
0.0034
0.0034
0.0049
0.0050
0.0050
0.0048
0.0047
0.0046
0.0098
0.0103
0.0108
0.0092
0.0098
0.0102
0.0033
0.0034
0.0036
0.0033
0.0033
0.0031
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
A0
A0
A1
A1
A2
A2
B0
B0
B1
B1
B2
B2
→
→
→
→
→
→
→
→
→
→
→
→
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
XL
X1
X2
X4
XL
X1
X2
X4
0.091
0.034
0.106
0.042
0.121
0.045
0.126
0.062
0.141
0.071
0.155
0.074
0.088
0.032
0.104
0.039
0.118
0.042
0.122
0.059
0.136
0.066
0.150
0.069
0.083
0.029
0.098
0.036
0.114
0.040
0.120
0.059
0.135
0.066
0.150
0.070
0.229
0.172
0.246
0.178
0.263
0.182
0.268
0.196
0.285
0.204
0.300
0.207
9.480
4.422
9.472
4.434
9.476
4.435
9.478
4.442
9.467
4.442
9.473
4.442
6.731
3.018
6.726
3.024
6.726
3.024
6.728
3.023
6.726
3.027
6.726
3.027
3.437
1.542
3.435
1.545
3.433
1.544
3.436
1.545
3.433
1.547
3.433
1.547
1.109
0.610
1.109
0.610
1.109
0.610
1.109
0.610
1.109
0.610
1.109
0.610
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
61
BUF
Your logo here
Cell Description
Logic Symbol
The BUF cell provides the logical buffer of a single
input (A). The output (Y) is represented by the logic
equation:
A
Y
Y = A
Cell Size
Functions
A
Y
0
1
0
1
Drive Strength
BUFXL
BUFX1
BUFX2
BUFX3
BUFX4
BUFX8
BUFX12
BUFX16
BUFX20
Height (µm) Width (µm)
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
Functional Schematic
A
Y
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
62
2.6
2.6
2.6
2.6
3.3
5.9
6.6
8.6
10.6
BUF
Your logo here
AC Power
Power (µW/MHz)
Pin
A
XL
X1
X2
X3
X4
X8
X12
X16
X20
0.0146
0.0168
0.0283
0.0374
0.0481
0.0920
0.1401
0.1845
0.2186
X20
Pin Capacitance
Capacitance (pF)
Pin
A
XL
X1
X2
X3
X4
X8
X12
X16
0.0021
0.0021
0.0032
0.0043
0.0056
0.0107
0.0160
0.0211
0.0265
X20
Delays at 25 oC, 1.8V, Typical Process
Intrinsic Delay (ns)
Description
A → Y↑
A → Y↓
XL
X1
X2
X3
X4
X8
X12
X16
0.052
0.074
0.055
0.084
0.058
0.083
0.056
0.082
0.053
0.077
0.049
0.074
0.050
0.074
0.050 0.049
0.073 0.071
X12
X16
Kload (ns/pF)
Description
A → Y↑
A → Y↓
XL
X1
X2
X3
X4
X8
6.232
3.294
4.514
2.430
2.248
1.209
1.497
0.809
1.124
0.605
0.554
0.304
0.370 0.277
0.203 0.151
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
63
X20
0.222
0.122
CLKBUF
Your logo here
Cell Description
Logic Symbol
The CLKBUF cell provides the logical buffer of a
single input (A), with balanced delays for clock
signals. The output (Y) is represented by the logic
equation:
Y = A
A
Y
Cell Size
Functions
A
Y
0
1
0
1
Drive Strength
CLKBUFXL
CLKBUFX1
CLKBUFX2
CLKBUFX3
CLKBUFX4
CLKBUFX8
CLKBUFX12
CLKBUFX16
CLKBUFX20
Height (µm) Width (µm)
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
Functional Schematic
A
Y
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
64
2.6
2.6
2.6
2.6
3.3
4.6
10.6
12.5
15.8
CLKBUF
Your logo here
AC Power
Power (µW/MHz)
Pin
A
XL
X1
X2
X3
X4
X8
X12
X16
0.0159
0.0201
0.0246
0.0298
0.0377
0.0754
0.1778
0.2394
X20
0.2860
Pin Capacitance
Capacitance (pF)
Pin
A
XL
X1
X2
X3
X4
X8
X12
X16
0.0019
0.0033
0.0029
0.0032
0.0040
0.0078
0.0189
0.0225
X20
0.0311
Delays at 25 oC, 1.8V, Typical Process
Intrinsic Delay (ns)
Description
A → Y↑
A → Y↓
XL
X1
X2
X3
X4
X8
X12
X16
0.050
0.106
0.056
0.059
0.064
0.079
0.071
0.086
0.073
0.084
0.067
0.079
0.065
0.075
0.069 0.064
0.078 0.073
X12
X16
Kload (ns/pF)
Description
A → Y↑
A → Y↓
X20
XL
X1
X2
X3
X4
X8
4.083
4.225
4.160
4.176
2.247
2.260
1.549
1.403
1.125
1.065
0.555
0.502
0.222 0.171
0.203 0.156
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
65
X20
0.139
0.121
CLKINV
Your logo here
Cell Description
Logic Symbol
The CLKINV cell provides the logical inversion of a
single input (A), with balanced delays for clock
signals. The output (Y) is represented by the logic
equation:
Y = A
A
Y
Cell Size
Functions
A
Y
0
1
1
0
Drive Strength
CLKINVXL
CLKINVX1
CLKINVX2
CLKINVX3
CLKINVX4
CLKINVX8
CLKINVX12
CLKINVX16
CLKINVX20
Height (µm) Width (µm)
5.0
5.0
5.0
5.0
5.0
5.04
5.04
5.04
5.04
Functional Schematic
A
Y
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
66
2.0
2.0
2.0
2.0
2.6
3.96
12.54
16.50
19.14
CLKINV
Your logo here
AC Power
Power (µW/MHz)
Pin
A
XL
X1
X2
X3
X4
X8
X12
X16
X20
0.0088
0.0104
0.0183
0.0264
0.0322
0.0695
0.2398
0.3204
0.3952
Pin Capacitance
Capacitance (pF)
Pin
A
XL
X1
X2
X3
X4
X8
X12
X16
X20
0.0026
0.0031
0.0058
0.0084
0.0108
0.0228
0.0069
0.0087
0.0107
Delays at 25 oC, 1.8V, Typical Process
Intrinsic Delay (ns)
Description
A → Y↑
A → Y↓
XL
X1
X2
X3
X4
X8
X12
X16
X20
0.024
0.020
0.022
0.019
0.017
0.017
0.016
0.015
0.015
0.015
0.017
0.017
0.144
0.137
0.142
0.148
0.139
0.143
Kload (ns/pF)
Description
A → Y↑
A → Y↓
XL
X1
X2
X3
X4
X8
X12
X16
X20
5.723
4.367
4.509
3.649
2.254
2.251
1.504
1.394
1.116
1.059
0.518
0.627
0.209
0.240
0.157
0.180
0.126
0.144
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
67
DFF
Your logo here
Cell Description
Logic Symbol
The DFF cell is a positive-edge triggered, static
D-type flip-flop.
D
Function Table
D
CK
0
1
x
Q
CK
QN
Q[n+1] QN[n+1]
0
1
Q[n]
1
0
QN[n]
Cell Size
Drive Strength
DFFXL
DFFX1
DFFX2
DFFX4
Height (µm) Width (µm)
5.0
5.0
5.0
5.0
11.2
11.2
13.9
16.5
Functional Schematic
c
cn
c
c
cn
cn
D
QN
c
cn
Q
cn
CK
c
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
68
DFF
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
D
CK
Q
XL
X1
X2
X4
0.0306
0.0335
0.0260
0.0276
0.0318
0.0346
0.0368
0.0396
0.0614
0.0606
0.0579
0.1091
D
CK
XL
X1
X2
X4
0.0033
0.0020
0.0020
0.0026
0.0024
0.0038
0.0038
0.0059
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
CK
CK
CK
CK
→
→
→
→
Q↑
Q↓
QN↑
QN↓
XL
X1
X2
X4
XL
X1
X2
X4
0.219
0.179
0.238
0.304
0.197
0.166
0.221
0.280
0.180
0.153
0.196
0.251
0.155
0.132
0.179
0.219
5.696
3.406
6.239
3.342
4.288
2.469
4.518
2.444
2.261
1.234
2.259
1.219
1.139
0.611
1.138
0.605
Timing Constraints at 25 oC, 1.8V, Typical Process
Interval (ns)
Pin
D
CK
Requirement
setup↑ → CK
setup↓ → CK
hold↑ → CK
hold↓ → CK
minpwh
minpwl
XL
X1
X2
X4
0.04
0.10
-0.02
0.01
0.18
0.25
0.06
0.15
-0.04
-0.04
0.18
0.25
0.06
0.15
-0.04
-0.04
0.18
0.25
0.06
0.14
-0.03
-0.04
0.18
0.25
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
69
DFFHQ
Your logo here
Cell Description
Logic Symbol
The DFFHQ cell is a high-speed, positive-edge
triggered, static D-type flip-flop. The cell has a single
output (Q) and fast clock-to-out path.
D
CK
Functions
D
CK
0
1
x
Q
Q[n+1]
0
1
Q[n]
Cell Size
Drive Strength
Height (µm) Width (µm)
DFFHQXL
DFFHQX1
DFFHQX2
DFFHQX4
5.0
5.0
5.0
5.0
10.6
10.6
13.2
14.5
Functional Schematic
c
cn
c
c
cn
cn
D
c
cn
Q
cn
CK
c
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
70
DFFHQ
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
D
CK
Q
Pin
XL
X1
X2
X4
0.0354
0.0346
0.0133
0.0355
0.0328
0.0176
0.0514
0.0388
0.0285
0.0669
0.0496
0.0422
D
CK
XL
X1
X2
X4
0.0035
0.0022
0.0022
0.0029
0.0022
0.0036
0.0031
0.0052
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
CK → Q↑
CK → Q↓
XL
X1
X2
X4
XL
X1
X2
X4
0.204
0.206
0.170
0.161
0.166
0.156
0.144
0.133
6.246
3.517
4.283
2.593
2.261
1.297
1.118
0.611
Timing Constraints at 25 oC, 1.8V, Typical Process
Interval (ns)
Pin
D
CK
Requirement
setup↑ → CK
setup↓ → CK
hold↑ → CK
hold↓ → CK
minpwh
minpwl
XL
X1
X2
X4
0.05
0.14
-0.02
0.01
0.18
0.25
0.08
0.18
-0.04
-0.04
0.18
0.25
0.09
0.20
-0.04
-0.05
0.18
0.25
0.08
0.18
-0.04
-0.04
0.18
0.25
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
71
DFFN
Your logo here
Cell Description
Logic Symbol
The DFFN cell is a negative-edge triggered, static
D-type flip-flop.
D
Function
D
Q
CKN
QN
CKN Q[n+1] QN[n+1]
0
1
x
0
1
Q[n]
1
0
QN[n]
Cell Size
Drive Strength
DFFNXL
DFFNX1
DFFNX2
DFFNX4
Height (µm) Width (µm)
5.0
5.0
5.0
5.0
11.2
11.2
13.9
15.8
Functional Schematic
c
cn
c
c
cn
cn
QN
D
c
cn
Q
c
CKN
cn
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
72
DFFN
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
D
CKN
Q
XL
X1
X2
X4
0.0319
0.0314
0.0370
0.0285
0.0347
0.0420
0.0370
0.0487
0.0695
0.0565
0.0739
0.1176
D
CKN
XL
X1
X2
X4
0.0029
0.0021
0.0018
0.0028
0.0022
0.0037
0.0028
0.0061
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
CKN
CKN
CKN
CKN
→
→
→
→
Q↑
Q↓
QN↑
QN↓
XL
X1
X2
X4
XL
X1
X2
X4
0.183
0.305
0.358
0.263
0.143
0.261
0.315
0.226
0.128
0.240
0.283
0.199
0.108
0.202
0.253
0.176
5.709
3.420
6.243
3.334
4.289
2.552
4.519
2.444
2.263
1.276
2.259
1.219
1.190
0.621
1.189
0.615
Timing Constraints at 25 oC, 1.8V, Typical Process
Interval (ns)
Pin
D
CKN
Requirement
setup↑ → CKN
setup↓ → CKN
hold↑ → CKN
hold↓ → CKN
minpwl
minpwh
XL
X1
X2
X4
0.05
0.07
0.08
-0.05
0.18
0.25
0.08
0.12
0.04
-0.09
0.18
0.25
0.09
0.12
0.04
-0.09
0.18
0.25
0.09
0.12
0.02
-0.09
0.18
0.25
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
73
DFFNR
Your logo here
Cell Description
Logic Symbol
The DFFNR cell is a negative-edge triggered, static
D-type flip-flop with asynchronous active-low reset
(RN).
D
CKN
Function
RN
D
0
1
1
1
x
0
1
x
Q
QN
CKN Q[n+1] QN[n+1]
x
0
0
1
Q[n]
RN
1
1
0
QN[n]
Cell Size
Drive Strength
DFFNRXL
DFFNRX1
DFFNRX2
DFFNRX4
Height (µm) Width (µm)
5.0
5.0
5.04
5.0
15.8
15.2
17.16
20.5
Functional Schematic
c
cn
c
c
cn
cn
Q
D
c
cn
QN
RN
c
CKN
cn
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
74
DFFNR
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
D
CKN
RN
Q
XL
X1
X2
X4
0.0334
0.0360
0.0164
0.0445
0.0265
0.0343
0.0182
0.0517
0.0342
0.0444
0.0216
0.0810
0.0414
0.0523
0.0328
0.1344
D
CKN
RN
XL
X1
X2
X4
0.0033
0.0023
0.0021
0.0020
0.0028
0.0026
0.0021
0.0030
0.0033
0.0027
0.0038
0.0055
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
CKN
CKN
RN
CKN
CKN
RN
→
→
→
→
→
→
Q↑
Q↓
Q↓
QN↑
QN↓
QN↑
XL
X1
X2
X4
XL
X1
X2
X4
0.360
0.418
0.238
0.368
0.332
0.187
0.319
0.413
0.242
0.349
0.284
0.178
0.323
0.435
0.240
0.357
0.275
0.162
0.281
0.368
0.208
0.300
0.230
0.141
6.237
3.301
3.301
6.239
3.519
6.245
4.515
2.433
2.434
4.517
2.491
4.518
2.077
1.442
1.442
2.079
1.463
2.080
1.137
0.615
0.615
1.138
0.625
1.139
Timing Constraints at 25 oC, 1.8V, Typical Process
Interval (ns)
Pin
D
CKN
RN
Requirement
setup↑ → CKN
setup↓ → CKN
hold↑ → CKN
hold↓ → CKN
minpwl
minpwh
minpwl
recovery
XL
X1
X2
X4
0.05
0.06
0.09
-0.04
0.18
0.25
0.50
0.05
0.08
0.13
0.04
-0.09
0.18
0.25
0.50
0.08
0.11
0.15
0.04
-0.09
0.18
0.25
0.50
0.10
0.10
0.12
0.04
-0.08
0.18
0.25
0.50
0.09
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
75
DFFNS
Your logo here
Cell Description
Logic Symbol
The DFFNS cell is a negative-edge triggered, static
D-type flip-flop with asynchronous active-low set
(SN).
SN
D
Function
SN
D
0
1
1
1
x
0
1
x
CKN
CKN Q[n+1] QN[n+1]
x
1
0
1
Q[n]
Q
0
1
0
QN[n]
QN
Cell Size
Drive Strength
DFFNSXL
DFFNSX1
DFFNSX2
DFFNSX4
Height (µm) Width (µm)
5.0
5.0
5.0
5.0
13.9
13.9
13.9
19.1
Functional Schematic
c
cn
c
c
cn
cn
Q
D
c
cn
QN
SN
c
CKN
cn
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
76
DFFNS
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
D
CKN
SN
Q
XL
X1
X2
X4
0.0315
0.0338
0.0050
0.0422
0.0243
0.0324
0.0059
0.0501
0.0282
0.0359
0.0092
0.0812
0.0359
0.0461
0.0166
0.1325
D
CKN
SN
XL
X1
X2
X4
0.0028
0.0020
0.0047
0.0017
0.0025
0.0052
0.0017
0.0028
0.0069
0.0020
0.0033
0.0117
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
CKN
CKN
SN
CKN
CKN
SN
→
→
→
→
→
→
Q↑
Q↓
Q↑
QN↑
QN↓
QN↓
XL
X1
X2
X4
XL
X1
X2
X4
0.289
0.397
0.157
0.350
0.260
0.127
0.266
0.389
0.146
0.328
0.230
0.110
0.266
0.376
0.152
0.307
0.216
0.101
0.253
0.362
0.142
0.295
0.204
0.093
6.240
3.298
6.240
6.255
3.363
3.343
4.516
2.430
4.518
4.522
2.441
2.439
2.277
1.211
2.276
2.280
1.214
1.216
1.137
0.606
1.137
1.139
0.608
0.610
Timing Constraints at 25 oC, 1.8V, Typical Process
Interval (ns)
Pin
D
CKN
SN
Requirement
setup↑ → CKN
setup↓ → CKN
hold↑ → CKN
hold↓ → CKN
minpwl
minpwh
minpwl
recovery
XL
X1
X2
X4
0.03
0.07
0.08
-0.05
0.18
0.25
0.50
-0.09
0.06
0.12
0.04
-0.09
0.18
0.25
0.50
-0.05
0.06
0.13
0.04
-0.10
0.18
0.25
0.50
-0.04
0.07
0.12
0.04
-0.10
0.18
0.25
0.50
-0.04
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
77
DFFNSR
Your logo here
Cell Description
Logic Symbol
SN
The DFFNSR cell is a negative-edge triggered, static
D-type flip-flop with asynchronous active-low reset
(RN) and set (SN), and set dominating reset.
D
Functions
Q
CKN
RN
SN
D
0
1
0
1
1
1
1
0
0
1
1
1
x
x
x
0
1
x
QN
CKN Q[n+1] QN[n+1]
x
x
x
0
1
1
0
1
Q[n]
1
0
0
1
0
QN[n]
RN
Cell Size
Drive Strength
DFFNSRXL
DFFNSRX1
DFFNSRX2
DFFNSRX4
Height (µm) Width (µm)
5.0
5.0
5.0
5.0
17.2
16.5
17.2
23.1
Functional Schematic
c
cn
c
c
cn
cn
Q
D
c
cn
QN
RN
SN
c
CKN
cn
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
78
DFFNSR
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
D
CKN
SN
RN
Q
XL
X1
X2
X4
0.0390
0.0344
0.0051
0.0182
0.0453
0.0318
0.0342
0.0056
0.0197
0.0539
0.0360
0.0392
0.0092
0.0234
0.0814
0.0500
0.0551
0.0170
0.0397
0.1465
D
CKN
SN
RN
XL
X1
X2
X4
0.0031
0.0019
0.0061
0.0022
0.0019
0.0027
0.0065
0.0025
0.0018
0.0027
0.0088
0.0035
0.0030
0.0039
0.0149
0.0057
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
CKN
CKN
SN
SN
RN
CKN
CKN
SN
SN
RN
→
→
→
→
→
→
→
→
→
→
Q↑
Q↓
Q↑
Q↓
Q↓
QN↑
QN↓
QN↑
QN↓
QN↑
XL
X1
X2
X4
XL
X1
X2
X4
0.364
0.428
0.183
0.186
0.271
0.369
0.329
0.127
0.145
0.212
0.328
0.422
0.171
0.178
0.265
0.352
0.290
0.109
0.130
0.196
0.310
0.392
0.167
0.161
0.232
0.323
0.256
0.093
0.113
0.164
0.292
0.371
0.156
0.155
0.222
0.303
0.244
0.088
0.109
0.154
6.238
3.093
6.237
3.093
3.094
6.260
3.581
6.278
3.387
6.279
4.515
2.436
4.515
2.436
2.436
4.522
2.501
4.533
2.455
4.531
2.276
1.212
2.276
1.211
1.211
2.279
1.234
2.284
1.221
2.284
1.137
0.610
1.137
0.610
0.610
1.140
0.624
1.142
0.619
1.142
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
79
DFFNSR
Your logo here
Timing Constraints at 25 oC, 1.8V, Typical Process
Interval (ns)
Pin
D
CKN
SN
RN
Requirement
setup↑
setup↓
hold↑
hold↓
→ CKN
→ CKN
→ CKN
→ CKN
minpwl
minpwh
minpwl
recovery
minpwl
recovery
XL
X1
X2
X4
0.08
0.10
0.06
-0.07
0.18
0.25
0.50
-0.07
0.50
0.07
0.15
0.17
0.02
-0.11
0.18
0.25
0.50
-0.04
0.50
0.12
0.13
0.18
0.02
-0.13
0.18
0.25
0.50
-0.04
0.50
0.10
0.11
0.14
0.03
-0.09
0.18
0.25
0.50
-0.04
0.50
0.09
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
80
DFFR
Your logo here
Cell Description
Logic Symbol
The DFFR cell is a positive-edge triggered, static
D-type flip-flop with asynchronous active-low
reset (RN).
D
Q
CK
Functions
RN
D
CK
0
1
1
1
x
0
1
x
x
QN
Q[n+1] QN[n+1]
0
0
1
Q[n]
RN
1
1
0
QN[n]
Cell Size
Drive Strength
DFFRXL
DFFRX1
DFFRX2
DFFRX4
Height (µm) Width (µm)
5.0
5.0
5.04
5.0
15.2
15.2
17.16
19.8
Functional Schematic
c
cn
c
c
cn
cn
Q
D
c
cn
QN
RN
cn
CK
c
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
81
DFFR
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
D
CK
RN
Q
XL
X1
X2
X4
0.0326
0.0365
0.0162
0.0347
0.0276
0.0349
0.0183
0.0403
0.0331
0.0395
0.0213
0.0817
0.0417
0.0444
0.0321
0.1302
D
CK
RN
XL
X1
X2
X4
0.0032
0.0021
0.0020
0.0021
0.0028
0.0026
0.0021
0.0030
0.0033
0.0027
0.0038
0.0055
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
CK
CK
RN
CK
CK
RN
→
→
→
→
→
→
Q↑
Q↓
Q↓
QN↑
QN↓
QN↑
XL
X1
X2
X4
XL
X1
X2
X4
0.406
0.283
0.237
0.232
0.378
0.186
0.379
0.312
0.242
0.247
0.344
0.179
0.390
0.307
0.239
0.230
0.341
0.163
0.335
0.271
0.208
0.202
0.284
0.140
6.238
3.300
3.301
6.240
3.519
6.244
4.515
2.434
2.434
4.519
2.492
4.518
2.077
1.387
1.386
2.078
1.408
2.079
1.137
0.615
0.615
1.138
0.625
1.139
Timing Constraints at 25 oC, 1.8V, Typical Process
Interval (ns)
Pin
D
CK
RN
Requirement
setup↑
setup↓
hold↑
hold↓
→ CK
→ CK
→ CK
→ CK
minpwh
minpwl
minpwl
recovery
XL
X1
X2
X4
0.05
0.09
-0.03
0.02
0.18
0.25
0.50
0.04
0.07
0.14
-0.05
-0.04
0.18
0.25
0.50
0.05
0.09
0.17
-0.06
-0.05
0.18
0.25
0.50
0.08
0.07
0.14
-0.05
-0.03
0.18
0.25
0.50
0.05
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
82
DFFRHQ
Your logo here
Cell Description
Logic Symbol
The DFFRHQ cell is a high-speed, positive-edge
triggered, static D-type flip-flop with asynchronous
active-low reset (RN). The cell has a single output
(Q) and fast clock-to-out path.
D
Q
CK
Functions
RN
D
CK
Q[n+1]
0
1
1
1
x
0
1
x
x
0
0
1
Q[n]
RN
Cell Size
Drive Strength
DFFRHQXL
DFFRHQX1
DFFRHQX2
DFFRHQX4
Height (µm) Width (µm)
5.0
5.0
5.0
5.0
13.9
13.9
17.2
21.1
Functional Schematic
c
cn
c
c
cn
cn
Q
D
c
cn
RN
cn
CK
c
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
83
DFFRHQ
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
D
CK
RN
Q
Pin
XL
X1
X2
X4
0.0332
0.0337
0.0210
0.0218
0.0381
0.0340
0.0252
0.0266
0.0586
0.0432
0.0354
0.0374
0.0913
0.0615
0.0548
0.0592
D
CK
RN
XL
X1
X2
X4
0.0032
0.0020
0.0024
0.0019
0.0030
0.0039
0.0026
0.0041
0.0054
0.0043
0.0062
0.0093
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
CK → Q↑
CK → Q↓
RN → Q↓
XL
X1
X2
X4
XL
X1
X2
X4
0.233
0.247
0.171
0.192
0.173
0.137
0.168
0.150
0.117
0.155
0.137
0.097
9.482
3.620
2.887
6.727
2.468
1.947
3.364
1.225
1.081
1.832
0.676
0.645
Timing Constraints at 25 oC, 1.8V, Typical Process
Interval (ns)
Pin
D
CK
RN
Requirement
setup↑ → CK
setup↓ → CK
hold↑ → CK
hold↓ → CK
minpwh
minpwl
minpwl
recovery
XL
X1
X2
X4
0.07
0.14
-0.02
0.02
0.18
0.25
0.50
0.09
0.12
0.20
-0.05
-0.03
0.18
0.25
0.50
0.11
0.12
0.20
-0.05
-0.02
0.18
0.25
0.50
0.12
0.11
0.18
-0.04
-0.02
0.18
0.25
0.50
0.10
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
84
DFFS
Your logo here
Cell Description
Logic Symbol
The DFFS cell is a positive-edge triggered, static Dtype flip-flop with asynchronous active-low set (SN).
SN
Functions
D
SN
D
CK
0
1
1
1
x
0
1
x
x
Q
Q[n+1] QN[n+1]
CK
1
0
1
Q[n]
0
1
0
QN[n]
QN
Cell Size
Drive Strength
DFFSXL
DFFSX1
DFFSX2
DFFSX4
Height (µm) Width (µm)
5.0
5.0
5.0
5.0
12.5
12.5
13.9
18.5
Functional Schematic
c
cn
c
c
cn
cn
Q
D
c
cn
QN
SN
cn
CK
c
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
85
DFFS
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
D
CK
SN
Q
XL
X1
X2
X4
0.0311
0.0318
0.0053
0.0335
0.0242
0.0293
0.0060
0.0385
0.0275
0.0307
0.0102
0.0706
0.0340
0.0380
0.0168
0.1293
D
CK
SN
XL
X1
X2
X4
0.0032
0.0021
0.0050
0.0019
0.0027
0.0054
0.0019
0.0028
0.0073
0.0022
0.0034
0.0121
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
CK
CK
SN
CK
CK
SN
→
→
→
→
→
→
Q↑
Q↓
Q↑
QN↑
QN↓
QN↓
XL
X1
X2
X4
XL
X1
X2
X4
0.333
0.274
0.156
0.227
0.304
0.127
0.307
0.284
0.141
0.226
0.274
0.108
0.322
0.287
0.153
0.216
0.271
0.103
0.304
0.266
0.142
0.198
0.256
0.094
6.241
3.301
6.243
6.254
3.364
3.345
4.518
2.432
4.516
4.718
2.611
2.609
2.194
1.210
2.193
2.197
1.214
1.217
1.097
0.606
1.097
1.099
0.608
0.610
Timing Constraints at 25 oC, 1.8V, Typical Process
Interval (ns)
Pin
D
CK
SN
Requirement
setup↑ → CK
setup↓ → CK
hold↑ → CK
hold↓ → CK
minpwh
minpwl
minpwl
recovery
XL
X1
X2
X4
0.04
0.09
-0.02
0.00
0.18
0.25
0.50
-0.02
0.05
0.14
-0.04
-0.05
0.18
0.25
0.50
-0.01
0.05
0.15
-0.04
-0.05
0.18
0.25
0.50
0.00
0.05
0.14
-0.04
-0.04
0.18
0.25
0.50
0.00
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
86
DFFSHQ
Your logo here
Cell Description
Logic Symbol
The DFFSHQ cell is a high-speed, positive-edge
triggered, static D-type flip-flop with asynchronous
active-low set (SN). The cell has a single output (Q)
and fast clock-to-out path.
SN
D
Functions
Q
CK
SN
D
CK
Q[n+1]
0
1
1
1
x
0
1
x
x
1
0
1
Q[n]
Cell Size
Drive Strength
DFFSHQXL
DFFSHQX1
DFFSHQX2
DFFSHQX4
Height (µm) Width (µm)
5.0
5.0
5.0
5.0
13.2
13.2
15.8
18.5
Functional Schematic
c
cn
c
c
cn
cn
Q
D
c
cn
SN
cn
CK
c
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
87
DFFSHQ
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
D
CK
SN
Q
Pin
XL
X1
X2
X4
0.0352
0.0333
0.0091
0.0214
0.0378
0.0335
0.0102
0.0238
0.0538
0.0393
0.0173
0.0333
0.0822
0.0590
0.0315
0.0560
D
CK
SN
XL
X1
X2
X4
0.0033
0.0021
0.0079
0.0019
0.0028
0.0085
0.0025
0.0037
0.0135
0.0037
0.0055
0.0214
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
CK → Q↑
CK → Q↓
SN → Q↑
XL
X1
X2
X4
XL
X1
X2
X4
0.224
0.237
0.072
0.191
0.171
0.081
0.171
0.148
0.082
0.154
0.135
0.087
6.271
4.218
3.455
4.522
2.773
2.426
2.251
1.383
1.251
1.125
0.690
0.665
Timing Constraints at 25 oC, 1.8V, Typical Process
Interval (ns)
Pin
D
CK
SN
Requirement
setup↑ → CK
setup↓ → CK
hold↑ → CK
hold↓ → CK
minpwh
minpwl
minpwl
recovery
XL
X1
X2
X4
0.05
0.16
-0.02
0.00
0.18
0.25
0.50
0.05
0.09
0.23
-0.05
-0.07
0.18
0.25
0.50
0.05
0.09
0.21
-0.04
-0.05
0.18
0.25
0.50
0.07
0.09
0.19
-0.04
-0.04
0.18
0.25
0.50
0.06
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
88
DFFSR
Your logo here
Cell Description
Logic Symbol
The DFFSR cell is a positive-edge triggered, static
D-type flip-flop with asynchronous active-low reset
(RN) and set (SN), and set dominating reset.
SN
D
Functions
RN
SN
D
CK
0
1
0
1
1
1
1
0
0
1
1
1
x
x
x
0
1
x
x
x
x
CK
Q[n+1] QN[n+1]
0
1
1
0
1
Q[n]
Q
1
0
0
1
0
QN[n]
QN
RN
Cell Size
Drive Strength
DFFSRXL
DFFSRX1
DFFSRX2
DFFSRX4
Height (µm) Width (µm)
5.0
5.0
5.0
5.0
17.2
17.2
17.2
23.8
Functional Schematic
c
cn
c
c
cn
cn
Q
D
c
cn
QN
RN
SN
cn
CK
c
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
89
DFFSR
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
XL
D
CK
SN
RN
Q
X1
0.0378
0.0362
0.0058
0.0174
0.0339
X2
0.0309
0.0336
0.0062
0.0192
0.0432
0.0353
0.0356
0.0098
0.0231
0.0756
X4
XL
D
CK
SN
RN
0.0497
0.0466
0.0177
0.0396
0.1400
0.0030
0.0024
0.0060
0.0022
X1
0.0019
0.0029
0.0065
0.0024
X2
0.0019
0.0030
0.0087
0.0036
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
CK
CK
SN
SN
RN
CK
CK
SN
SN
RN
→
→
→
→
→
→
→
→
→
→
Q↑
Q↓
Q↑
Q↓
Q↓
QN↑
QN↓
QN↑
QN↓
QN↑
XL
X1
X2
X4
XL
X1
X2
X4
0.401
0.307
0.181
0.184
0.276
0.248
0.368
0.126
0.144
0.218
0.370
0.319
0.171
0.179
0.263
0.248
0.332
0.108
0.130
0.192
0.354
0.288
0.167
0.161
0.232
0.218
0.299
0.092
0.112
0.163
0.339
0.276
0.156
0.155
0.222
0.207
0.291
0.088
0.109
0.155
6.236
3.310
6.233
3.311
3.311
6.258
3.576
6.278
3.386
6.275
4.515
2.436
4.515
2.437
2.437
4.525
2.501
4.531
2.455
4.532
2.276
1.211
2.276
1.211
1.211
2.279
1.233
2.285
1.221
2.284
1.137
0.610
1.137
0.610
0.610
1.139
0.624
1.142
0.619
1.142
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
90
X4
0.0030
0.0039
0.0149
0.0059
DFFSR
Your logo here
Timing Constraints at 25 oC, 1.8V, Typical Process
Interval (ns)
Pin
D
CK
SN
RN
Requirement
setup↑
setup↓
hold↑
hold↓
→ CK
→ CK
→ CK
→ CK
minpwh
minpwl
minpwl
recovery
minpwl
recovery
XL
X1
X2
X4
0.08
0.12
-0.05
-0.01
0.18
0.25
0.50
-0.01
0.50
0.06
0.13
0.18
-0.09
-0.05
0.18
0.25
0.50
0.01
0.50
0.11
0.12
0.20
-0.08
-0.06
0.18
0.25
0.50
0.02
0.50
0.09
0.09
0.16
-0.05
-0.04
0.18
0.25
0.50
0.01
0.50
0.07
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
91
DFFSRHQ
Your logo here
Cell Description
Logic Symbol
The DFFSRHQ cell is a high-speed, positive-edge
triggered, static D-type flip-flop with asynchronous
active-low reset (RN) and set (SN), and set
dominating reset. The cell has a single output (Q)
and fast clock-to-out path.
SN
D
Q
CK
Functions
RN
SN
D
CK
Q[n+1]
0
1
0
1
1
1
1
0
0
1
1
1
x
x
x
0
1
x
x
x
x
0
1
1
0
1
Q[n]
RN
Cell Size
Drive Strength
DFFSRHQXL
DFFSRHQX1
DFFSRHQX2
DFFSRHQX4
Height (µm) Width (µm)
5.0
5.0
5.0
5.0
15.8
15.8
22.4
30.4
Functional Schematic
c
cn
c
c
cn
cn
Q
D
c
cn
RN
SN
cn
CK
c
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
92
DFFSRHQ
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
XL
X1
X2
X4
D
CK
SN
RN
0.0358
0.0352
0.0093
0.0246
0.0401
0.0343
0.0104
0.0278
0.0657
0.0456
0.0172
0.0421
0.1125
0.0669
0.0316
0.0675
Q
0.0234
0.0257
0.0434
0.0734
D
CK
SN
RN
XL
X1
X2
X4
0.0034
0.0021
0.0105
0.0025
0.0023
0.0031
0.0115
0.0038
0.0031
0.0045
0.0167
0.0058
0.0049
0.0065
0.0276
0.0101
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
CK
CK
SN
SN
RN
→
→
→
→
→
Q↑
Q↓
Q↑
Q↓
Q↓
XL
X1
X2
X4
XL
X1
X2
X4
0.240
0.241
0.077
0.050
0.178
0.198
0.165
0.083
0.052
0.131
0.184
0.154
0.088
0.046
0.113
0.169
0.141
0.091
0.038
0.099
9.490
4.187
4.001
3.731
3.768
6.732
2.761
2.834
2.480
2.481
3.366
1.396
1.452
1.332
1.332
1.683
0.694
0.773
0.692
0.692
Timing Constraints at 25 oC, 1.8V, Typical Process
Interval (ns)
Pin
D
CK
SN
RN
Requirement
setup↑ → CK
setup↓ → CK
hold↑ → CK
hold↓ → CK
minpwh
minpwl
minpwl
recovery
minpwl
recovery
XL
X1
X2
X4
0.09
0.16
-0.02
0.02
0.18
0.25
0.50
0.06
0.50
0.10
0.12
0.20
-0.05
-0.02
0.18
0.25
0.50
0.06
0.50
0.12
0.13
0.20
-0.05
-0.02
0.18
0.25
0.50
0.08
0.50
0.12
0.12
0.20
-0.03
-0.02
0.18
0.25
0.50
0.09
0.50
0.12
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
93
DFFTR
Your logo here
Cell Description
Logic Symbol
The DFFTR cell is a positive-edge triggered,
static D-type flip-flop with synchronous active-low
reset (RN).
D
CK
Functions
RN
D
0
x
1
1
x
x
0
1
Q
CK
QN
Q[n+1] QN[n+1]
0
Q[n]
0
1
RN
1
QN[n]
1
0
Cell Size
Drive Strength
Height (µm) Width (µm)
DFFTRXL
DFFTRX1
DFFTRX2
DFFTRX4
5.0
5.0
5.0
5.0
11.2
11.2
13.9
16.5
Functional Schematic
c
cn
c
c
cn
cn
D
RN
Q
c
cn
QN
cn
CK
c
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
94
DFFTR
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
D
CK
RN
Q
XL
X1
X2
X4
0.0300
0.0332
0.0325
0.0237
0.0286
0.0340
0.0303
0.0293
0.0351
0.0406
0.0373
0.0606
0.0575
0.0578
0.0593
0.1067
D
CK
RN
XL
X1
X2
X4
0.0029
0.0021
0.0025
0.0022
0.0029
0.0019
0.0021
0.0040
0.0019
0.0032
0.0062
0.0028
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
CK
CK
CK
CK
→
→
→
→
Q↑
Q↓
QN↑
QN↓
XL
X1
X2
X4
XL
X1
X2
X4
0.217
0.174
0.218
0.285
0.198
0.159
0.206
0.270
0.193
0.147
0.204
0.269
0.156
0.133
0.181
0.223
6.245
3.396
6.246
3.330
4.520
2.461
4.519
2.440
2.250
1.226
2.249
1.213
1.125
0.612
1.124
0.606
Timing Constraints at 25 oC, 1.8V, Typical Process
Interval (ns)
Pin
D
CK
RN
Requirement
setup↑ → CK
setup↓ → CK
hold↑ → CK
hold↓ → CK
minpwh
minpwl
setup↑ → CK
setup↓ → CK
hold↑ → CK
hold↓ → CK
XL
X1
X2
X4
0.08
0.14
-0.05
-0.05
0.18
0.25
0.08
0.16
-0.06
-0.05
0.09
0.22
-0.07
-0.12
0.18
0.25
0.09
0.23
-0.07
-0.12
0.10
0.22
-0.07
-0.11
0.18
0.25
0.10
0.23
-0.08
-0.12
0.09
0.19
-0.06
-0.09
0.18
0.25
0.10
0.20
-0.07
-0.09
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
95
DLY1
Your logo here
Cell Description
Logic Symbol
The DLY1 cell provides the logical delay of a single
input (A). The output (Y) is represented by the logic
equation:
A
Y
Y = A
Cell Size
Functions
Drive Strength
A
Y
0
1
0
1
DLY1X1
Height (µm) Width (µm)
5.0
4.0
Functional Schematic
A
Y
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
96
DLY1
Your logo here
AC Power
Pin Capacitance
Power (µW/MHz)
Capacitance (pF)
Pin
Pin
X1
A
X1
0.0304
A
0.0018
Delays at 25 oC, 1.8V, Typical Process
Intrinsic Delay (ns)
Kload (ns/pF)
X1
X1
0.135
0.162
4.518
2.435
Description
A → Y↑
A → Y↓
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
97
DLY2
Your logo here
Cell Description
Logic Symbol
The DLY2 cell provides the logical delay of a single
input (A). The output (Y) is represented by the logic
equation:
A
Y
Y = A
Cell Size
Functions
Drive Strength
A
Y
0
1
0
1
DLY2X1
Height (µm) Width (µm)
5.0
4.0
Functional Schematic
A
Y
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
98
DLY2
Your logo here
AC Power
Pin Capacitance
Power (µW/MHz)
Capacitance (pF)
Pin
Pin
X1
A
X1
0.0347
A
0.0018
Delays at 25 oC, 1.8V, Typical Process
Intrinsic Delay (ns)
Kload (ns/pF)
X1
X1
0.283
0.311
4.527
2.515
Description
A → Y↑
A → Y↓
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
99
DLY3
Your logo here
Cell Description
Logic Symbol
The DLY3 cell provides the logical delay of a single
input (A). The output (Y) is represented by the logic
equation:
A
Y
Y = A
Cell Size
Functions
Drive Strength
A
Y
0
1
0
1
DLY3X1
Height (µm) Width (µm)
5.0
4.6
Functional Schematic
A
Y
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
100
DLY3
Your logo here
AC Power
Pin Capacitance
Power (µW/MHz)
Capacitance (pF)
Pin
Pin
X1
A
X1
0.0416
A
0.0018
Delays at 25 oC, 1.8V, Typical Process
Intrinsic Delay (ns)
Kload (ns/pF)
X1
X1
0.476
0.469
4.541
2.628
Description
A → Y↑
A → Y↓
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
101
DLY4
Your logo here
Cell Description
Logic Symbol
The DLY4 cell provides the logical delay of a single
input (A). The output (Y) is represented by the logic
equation:
A
Y
Y = A
Cell Size
Functions
Drive Strength
A
Y
0
1
0
1
DLY4X1
Height (µm) Width (µm)
5.0
4.6
Functional Schematic
A
Y
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
102
DLY4
Your logo here
AC Power
Pin Capacitance
Power (µW/MHz)
Capacitance (pF)
Pin
Pin
X1
A
X1
0.0490
A
0.0018
Delays at 25 oC, 1.8V, Typical Process
Intrinsic Delay (ns)
Kload (ns/pF)
X1
X1
0.708
0.648
4.564
2.771
Description
A → Y↑
A → Y↓
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
103
EDFF
Your logo here
Cell Description
Logic Symbol
The EDFF cell is a positive-edge triggered, static Dtype flip-flop with synchronous active-high enable
(E).
D
Q
E
Functions
QN
CK
E
D
CK
0
1
1
1
x
0
1
x
x
Q[n+1] QN[n+1]
Q[n]
0
1
Q[n]
QN[n]
1
0
QN[n]
Cell Size
Drive Strength
EDFFXL
EDFFX1
EDFFX2
EDFFX4
Height (µm) Width (µm)
5.0
5.0
5.0
5.0
15.2
15.2
17.8
20.5
Functional Schematic
c
cn
c
D
E
c
cn
cn
QN
cn
c
Q
cn
CK
c
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
104
EDFF
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
D
CK
E
Q
XL
X1
X2
X4
0.0342
0.0400
0.0499
0.0265
0.0342
0.0389
0.0467
0.0353
0.0446
0.0455
0.0580
0.0624
0.0691
0.0645
0.0865
0.1137
D
CK
E
XL
X1
X2
X4
0.0028
0.0022
0.0052
0.0019
0.0029
0.0043
0.0023
0.0041
0.0046
0.0035
0.0066
0.0058
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
CK
CK
CK
CK
→
→
→
→
Q↑
Q↓
QN↑
QN↓
XL
X1
X2
X4
XL
X1
X2
X4
0.231
0.182
0.257
0.340
0.205
0.160
0.221
0.293
0.180
0.147
0.207
0.264
0.159
0.135
0.187
0.233
6.242
3.396
6.249
3.427
5.051
2.717
4.522
2.456
2.246
1.262
2.246
1.256
1.138
0.616
1.138
0.611
Timing Constraints at 25 oC, 1.8V, Typical Process
Interval (ns)
Pin
D
CK
E
Requirement
setup↑ → CK
setup↓ → CK
hold↑ → CK
hold↓ → CK
minpwh
minpwl
setup↑ → CK
setup↓ → CK
hold↑ → CK
hold↓ → CK
XL
X1
X2
X4
0.09
0.23
-0.07
-0.12
0.18
0.25
0.27
0.15
-0.08
-0.11
0.10
0.38
-0.08
-0.26
0.18
0.25
0.42
0.30
-0.09
-0.13
0.12
0.34
-0.09
-0.22
0.18
0.25
0.38
0.27
-0.10
-0.15
0.12
0.30
-0.09
-0.18
0.18
0.25
0.34
0.22
-0.10
-0.16
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
105
EDFFTR
Your logo here
Cell Description
Logic Symbol
The EDFFTR cell is a positive-edge triggered, static
D-type flip-flop with synchronous active-high enable
(E) and synchronous active-low reset (RN).
D
Q
E
Functions
QN
CK
RN
E
D
0
x
1
1
1
x
x
0
1
1
x
x
x
0
1
CK
Q[n+1] QN[n+1]
0
Q[n]
Q[n]
0
1
RN
1
QN[n]
QN[n]
1
0
Cell Size
Drive Strength
Height (µm) Width (µm)
EDFFTRXL
EDFFTRX1
EDFFTRX2
EDFFTRX4
5.0
5.0
5.0
5.0
16.5
16.5
17.8
21.1
Functional Schematic
c
cn
RN
c
c
cn
cn
D
QN
E
cn
c
Q
cn
CK
c
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
106
EDFFTR
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
XL
X1
X2
X4
D
CK
E
RN
0.0380
0.0432
0.0548
0.0438
0.0370
0.0421
0.0490
0.0408
0.0474
0.0503
0.0624
0.0530
0.0742
0.0724
0.0948
0.0813
Q
0.0254
0.0333
0.0615
0.1082
D
CK
E
RN
XL
X1
X2
X4
0.0029
0.0023
0.0056
0.0027
0.0019
0.0031
0.0045
0.0020
0.0023
0.0042
0.0049
0.0023
0.0037
0.0064
0.0061
0.0036
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
CK
CK
CK
CK
→
→
→
→
Q↑
Q↓
QN↑
QN↓
XL
X1
X2
X4
XL
X1
X2
X4
0.236
0.190
0.275
0.345
0.210
0.170
0.238
0.305
0.190
0.150
0.210
0.272
0.168
0.134
0.188
0.243
6.254
3.205
6.253
3.422
4.522
2.467
4.523
2.459
2.251
1.224
2.232
1.217
1.138
0.616
1.137
0.612
Timing Constraints at 25 oC, 1.8V, Typical Process
Interval (ns)
Pin
D
CK
E
RN
Requirement
setup↑ → CK
setup↓ → CK
hold↑ → CK
hold↓ → CK
minpwh
minpwl
setup↑ → CK
setup↓ → CK
hold↑ → CK
hold↓ → CK
setup↑ → CK
setup↓ → CK
hold↑ → CK
hold↓ → CK
XL
X1
X2
X4
0.12
0.26
-0.09
-0.13
0.18
0.25
0.29
0.18
-0.12
-0.13
0.14
0.23
-0.11
-0.08
0.15
0.42
-0.12
-0.30
0.18
0.25
0.45
0.35
-0.13
-0.17
0.16
0.34
-0.13
-0.20
0.16
0.37
-0.12
-0.25
0.18
0.25
0.40
0.30
-0.14
-0.19
0.17
0.31
-0.14
-0.18
0.15
0.31
-0.11
-0.20
0.18
0.25
0.34
0.23
-0.12
-0.19
0.16
0.27
-0.12
-0.13
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
107
HOLD
Your logo here
Cell Description
Logic Symbol
The HOLD cell holds data at a known value. This cell
is often used for holding data on a tri-state bus.
Y
Cell Size
Drive Strength
HOLDX1
Height (µm) Width (µm)
5.0
Functional Schematic
Y
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
108
2.6
HOLD
Your logo here
AC Power
Pin
Pin Capacitance
Power
(µW/MHz)
Pin
X1
X1
Y
0.0209
Capacitance
(pF)
Y
0.0428
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
109
INV
Your logo here
Cell Description
Logic Symbol
The INV cell provides the logical inversion of a single
input (A). The output (Y) is represented by the logic
equation:
A
Y
Y = A
Cell Size
Functions
A
Y
0
1
1
0
Drive Strength
INVXL
INVX1
INVX2
INVX3
INVX4
INVX8
INVX12
INVX16
INVX20
Height (µm) Width (µm)
5.0
5.0
5.0
5.0
5.0
5.04
5.04
5.04
5.04
Functional Schematic
A
Y
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
110
1.3
1.3
2.0
2.6
2.6
3.96
8.58
11.22
12.54
INV
Your logo here
AC Power
Power (µW/MHz)
Pin
A
XL
X1
X2
X3
X4
X8
X12
X16
X20
0.0087
0.0114
0.0209
0.0315
0.0378
0.0775
0.1665
0.2250
0.2804
Pin Capacitance
Capacitance (pF)
Pin
A
XL
X1
X2
X3
X4
X8
X12
X16
X20
0.0026
0.0036
0.0070
0.0100
0.0129
0.0267
0.0067
0.0088
0.0109
Delays at 25 oC, 1.8V, Typical Process
Intrinsic Delay (ns)
Description
A → Y↑
A → Y↓
XL
X1
X2
X3
X4
X8
X12
X16
X20
0.023
0.015
0.023
0.014
0.020
0.012
0.022
0.013
0.018
0.011
0.018
0.012
0.122
0.119
0.119
0.113
0.117
0.110
Kload (ns/pF)
Description
A → Y↑
A → Y↓
XL
X1
X2
X3
X4
X8
X12
X16
X20
6.229
3.237
4.512
2.401
2.256
1.195
1.507
0.798
1.137
0.598
0.519
0.356
0.346
0.240
0.260
0.180
0.208
0.144
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
111
JKFF
Your logo here
Cell Description
Logic Symbol
The JKFF cell is a positive-edge triggered JK-type
flip-flop.
J
Q
K
Function
QN
CK
J
K
x
0
0
1
1
x
0
1
0
1
CK
Q[n+1] QN[n+1]
Q[n]
Q[n]
0
1
QN[n]
QN[n]
QN[n]
1
0
Q[n]
Cell Size
Drive Strength
JKFFXL
JKFFX1
JKFFX2
JKFFX4
Height (µm) Width (µm)
5.0
5.0
5.0
5.04
13.9
13.9
16.5
19.80
Functional Schematic
c
cn
c
c
K
cn
cn
Q
J
cn
c
QN
cn
CK
c
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
112
JKFF
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
J
K
CK
Q
XL
X1
X2
X4
0.0295
0.0261
0.0363
0.0351
0.0290
0.0261
0.0350
0.0402
0.0395
0.0359
0.0432
0.0785
0.0661
0.0561
0.0638
0.1293
J
K
CK
XL
X1
X2
X4
0.0022
0.0028
0.0020
0.0019
0.0018
0.0028
0.0019
0.0022
0.0037
0.0024
0.0035
0.0068
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
CK
CK
CK
CK
→
→
→
→
Q↑
Q↓
QN↑
QN↓
XL
X1
X2
X4
XL
X1
X2
X4
0.259
0.342
0.220
0.171
0.219
0.293
0.196
0.153
0.218
0.278
0.197
0.158
0.190
0.248
0.170
0.138
6.261
3.460
6.246
3.395
4.522
2.463
4.936
2.884
2.218
1.216
2.219
1.227
1.040
0.722
1.040
0.726
Timing Constraints at 25 oC, 1.8V, Typical Process
Interval (ns)
Pin
J
K
CK
Requirement
setup↑ → CK
setup↓ → CK
hold↑ → CK
hold↓ → CK
setup↑ → CK
setup↓ → CK
hold↑ → CK
hold↓ → CK
minpwh
minpwl
XL
X1
X2
X4
0.16
0.12
-0.09
-0.12
0.09
0.14
-0.08
-0.12
0.18
0.25
0.23
0.13
-0.16
-0.12
0.09
0.30
-0.08
-0.26
0.18
0.25
0.22
0.15
-0.16
-0.13
0.11
0.24
-0.09
-0.20
0.18
0.25
0.22
0.17
-0.15
-0.16
0.10
0.20
-0.09
-0.17
0.18
0.25
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
113
JKFFR
Your logo here
Cell Description
Logic Symbol
The JKFFR cell is a positive-edge triggered JK-type
flip-flop with asynchronous active-low reset (RN).
J
Q
K
Function
QN
CK
RN
J
K
1
0
1
1
1
1
x
x
0
0
1
1
x
x
0
1
0
1
CK
x
Q[n+1] QN[n+1]
Q[n]
0
Q[n]
0
1
QN[n]
QN[n]
1
QN[n]
1
0
Q[n]
RN
Cell Size
Drive Strength
JKFFRXL
JKFFRX1
JKFFRX2
JKFFRX4
Height (µm) Width (µm)
5.0
5.0
5.0
5.0
17.2
18.5
18.5
23.1
Functional Schematic
c
cn
c
c
J
cn
cn
Q
K
cn
c
QN
RN
cn
CK
c
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
114
JKFFR
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
XL
X1
X2
X4
J
K
CK
RN
0.0278
0.0335
0.0373
0.0164
0.0258
0.0298
0.0366
0.0175
0.0272
0.0332
0.0381
0.0213
0.0388
0.0454
0.0456
0.0349
Q
0.0527
0.0562
0.0919
0.1493
J
K
CK
RN
XL
X1
X2
X4
0.0028
0.0025
0.0020
0.0021
0.0019
0.0023
0.0025
0.0026
0.0018
0.0023
0.0029
0.0033
0.0023
0.0024
0.0039
0.0056
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
CK
CK
RN
CK
CK
RN
→
→
→
→
→
→
Q↑
Q↓
Q↓
QN↑
QN↓
QN↑
XL
X1
X2
X4
XL
X1
X2
X4
0.462
0.356
0.318
0.222
0.361
0.180
0.421
0.361
0.299
0.234
0.332
0.169
0.398
0.326
0.263
0.225
0.321
0.160
0.341
0.280
0.233
0.197
0.277
0.149
6.254
3.465
3.459
6.237
3.512
6.238
4.523
2.487
2.484
4.515
2.608
4.517
2.219
1.241
1.240
2.219
1.255
2.220
1.110
0.603
0.602
1.110
0.610
1.110
Timing Constraints at 25 oC, 1.8V, Typical Process
Interval (ns)
Pin
J
K
CK
RN
Requirement
setup↑ → CK
setup↓ → CK
hold↑ → CK
hold↓ → CK
setup↑ → CK
setup↓ → CK
hold↑ → CK
hold↓ → CK
minpwh
minpwl
minpwl
recovery
XL
X1
X2
X4
0.11
0.12
-0.09
-0.09
0.16
0.16
-0.09
-0.15
0.18
0.25
0.50
0.05
0.11
0.25
-0.10
-0.20
0.23
0.15
-0.17
-0.13
0.18
0.25
0.50
0.05
0.13
0.26
-0.11
-0.20
0.25
0.16
-0.19
-0.14
0.18
0.25
0.50
0.08
0.14
0.22
-0.12
-0.16
0.24
0.17
-0.16
-0.16
0.18
0.25
0.50
0.07
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
115
JKFFS
Your logo here
Cell Description
Logic Symbol
The JKFFS cell is a positive-edge triggered JK-type
flip-flop with asynchronous active-low set (SN).
SN
Function
J
SN
J
K
1
0
1
1
1
1
x
x
0
0
1
1
x
x
0
1
0
1
CK
x
Q[n]
1
Q[n]
0
1
QN[n]
Q
K
Q[n+1] QN[n+1]
QN
CK
QN[n]
0
QN[n]
1
0
Q[n]
Cell Size
Drive Strength
JKFFSXL
JKFFSX1
JKFFSX2
JKFFSX4
Height (µm) Width (µm)
5.0
5.0
5.0
5.04
16.5
17.2
17.8
20.46
Functional Schematic
c
cn
c
c
J
cn
cn
Q
K
cn
c
QN
SN
cn
CK
c
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
116
JKFFS
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
XL
X1
X2
X4
J
K
CK
SN
0.0274
0.0387
0.0384
0.0051
0.0240
0.0325
0.0361
0.0066
0.0263
0.0360
0.0365
0.0095
0.0302
0.0451
0.0447
0.0156
Q
0.0489
0.0579
0.0851
0.1570
J
K
CK
SN
XL
X1
X2
X4
0.0026
0.0023
0.0021
0.0051
0.0017
0.0023
0.0025
0.0060
0.0017
0.0023
0.0028
0.0079
0.0020
0.0025
0.0036
0.0127
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
CK
CK
SN
CK
CK
SN
→
→
→
→
→
→
Q↑
Q↓
Q↑
QN↑
QN↓
QN↓
XL
X1
X2
X4
XL
X1
X2
X4
0.413
0.379
0.221
0.238
0.316
0.127
0.370
0.344
0.182
0.240
0.296
0.109
0.356
0.316
0.176
0.215
0.280
0.101
0.347
0.285
0.165
0.205
0.281
0.100
6.256
3.468
6.250
6.263
3.386
3.363
4.520
2.462
4.523
4.726
2.532
2.531
2.319
1.241
2.319
2.320
1.233
1.235
1.040
0.722
1.039
1.041
0.723
0.725
Timing Constraints at 25 oC, 1.8V, Typical Process
Interval (ns)
Pin
J
K
CK
SN
Requirement
setup↑ → CK
setup↓ → CK
hold↑ → CK
hold↓ → CK
setup↑ → CK
setup↓ → CK
hold↑ → CK
hold↓ → CK
minpwh
minpwl
minpwl
recovery
XL
X1
X2
X4
0.10
0.15
-0.09
-0.12
0.19
0.16
-0.11
-0.15
0.18
0.25
0.50
-0.02
0.11
0.31
-0.10
-0.27
0.30
0.14
-0.23
-0.13
0.18
0.25
0.50
-0.01
0.12
0.33
-0.10
-0.29
0.32
0.14
-0.24
-0.13
0.18
0.25
0.50
0.00
0.12
0.25
-0.12
-0.21
0.27
0.16
-0.19
-0.15
0.18
0.25
0.50
-0.01
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
117
JKFFSR
Your logo here
Cell Description
Logic Symbol
The JKFFSR cell is a positive-edge triggered
JK-type flip-flop with asynchronous active-low reset
(RN) and set (SN), and set dominating reset.
SN
J
Q
Function
K
RN
SN
J
K
1
1
0
0
1
1
1
1
1
0
1
0
1
1
1
1
x
x
x
x
0
0
1
1
x
x
x
x
0
1
0
1
CK
x
x
x
Q[n+1] QN[n+1]
Q[n]
1
0
1
Q[n]
0
1
QN[n]
QN[n]
0
1
0
QN[n]
1
0
Q[n]
QN
CK
RN
Cell Size
Drive Strength
JKFFSRXL
JKFFSRX1
JKFFSRX2
JKFFSRX4
Height (µm) Width (µm)
5.0
5.0
5.0
5.0
19.8
19.8
20.5
21.8
Functional Schematic
c
cn
J
c
c
cn
cn
Q
K
cn
c
QN
RN
SN
cn
CK
c
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
118
JKFFSR
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
J
K
CK
SN
RN
Q
XL
X1
X2
X4
0.0318
0.0367
0.0382
0.0051
0.0138
0.0604
0.0277
0.0314
0.0368
0.0060
0.0157
0.0672
0.0302
0.0369
0.0388
0.0099
0.0210
0.1016
0.0302
0.0370
0.0390
0.0099
0.0210
0.1515
J
K
CK
SN
RN
XL
X1
X2
X4
0.0027
0.0026
0.0019
0.0043
0.0023
0.0017
0.0026
0.0024
0.0049
0.0027
0.0019
0.0026
0.0028
0.0070
0.0038
0.0019
0.0026
0.0028
0.0070
0.0038
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
CK
CK
SN
SN
RN
CK
CK
SN
SN
RN
→
→
→
→
→
→
→
→
→
→
Q↑
Q↓
Q↑
Q↓
Q↓
QN↑
QN↓
QN↑
QN↓
QN↑
XL
X1
X2
X4
XL
X1
X2
X4
0.522
0.414
0.243
0.279
0.352
0.274
0.418
0.136
0.152
0.209
0.446
0.366
0.206
0.216
0.287
0.267
0.374
0.116
0.137
0.186
0.429
0.346
0.184
0.205
0.270
0.254
0.360
0.113
0.118
0.177
0.470
0.378
0.212
0.235
0.300
0.275
0.396
0.132
0.143
0.197
6.259
3.490
6.260
3.479
3.478
6.265
3.607
6.286
3.394
6.284
4.524
2.463
4.523
2.460
2.459
5.059
2.799
5.068
2.756
5.070
2.249
1.219
2.250
1.218
1.219
2.254
1.243
2.258
1.224
2.258
1.125
0.611
1.125
0.611
0.611
1.130
0.633
1.131
0.617
1.131
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
119
JKFFSR
Your logo here
Timing Constraints at 25 oC, 1.8V, Typical Process
Interval (ns)
Pin
J
K
CK
SN
RN
Requirement
setup↑ → CK
setup↓ → CK
hold↑ → CK
hold↓ → CK
setup↑ → CK
setup↓ → CK
hold↑ → CK
hold↓ → CK
minpwh
minpwl
minpwl
recovery
minpwl
recovery
XL
X1
X2
X4
0.12
0.12
-0.11
-0.08
0.17
0.16
-0.09
-0.16
0.18
0.25
0.50
-0.02
0.50
0.06
0.16
0.27
-0.14
-0.20
0.27
0.19
-0.19
-0.16
0.18
0.25
0.50
0.00
0.50
0.11
0.15
0.23
-0.12
-0.17
0.25
0.17
-0.16
-0.16
0.18
0.25
0.50
0.00
0.50
0.08
0.14
0.23
-0.12
-0.17
0.24
0.17
-0.16
-0.16
0.18
0.25
0.50
0.00
0.50
0.08
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
120
MX2
Your logo here
Cell Description
Logic Symbol
The MX2 cell is a 2-to-1 multiplexer. The state of the
select input (S0) determines which data input (A, B)
is presented to the output (Y).The output (Y) is
represented by the logic equation:
A
Y
B
Y = ( S0 • A ) + ( S0 • B )
S0
Functions
S0
A
B
Y
0
0
1
1
0
1
x
x
x
x
0
1
0
1
0
1
Cell Size
Drive Strength
MX2XL
MX2X1
MX2X2
MX2X4
Height (µm) Width (µm)
5.0
5.0
5.0
5.04
Functional Schematic
A
s0n
Y
B
s0
s0n
S0
s0
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
121
5.3
5.3
5.9
6.60
MX2
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
S0
A
B
XL
X1
X2
X4
0.0331
0.0223
0.0254
0.0339
0.0269
0.0294
0.0571
0.0476
0.0522
0.0856
0.0697
0.0770
S0
A
B
XL
X1
X2
X4
0.0060
0.0022
0.0023
0.0056
0.0032
0.0033
0.0085
0.0057
0.0052
0.0103
0.0071
0.0061
Delay Tables at 25 oC, 1.8V, Typical Process
Intrinsic Delay (ns)
Description
XL
X1
X2
X4
S0 → Y↑
0.125
0.120
0.121
0.136
→
→
→
→
→
0.127
0.097
0.147
0.098
0.153
0.118
0.087
0.119
0.086
0.124
0.110
0.078
0.109
0.080
0.115
0.134
0.096
0.126
0.086
0.140
S0
A
A
B
B
Y↓
Y↑
Y↓
Y↑
Y↓
Kload (ns/pF)
Description
S0
S0
A
A
B
B
→
→
→
→
→
→
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
XL
X1
X2
X4
6.249
3.493
6.250
3.497
6.250
3.506
4.520
2.469
4.518
2.476
4.521
2.477
2.236
1.228
2.236
1.229
2.236
1.229
1.126
0.736
1.127
0.733
1.126
0.737
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
122
MX4
Your logo here
Cell Description
Logic Symbol
The MX4 cell is a 4-to-1 multiplexer. The state of the
select inputs (S1, S0) determines which data input
(A, B, C, D) is presented to the output (Y). The output
(Y) is represented by the logic equation:
A
B
C
D
Y
Y= ( S0 • S1 • A )+( S0 • S1 • B )+( S0 • S1 • C )+(S0 • S1 • D )
S1 S0
Functions
S1
S0
A
B
C
D
Y
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
x
x
x
x
x
x
x
x
0
1
x
x
x
x
x
x
x
x
0
1
x
x
x
x
x
x
x
x
0
1
0
1
0
1
0
1
0
1
Cell Size
Drive Strength
MX4XL
MX4X1
MX4X2
MX4X4
Height (µm) Width (µm)
5.0
5.0
5.04
5.04
13.2
13.2
15.18
15.84
Functional Schematic
A
s0n
s1n
s0n
S0
s0
B
s0
s1n
s1n
C
s0n
s1
Y
S1
s1
D
s0
s1
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
123
MX4
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
S0
S1
A
B
C
D
XL
X1
X2
X4
0.0544
0.0318
0.0333
0.0367
0.0388
0.0432
0.0678
0.0399
0.0444
0.0480
0.0506
0.0555
0.1150
0.0645
0.0713
0.0799
0.0824
0.0909
0.1397
0.0792
0.0981
0.1091
0.1120
0.1207
S0
S1
A
B
C
D
XL
X1
X2
X4
0.0102
0.0059
0.0020
0.0021
0.0019
0.0021
0.0133
0.0067
0.0043
0.0042
0.0042
0.0043
0.0228
0.0110
0.0067
0.0065
0.0068
0.0066
0.0228
0.0111
0.0067
0.0065
0.0068
0.0066
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
S0
S0
S1
S1
A
A
B
B
C
C
D
D
→
→
→
→
→
→
→
→
→
→
→
→
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
XL
X1
X2
X4
XL
X1
X2
X4
0.229
0.256
0.137
0.125
0.170
0.248
0.169
0.252
0.176
0.259
0.176
0.266
0.172
0.193
0.132
0.123
0.129
0.175
0.128
0.179
0.131
0.184
0.130
0.188
0.159
0.187
0.127
0.120
0.120
0.166
0.125
0.173
0.125
0.178
0.125
0.182
0.170
0.217
0.138
0.150
0.133
0.195
0.138
0.203
0.136
0.208
0.136
0.212
6.284
3.953
6.283
3.835
6.282
3.928
6.281
3.933
6.290
3.974
6.288
3.983
4.526
2.582
4.527
2.566
4.530
2.575
4.526
2.577
4.528
2.585
4.530
2.587
2.239
1.278
2.239
1.270
2.240
1.272
2.240
1.272
2.241
1.279
2.240
1.279
1.044
0.764
1.044
0.759
1.043
0.761
1.044
0.761
1.044
0.764
1.044
0.764
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
124
MXI2
Your logo here
Cell Description
Logic Symbol
The MXI2 cell is a 2-to-1 multiplexer with inverted
output. The state of the select input (S0) determines
which data input (A, B) is presented to the output (Y).
The output (Y) is represented by the logic equation:
A
Y
B
Y = ( S0 • A ) + ( S0 • B )
S0
Functions
S0
A
B
Y
0
0
1
1
0
1
x
x
x
x
0
1
1
0
1
0
Cell Size
Drive Strength
MXI2XL
MXI2X1
MXI2X2
MXI2X4
Height (µm) Width (µm)
5.0
5.0
5.04
5.04
Functional Schematic
A
s0n
Y
B
s0
s0n
S0
s0
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
125
4.6
4.6
5.28
9.24
MXI2
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
S0
A
B
XL
X1
X2
X4
0.0254
0.0167
0.0173
0.0288
0.0204
0.0249
0.0517
0.0354
0.0429
0.0954
0.0755
0.0891
S0
A
B
XL
X1
X2
X4
0.0061
0.0027
0.0020
0.0067
0.0039
0.0039
0.0100
0.0068
0.0062
0.0207
0.0133
0.0134
Delay Tables at 25 oC, 1.8V, Typical Process
Intrinsic Delay (ns)
Description
XL
X1
X2
X4
S0 → Y↑
0.051
0.053
0.058
0.053
→
→
→
→
→
0.056
0.060
0.043
0.081
0.047
0.068
0.049
0.038
0.052
0.035
0.057
0.049
0.042
0.051
0.044
0.062
0.046
0.041
0.051
0.038
S0
A
A
B
B
Y↓
Y↑
Y↓
Y↑
Y↓
Kload (ns/pF)
Description
S0
S0
A
A
B
B
→
→
→
→
→
→
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
XL
X1
X2
X4
9.538
4.415
7.047
3.894
9.706
4.701
4.872
2.791
4.901
2.852
4.900
2.850
2.729
2.058
2.739
1.772
2.786
2.136
1.305
0.884
1.312
0.903
1.309
0.900
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
126
MXI4
Your logo here
Cell Description
Logic Symbol
The MXI4 cell is a 4-to-1 multiplexer with inverted
output. The state of the select inputs (S1, S0)
determines which data input (A, B, C, D) is presented
to the output (Y). The output (Y) is represented by
the logic equation:
A
B
C
D
Y = ( S0 • S1 • A )+( S0 • S1 • B )+( S0 • S1 • C )+(S0 • S1 • D )
Y
S1 S0
Functions
Cell Size
S1
S0
A
B
C
D
Y
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
x
x
x
x
x
x
x
x
0
1
x
x
x
x
x
x
x
x
0
1
x
x
x
x
x
x
x
x
0
1
1
0
1
0
1
0
1
0
Drive Strength
MXI4XL
MXI4X1
MXI4X2
MXI4X4
Height (µm) Width (µm)
5.0
5.0
5.0
5.04
15.2
15.2
15.8
16.50
Functional Schematic
A
s0n
s1n
s0n
S0
s0
B
s0
s1n
s1n
C
s0n
s1
Y
S1
s1
D
s0
s1
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
127
MXI4
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
S0
S1
A
B
C
D
XL
X1
X2
X4
0.0642
0.0341
0.0440
0.0477
0.0383
0.0395
0.0615
0.0348
0.0465
0.0489
0.0400
0.0417
0.1027
0.0586
0.0835
0.0898
0.0665
0.0704
0.1431
0.0825
0.1149
0.1200
0.0937
0.1006
S0
S1
A
B
C
D
XL
X1
X2
X4
0.0101
0.0044
0.0021
0.0020
0.0021
0.0021
0.0084
0.0042
0.0026
0.0025
0.0026
0.0025
0.0138
0.0052
0.0045
0.0045
0.0046
0.0044
0.0169
0.0062
0.0055
0.0057
0.0057
0.0054
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
S0
S0
S1
S1
A
A
B
B
C
C
D
D
→
→
→
→
→
→
→
→
→
→
→
→
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
XL
X1
X2
X4
XL
X1
X2
X4
0.251
0.302
0.136
0.138
0.263
0.247
0.265
0.246
0.243
0.236
0.247
0.235
0.229
0.259
0.129
0.121
0.225
0.209
0.227
0.207
0.208
0.199
0.210
0.198
0.201
0.230
0.123
0.107
0.199
0.188
0.205
0.188
0.176
0.171
0.177
0.172
0.208
0.252
0.134
0.119
0.207
0.216
0.211
0.213
0.174
0.190
0.178
0.187
6.253
3.534
6.250
3.525
6.252
3.534
6.253
3.534
6.251
3.526
6.253
3.525
4.522
2.487
4.519
2.478
4.521
2.488
4.521
2.488
4.521
2.486
4.520
2.486
2.307
1.232
2.307
1.226
2.308
1.232
2.308
1.232
2.307
1.227
2.307
1.227
1.120
0.620
1.119
0.618
1.120
0.620
1.120
0.620
1.119
0.618
1.119
0.618
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
128
NAND2
Your logo here
Cell Description
Logic Symbol
The NAND2 cell provides the logical NAND of two
inputs (A, B). The output (Y) is represented by the
logic equation:
A
Y
B
Y = ( A • B)
Cell Size
Functions
A
0
x
1
B
x
0
1
Y
Drive Strength
1
1
0
NAND2XL
NAND2X1
NAND2X2
NAND2X4
Height (µm) Width (µm)
5.0
5.0
5.0
5.0
Functional Schematic
A
B
Y
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
129
2.0
2.0
3.3
4.6
NAND2
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
A
B
XL
X1
X2
X4
0.0098
0.0123
0.0135
0.0169
0.0260
0.0338
0.0508
0.0660
A
B
XL
X1
X2
X4
0.0031
0.0029
0.0040
0.0038
0.0079
0.0082
0.0158
0.0154
Delay at 25 oC, 1.8V, Typical Process
Intrinsic Delay (ns)
Description
XL
X1
X2
X4
A → Y↑
0.028
0.027
0.025
0.025
A → Y↓
B → Y↑
B → Y↓
0.018
0.035
0.023
0.017
0.034
0.021
0.016
0.033
0.021
0.015
0.033
0.020
Kload (ns/pF)
Description
A
A
B
B
→
→
→
→
Y↑
Y↓
Y↑
Y↓
XL
X1
X2
X4
6.234
3.893
6.229
3.901
4.512
2.782
4.512
2.786
2.211
1.356
2.211
1.358
1.179
0.680
1.178
0.681
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
130
NAND2B
Your logo here
Cell Description
Logic Symbol
The NAND2B cell provides the logical NAND of one
inverted input (AN) and one non-inverted input (B).
The output (Y) is represented by the logic equation:
AN
Y
B
Y = ( AN • B )
Cell Size
Functions
AN
1
x
0
B
x
0
1
Y
Drive Strength
1
1
0
NAND2BXL
NAND2BX1
NAND2BX2
NAND2BX4
Height (µm) Width (µm)
5.0
5.0
5.0
5.0
Functional Schematic
AN
B
Y
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
131
2.6
2.6
4.0
5.3
NAND2B
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
AN
B
XL
X1
X2
X4
0.0156
0.0101
0.0184
0.0138
0.0336
0.0252
0.0657
0.0488
AN
B
XL
X1
X2
X4
0.0017
0.0030
0.0017
0.0040
0.0026
0.0083
0.0047
0.0157
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
AN
AN
B
B
→
→
→
→
Y↑
Y↓
Y↑
Y↓
XL
X1
X2
X4
XL
X1
X2
X4
0.059
0.081
0.035
0.025
0.064
0.090
0.034
0.024
0.066
0.088
0.032
0.024
0.065
0.083
0.032
0.023
6.240
3.937
6.234
3.912
4.518
2.738
4.516
2.724
2.244
1.369
2.252
1.362
1.180
0.686
1.179
0.683
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
132
NAND3
Your logo here
Cell Description
Logic Symbol
The NAND3 cell provides the logical NAND of three
inputs (A, B, C). The output (Y) is represented by the
logic equation:
A
B
C
Y
Y = ( A • B • C)
Cell Size
Functions
A
B
C
Y
Drive Strength
0
x
x
1
x
0
x
1
x
x
0
1
1
1
1
0
NAND3XL
NAND3X1
NAND3X2
NAND3X4
Height (µm) Width (µm)
5.0
5.0
5.0
5.0
Functional Schematic
A
B
Y
C
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
133
2.6
2.6
4.6
6.6
NAND3
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
A
B
C
XL
X1
X2
X4
0.0111
0.0153
0.0186
0.0168
0.0216
0.0253
0.0279
0.0369
0.0496
0.0461
0.0637
0.0774
A
B
C
XL
X1
X2
X4
0.0034
0.0032
0.0032
0.0048
0.0047
0.0045
0.0084
0.0088
0.0094
0.0144
0.0139
0.0142
Delays at 25 oC, 1.8V, Typical Process
Intrinsic Delay (ns)
Description
A → Y↑
A
B
B
C
C
→
→
→
→
→
Y↓
Y↑
Y↓
Y↑
Y↓
XL
X1
X2
X4
0.041
0.034
0.031
0.032
0.029
0.050
0.036
0.059
0.039
0.024
0.043
0.031
0.051
0.033
0.020
0.040
0.027
0.050
0.031
0.020
0.042
0.027
0.051
0.031
Kload (ns/pF)
Description
A
A
B
B
C
C
→
→
→
→
→
→
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
XL
X1
X2
X4
6.234
4.396
6.233
4.403
6.236
4.404
4.151
3.005
4.150
3.009
4.152
3.009
2.209
1.503
2.209
1.504
2.211
1.505
1.449
0.961
1.447
0.962
1.448
0.962
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
134
NAND3B
Your logo here
Cell Description
Logic Symbol
The NAND3B cell provides the logical NAND of one
inverted input (AN) and two non-inverted inputs (B,
C). The output (Y) is represented by the logic
equation:
AN
B
C
Y
Y = ( AN • B • C )
Cell Size
Functions
Drive Strength
AN
B
C
Y
1
x
x
0
x
0
x
1
x
x
0
1
1
1
1
0
NAND3BXL
NAND3BX1
NAND3BX2
NAND3BX4
Height (µm) Width (µm)
5.0
5.0
5.0
5.0
Functional Schematic
AN
B
Y
C
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
135
3.3
3.3
5.3
7.3
NAND3B
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
AN
B
C
XL
X1
X2
X4
0.0228
0.0128
0.0153
0.0242
0.0168
0.0221
0.0388
0.0295
0.0407
0.0635
0.0485
0.0657
AN
B
C
XL
X1
X2
X4
0.0017
0.0033
0.0032
0.0017
0.0047
0.0047
0.0028
0.0088
0.0096
0.0049
0.0138
0.0143
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
AN
AN
B
B
C
C
→
→
→
→
→
→
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
XL
X1
X2
X4
XL
X1
X2
X4
0.078
0.100
0.049
0.038
0.058
0.041
0.075
0.101
0.042
0.034
0.050
0.037
0.071
0.087
0.040
0.030
0.049
0.034
0.067
0.081
0.039
0.030
0.049
0.033
6.246
4.429
6.239
4.413
6.240
4.413
4.156
3.025
4.153
3.016
4.154
3.016
2.212
1.512
2.211
1.508
2.212
1.508
1.410
0.972
1.410
0.970
1.415
0.970
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
136
NAND4
Your logo here
Cell Description
Logic Symbol
The NAND4 cell provides a logical NAND of four
inputs (A, B, C, D). The output (Y) is represented by
the logic equation:
A
B
C
D
Y = ( A • B • C • D)
Y
Cell Size
Functions
A
B
C
D
Y
Drive Strength
0
x
x
x
1
x
0
x
x
1
x
x
0
x
1
x
x
x
0
1
1
1
1
1
0
NAND4XL
NAND4X1
NAND4X2
NAND4X4
Height (µm) Width (µm)
5.0
5.0
5.0
5.0
Functional Schematic
A
B
C
D
Y
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
137
3.3
3.3
5.9
11.2
NAND4
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
A
B
C
D
XL
X1
X2
X4
0.0127
0.0170
0.0202
0.0239
0.0177
0.0229
0.0286
0.0330
0.0320
0.0452
0.0542
0.0646
0.0648
0.0911
0.1096
0.1305
A
B
C
D
XL
X1
X2
X4
0.0033
0.0035
0.0035
0.0032
0.0048
0.0047
0.0047
0.0046
0.0089
0.0091
0.0095
0.0098
0.0185
0.0189
0.0194
0.0204
Delays at 25 oC, 1.8V, Typical Process
Intrinsic Delay (ns)
Description
A → Y↑
A
B
B
C
C
D
D
→
→
→
→
→
→
→
Y↓
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
XL
X1
X2
X4
0.040
0.037
0.035
0.035
0.028
0.052
0.040
0.062
0.045
0.069
0.048
0.025
0.048
0.035
0.057
0.041
0.066
0.044
0.024
0.046
0.033
0.056
0.039
0.065
0.043
0.024
0.046
0.033
0.056
0.039
0.066
0.043
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Description
A
A
B
B
C
C
D
D
→
→
→
→
→
→
→
→
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
XL
X1
X2
X4
6.236
5.028
6.231
5.037
6.236
5.038
6.256
5.036
4.372
3.459
4.366
3.464
4.371
3.463
4.380
3.463
2.211
1.730
2.208
1.732
2.210
1.732
2.215
1.732
1.106
0.865
1.104
0.866
1.105
0.866
1.107
0.866
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
138
NAND4B
Your logo here
Cell Description
Logic Symbol
The NAND4B cell provides a logical NAND of one
inverted input (AN) and three non-inverted inputs (B,
C, D). The output (Y) is represented by the logic
equation:
AN
B
C
D
Y
Y = ( AN • B • C • D )
Cell Size
Functions
Drive Strength
AN
B
C
D
Y
1
x
x
x
0
x
0
x
x
1
x
x
0
x
1
x
x
x
0
1
1
1
1
1
0
NAND4BXL
NAND4BX1
NAND4BX2
NAND4BX4
Height (µm) Width (µm)
5.0
5.0
5.0
5.0
Functional Schematic
AN
B
C
D
Y
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
139
4.0
4.6
6.6
11.9
NAND4B
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
AN
B
C
D
XL
X1
X2
X4
0.0201
0.0145
0.0179
0.0213
0.0238
0.0196
0.0252
0.0290
0.0420
0.0350
0.0456
0.0540
0.0841
0.0699
0.0850
0.1080
AN
B
C
D
XL
X1
X2
X4
0.0017
0.0034
0.0033
0.0031
0.0017
0.0047
0.0047
0.0045
0.0029
0.0091
0.0095
0.0100
0.0052
0.0188
0.0194
0.0206
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
AN
AN
B
B
C
C
D
D
→
→
→
→
→
→
→
→
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
XL
X1
X2
X4
XL
X1
X2
X4
0.079
0.099
0.054
0.044
0.064
0.050
0.073
0.053
0.081
0.104
0.050
0.040
0.059
0.046
0.068
0.049
0.076
0.092
0.045
0.036
0.055
0.042
0.065
0.046
0.075
0.090
0.045
0.036
0.055
0.042
0.066
0.046
6.245
5.051
6.236
5.044
6.239
5.043
6.255
5.044
4.375
3.475
4.369
3.469
4.374
3.470
4.380
3.469
2.213
1.737
2.210
1.734
2.211
1.734
2.215
1.735
1.106
0.869
1.105
0.867
1.106
0.867
1.107
0.868
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
140
NAND4BB
Your logo here
Cell Description
Logic Symbol
The NAND4BB cell provides a logical NAND of two
inverted inputs (AN, BN) and two non-inverted inputs
(C, D). The output (Y) is represented by the logic
equation:
AN
BN
C
D
Y
Y = ( AN • BN • C • D )
Cell Size
Functions
Drive Strength
AN
BN
C
D
Y
1
x
x
x
0
x
1
x
x
0
x
x
0
x
1
x
x
x
0
1
1
1
1
1
0
NAND4BBXL
NAND4BBX1
NAND4BBX2
NAND4BBX4
Height (µm) Width (µm)
5.0
5.0
5.0
5.0
Functional Schematic
AN
BN
C
D
Y
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
141
5.3
5.3
7.3
12.5
NAND4BB
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
AN
BN
C
D
XL
X1
X2
X4
0.0207
0.0246
0.0153
0.0184
0.0247
0.0305
0.0199
0.0245
0.0435
0.0533
0.0370
0.0470
0.0859
0.1054
0.0724
0.0934
AN
BN
C
D
XL
X1
X2
X4
0.0017
0.0017
0.0034
0.0033
0.0017
0.0017
0.0048
0.0047
0.0029
0.0029
0.0096
0.0101
0.0052
0.0054
0.0194
0.0204
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
AN
AN
BN
BN
C
C
D
D
→
→
→
→
→
→
→
→
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
XL
X1
X2
X4
XL
X1
X2
X4
0.079
0.099
0.089
0.108
0.063
0.051
0.072
0.054
0.081
0.103
0.092
0.114
0.058
0.047
0.067
0.051
0.077
0.093
0.089
0.104
0.055
0.044
0.065
0.049
0.076
0.091
0.088
0.100
0.055
0.044
0.065
0.049
6.245
5.051
6.242
5.063
6.245
5.049
6.260
5.048
4.375
3.475
4.374
3.485
4.377
3.475
4.383
3.474
2.211
1.737
2.212
1.740
2.214
1.736
2.217
1.737
1.106
0.869
1.106
0.870
1.106
0.868
1.108
0.868
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
142
NOR2
Your logo here
Cell Description
Logic Symbol
The NOR2 cell provides a logical NOR of two inputs
(A, B). The output (Y) is represented by the logic
equation:
A
Y
B
Y = ( A + B)
Cell Size
Functions
A
0
x
1
B
0
1
x
Y
Drive Strength
1
0
0
NOR2XL
NOR2X1
NOR2X2
NOR2X4
Height (µm) Width (µm)
5.0
5.0
5.0
5.0
Functional Schematic
A
B
Y
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
143
2.0
2.0
3.3
4.6
NOR2
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
A
B
XL
X1
X2
X4
0.0099
0.0130
0.0131
0.0166
0.0249
0.0340
0.0498
0.0668
A
B
XL
X1
X2
X4
0.0032
0.0028
0.0043
0.0039
0.0081
0.0082
0.0165
0.0155
Delays at 25 oC, 1.8V, Typical Process
Intrinsic Delay (ns)
Description
XL
X1
X2
X4
A → Y↑
0.038
0.037
0.031
0.031
A → Y↓
B → Y↑
B → Y↓
0.019
0.047
0.023
0.018
0.045
0.022
0.015
0.040
0.020
0.016
0.039
0.020
Kload (ns/pF)
Description
A
A
B
B
→
→
→
→
Y↑
Y↓
Y↑
Y↓
XL
X1
X2
X4
9.465
3.366
9.455
3.386
6.723
2.403
6.720
2.410
3.361
1.195
3.360
1.199
1.649
0.597
1.648
0.599
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
144
NOR2B
Your logo here
Cell Description
Logic Symbol
The NOR2B cell provides a logical NOR of
one inverted input (AN) and one non-inverted input
(B). The output (Y) is represented by the logic
equation:
AN
Y
B
Y = ( AN + B )
Cell Size
Functions
Drive Strength
AN
B
Y
1
x
0
0
1
x
1
0
0
NOR2BXL
NOR2BX1
NOR2BX2
NOR2BX4
Height (µm) Width (µm)
5.0
5.0
5.0
5.0
Functional Schematic
AN
B
Y
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
145
2.6
2.6
4.0
5.3
NOR2B
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
AN
B
XL
X1
X2
X4
0.0173
0.0126
0.0203
0.0178
0.0307
0.0331
0.0631
0.0658
AN
B
XL
X1
X2
X4
0.0017
0.0031
0.0017
0.0042
0.0028
0.0084
0.0049
0.0158
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
AN
AN
B
B
→
→
→
→
Y↑
Y↓
Y↑
Y↓
XL
X1
X2
X4
XL
X1
X2
X4
0.069
0.087
0.049
0.022
0.073
0.099
0.048
0.022
0.066
0.086
0.042
0.020
0.066
0.088
0.042
0.020
9.473
3.302
9.460
3.263
6.726
2.435
6.722
2.411
3.363
1.210
3.361
1.199
1.642
0.605
1.641
0.600
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
146
NOR3
Your logo here
Cell Description
Logic Symbol
The NOR3 cell provides a logical NOR of three inputs
(A, B, C). The output (Y) is represented by the logic
equation:
A
B
C
Y
Y = ( A + B + C)
Cell Size
Functions
A
B
C
Y
Drive Strength
0
x
x
1
0
x
1
x
0
1
x
x
1
0
0
0
NOR3XL
NOR3X1
NOR3X2
NOR3X4
Height (µm) Width (µm)
5.0
5.0
5.0
5.0
Functional Schematic
A
B
Y
C
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2.6
2.6
4.6
6.6
NOR3
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
A
B
C
XL
X1
X2
X4
0.0126
0.0164
0.0197
0.0171
0.0223
0.0280
0.0329
0.0432
0.0546
0.0521
0.0649
0.0872
A
B
C
XL
X1
X2
X4
0.0035
0.0033
0.0032
0.0047
0.0045
0.0043
0.0090
0.0094
0.0095
0.0158
0.0150
0.0147
Delays at 25 oC, 1.8V, Typical Process
Intrinsic Delay (ns)
Description
A → Y↑
A
B
B
C
C
→
→
→
→
→
Y↓
Y↑
Y↓
Y↑
Y↓
XL
X1
X2
X4
0.055
0.051
0.044
0.043
0.022
0.080
0.028
0.088
0.030
0.022
0.075
0.028
0.082
0.031
0.020
0.069
0.026
0.077
0.030
0.019
0.067
0.025
0.074
0.029
Kload (ns/pF)
Description
A
A
B
B
C
C
→
→
→
→
→
→
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
XL
X1
X2
X4
12.252
3.238
12.237
3.257
12.235
3.302
8.498
2.398
8.494
2.407
8.493
2.429
4.248
1.193
4.247
1.197
4.247
1.207
2.579
0.703
2.578
0.705
2.578
0.709
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
148
NOR3B
Your logo here
Cell Description
Logic Symbol
The NOR3B cell provides a logical NOR of
one inverted input (AN) and two non-inverted inputs
(B, C). The output (Y) is represented by the logic
equation:
AN
B
C
Y
Y = ( AN + B + C )
Cell Size
Functions
Drive Strength
AN
B
C
Y
1
x
x
0
0
x
1
x
0
1
x
x
1
0
0
0
NOR3BXL
NOR3BX1
NOR3BX2
NOR3BX4
Height (µm) Width (µm)
5.0
5.0
5.0
5.0
Functional Schematic
AN
B
Y
C
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149
4.0
4.0
5.3
7.3
NOR3B
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
AN
B
C
XL
X1
X2
X4
0.0185
0.0166
0.0208
0.0232
0.0227
0.0272
0.0352
0.0424
0.0545
0.0655
0.0692
0.0911
AN
B
C
XL
X1
X2
X4
0.0015
0.0033
0.0032
0.0016
0.0045
0.0044
0.0029
0.0090
0.0096
0.0047
0.0156
0.0157
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
AN
AN
B
B
C
C
→
→
→
→
→
→
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
XL
X1
X2
X4
XL
X1
X2
X4
0.088
0.095
0.082
0.028
0.089
0.030
0.088
0.102
0.077
0.028
0.083
0.031
0.079
0.092
0.069
0.025
0.077
0.030
0.079
0.095
0.067
0.026
0.075
0.030
12.258
3.300
12.237
3.258
12.234
3.301
8.499
2.431
8.493
2.408
8.493
2.429
4.250
1.209
4.247
1.198
4.248
1.207
2.435
0.711
2.433
0.705
2.433
0.709
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
150
NOR4
Your logo here
Cell Description
Logic Symbol
The NOR4 cell provides a logical NOR of four inputs
(A, B, C, D). The output (Y) is represented by the logic
equation:
A
B
C
D
Y = ( A + B + C + D)
Y
Cell Size
Functions
A
B
C
D
Y
Drive Strength
0
x
x
x
1
0
x
x
1
x
0
x
1
x
x
0
1
x
x
x
1
0
0
0
0
NOR4XL
NOR4X1
NOR4X2
NOR4X4
Height (µm) Width (µm)
5.0
5.0
5.0
5.0
Functional Schematic
A
B
C
D
Y
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151
4.0
4.0
5.9
11.2
NOR4
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
A
B
C
D
XL
X1
X2
X4
0.0149
0.0195
0.0237
0.0277
0.0198
0.0265
0.0324
0.0386
0.0366
0.0487
0.0613
0.0756
0.0678
0.0920
0.1110
0.1388
A
B
C
D
XL
X1
X2
X4
0.0039
0.0038
0.0037
0.0035
0.0052
0.0051
0.0050
0.0048
0.0099
0.0100
0.0105
0.0109
0.0187
0.0194
0.0192
0.0193
Delays at 25 oC, 1.8V, Typical Process
Intrinsic Delay (ns)
Description
A
A
B
B
C
C
D
D
→
→
→
→
→
→
→
→
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
XL
X1
X2
X4
0.062
0.025
0.101
0.033
0.124
0.037
0.131
0.037
0.054
0.024
0.094
0.033
0.115
0.039
0.121
0.039
0.043
0.020
0.081
0.030
0.102
0.034
0.110
0.036
0.048
0.021
0.088
0.031
0.108
0.035
0.117
0.036
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Description
A
A
B
B
C
C
D
D
→
→
→
→
→
→
→
→
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
XL
X1
X2
X4
13.903
3.239
13.889
3.266
13.895
3.299
13.890
3.351
9.471
2.402
9.468
2.413
9.468
2.428
9.467
2.454
4.736
1.195
4.735
1.200
4.734
1.208
4.735
1.221
2.743
0.664
2.743
0.667
2.743
0.671
2.743
0.677
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
152
NOR4B
Your logo here
Cell Description
Logic Symbol
The NOR4B cell provides a logical NOR of
one inverted input (AN) and three non-inverted
inputs (B, C, D). The output (Y) is represented by the
logic equation:
AN
B
C
D
Y
Y = ( AN + B + C + D )
Cell Size
Functions
Drive Strength
AN
B
C
D
Y
1
x
x
x
0
0
x
x
1
x
0
x
1
x
x
0
1
x
x
x
1
0
0
0
0
NOR4BXL
NOR4BX1
NOR4BX2
NOR4BX4
Height (µm) Width (µm)
5.0
5.0
5.0
5.0
Functional Schematic
AN
B
C
D
Y
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
153
4.0
4.0
6.6
11.9
NOR4B
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
AN
B
C
D
XL
X1
X2
X4
0.0216
0.0198
0.0237
0.0279
0.0261
0.0268
0.0323
0.0400
0.0414
0.0513
0.0637
0.0768
0.0734
0.0921
0.1137
0.1377
AN
B
C
D
XL
X1
X2
X4
0.0016
0.0037
0.0037
0.0037
0.0019
0.0050
0.0050
0.0051
0.0033
0.0100
0.0105
0.0107
0.0052
0.0191
0.0192
0.0196
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
AN
AN
B
B
C
C
D
D
→
→
→
→
→
→
→
→
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
XL
X1
X2
X4
XL
X1
X2
X4
0.097
0.108
0.103
0.033
0.125
0.037
0.132
0.037
0.092
0.108
0.096
0.033
0.117
0.039
0.123
0.040
0.082
0.098
0.084
0.030
0.106
0.035
0.112
0.036
0.083
0.100
0.089
0.030
0.109
0.035
0.118
0.036
13.912
3.307
13.893
3.266
13.894
3.299
13.889
3.351
9.475
2.430
9.469
2.411
9.468
2.429
9.468
2.454
4.737
1.208
4.735
1.199
4.736
1.208
4.735
1.220
2.745
0.671
2.743
0.666
2.743
0.671
2.743
0.677
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
154
NOR4BB
Your logo here
Cell Description
Logic Symbol
The NOR4BB cell provides a logical NOR of two
inverted inputs (AN, BN) and two non-inverted inputs
(C, D). The output (Y) is represented by the logic
equation:
AN
BN
C
D
Y
Y = ( AN + BN + C + D )
Cell Size
Functions
Drive Strength
AN
BN
C
D
Y
1
x
x
x
0
1
x
x
0
x
0
x
1
x
x
0
1
x
x
x
1
0
0
0
0
NOR4BBXL
NOR4BBX1
NOR4BBX2
NOR4BBX4
Height (µm) Width (µm)
5.0
5.0
5.0
5.0
Functional Schematic
AN
BN
C
D
Y
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
155
5.3
5.3
7.3
13.2
NOR4BB
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
AN
BN
C
D
XL
X1
X2
X4
0.0209
0.0228
0.0253
0.0294
0.0266
0.0304
0.0336
0.0405
0.0412
0.0526
0.0653
0.0774
0.0733
0.0950
0.1158
0.1377
AN
BN
C
D
XL
X1
X2
X4
0.0017
0.0020
0.0037
0.0037
0.0019
0.0023
0.0050
0.0050
0.0033
0.0037
0.0105
0.0110
0.0052
0.0052
0.0192
0.0194
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
AN
AN
BN
BN
C
C
D
D
→
→
→
→
→
→
→
→
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
XL
X1
X2
X4
XL
X1
X2
X4
0.101
0.108
0.147
0.119
0.132
0.038
0.140
0.039
0.095
0.108
0.137
0.120
0.120
0.039
0.127
0.040
0.084
0.099
0.122
0.110
0.108
0.035
0.115
0.037
0.084
0.100
0.128
0.115
0.112
0.035
0.121
0.037
13.905
3.301
13.902
3.303
13.892
3.302
13.891
3.350
9.474
2.429
9.472
2.429
9.468
2.428
9.467
2.453
4.738
1.208
4.735
1.208
4.734
1.208
4.735
1.220
2.745
0.671
2.745
0.671
2.743
0.671
2.743
0.677
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
156
OAI21
Your logo here
Cell Description
Logic Symbol
The OAI21 cell provides the logical inverted AND of
one OR group and an additional input. The output
(Y) is represented by the logic equation:
A0
A1
Y = ( A0 + A1 ) • B0
B0
Y
Functions
Cell Size
A0
A1
B0
Y
0
x
x
1
0
x
1
x
x
0
1
1
1
1
0
0
Drive Strength
OAI21XL
OAI21X1
OAI21X2
OAI21X4
Height (µm) Width (µm)
5.0
5.0
5.0
5.0
Functional Schematic
A0
A1
Y
B0
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
157
2.6
3.3
5.3
7.3
OAI21
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
A0
A1
B0
XL
X1
X2
X4
0.0165
0.0188
0.0133
0.0222
0.0257
0.0174
0.0417
0.0515
0.0323
0.0783
0.0954
0.0676
A0
A1
B0
XL
X1
X2
X4
0.0033
0.0032
0.0030
0.0045
0.0043
0.0040
0.0094
0.0086
0.0078
0.0183
0.0174
0.0152
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
A0
A0
A1
A1
B0
B0
→
→
→
→
→
→
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
XL
X1
X2
X4
XL
X1
X2
X4
0.067
0.030
0.078
0.037
0.031
0.027
0.064
0.028
0.074
0.035
0.029
0.026
0.065
0.030
0.073
0.036
0.030
0.026
0.053
0.025
0.062
0.031
0.026
0.023
9.468
3.903
9.463
3.915
6.243
3.908
6.723
2.717
6.722
2.722
4.520
2.718
3.362
1.376
3.361
1.378
2.260
1.376
1.627
0.682
1.626
0.683
1.161
0.682
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
158
OAI211
Your logo here
Cell Description
Logic Symbol
The OAI211 cell provides the logical inverted OR of
one OR group and two additional inputs. The output
(Y) is represented by the logic equation:
A0
A1
Y = ( A0 + A1 ) • B0 • C0
B0
Y
C0
Functions
A0
A1
B0
C0
Y
0
x
x
x
1
0
x
x
1
x
x
0
x
1
1
x
x
0
1
1
1
1
1
0
0
Cell Size
Drive Strength
OAI211XL
OAI211X1
OAI211X2
OAI211X4
Height (µm) Width (µm)
5.0
5.0
5.0
5.0
Functional Schematic
A0
A1
B0
Y
C0
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
159
4.0
4.0
6.6
5.9
OAI211
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
A0
A1
B0
C0
XL
X1
X2
X4
0.0230
0.0252
0.0146
0.0199
0.0296
0.0345
0.0210
0.0267
0.0568
0.0675
0.0379
0.0484
0.0791
0.0833
0.0674
0.0715
A0
A1
B0
C0
XL
X1
X2
X4
0.0035
0.0034
0.0032
0.0032
0.0049
0.0046
0.0043
0.0043
0.0100
0.0092
0.0082
0.0085
0.0032
0.0032
0.0032
0.0029
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
A0
A0
A1
A1
B0
B0
C0
C0
→
→
→
→
→
→
→
→
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
XL
X1
X2
X4
XL
X1
X2
X4
0.099
0.044
0.109
0.052
0.040
0.035
0.050
0.044
0.096
0.041
0.106
0.049
0.039
0.033
0.049
0.041
0.092
0.040
0.100
0.047
0.037
0.031
0.047
0.039
0.243
0.173
0.254
0.183
0.158
0.167
0.169
0.175
9.481
4.407
9.477
4.417
6.238
4.411
6.240
4.419
6.730
3.034
6.726
3.040
4.519
3.036
4.520
3.040
3.365
1.510
3.364
1.517
2.338
1.516
2.337
1.518
1.109
0.610
1.109
0.610
1.109
0.610
1.109
0.610
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
160
OAI22
Your logo here
Cell Description
Logic Symbol
The OAI22 cell provides the logical inverted AND of
two OR groups. The output (Y) is represented by the
logic equation:
A0
A1
Y = ( A0 + A1 ) • ( B0 + B1 )
Y
B0
B1
Functions
A0
A1
B0
B1
Y
0
x
x
x
1
1
0
x
1
1
x
x
x
0
x
1
x
1
x
0
1
x
1
x
1
1
0
0
0
0
Cell Size
Drive Strength
OAI22XL
OAI22X1
OAI22X2
OAI22X4
Height (µm) Width (µm)
5.0
5.0
5.0
5.0
Functional Schematic
A0
A1
Y
B0
B1
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
161
4.0
4.0
5.9
9.2
OAI22
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
A0
A1
B0
B1
XL
X1
X2
X4
0.0156
0.0188
0.0231
0.0266
0.0202
0.0256
0.0301
0.0355
0.0411
0.0513
0.0577
0.0682
0.0832
0.1014
0.1155
0.1336
A0
A1
B0
B1
XL
X1
X2
X4
0.0034
0.0034
0.0034
0.0032
0.0047
0.0046
0.0046
0.0043
0.0095
0.0087
0.0092
0.0086
0.0182
0.0174
0.0181
0.0175
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
A0
A0
A1
A1
B0
B0
B1
B1
→
→
→
→
→
→
→
→
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
XL
X1
X2
X4
XL
X1
X2
X4
0.048
0.030
0.059
0.037
0.089
0.043
0.098
0.050
0.045
0.028
0.055
0.035
0.082
0.040
0.091
0.046
0.050
0.032
0.059
0.038
0.082
0.042
0.091
0.048
0.046
0.031
0.054
0.037
0.075
0.040
0.083
0.046
9.495
3.910
9.492
3.922
9.470
3.917
9.463
3.923
6.742
2.720
6.738
2.724
6.725
2.723
6.721
2.726
3.370
1.395
3.368
1.397
3.362
1.397
3.360
1.398
1.631
0.701
1.631
0.702
1.627
0.701
1.626
0.702
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
162
OAI221
Your logo here
Cell Description
Logic Symbol
The OAI221 cell provides the logical inverted AND
of two OR groups and an additional input. The output
(Y) is represented by the logic equation:
A0
A1
Y = ( A0 + A1 ) • ( B0 + B1 ) • C0
B0
B1
Functions
Y
C0
A0
A1
B0
B1
C0
Y
0
x
x
x
x
1
1
0
x
x
1
1
x
x
x
0
x
x
1
x
1
x
0
x
1
x
1
x
x
x
0
1
1
1
1
1
1
1
0
0
0
0
Cell Size
Drive Strength
OAI221XL
OAI221X1
OAI221X2
OAI221X4
Height (µm) Width (µm)
5.0
5.0
5.0
5.0
Functional Schematic
A0
A1
B0
B1
Y
C0
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
163
4.6
5.3
8.6
7.3
OAI221
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
A0
A1
B0
B1
C0
XL
X1
X2
X4
0.0234
0.0262
0.0299
0.0337
0.0191
0.0311
0.0351
0.0402
0.0444
0.0262
0.0587
0.0690
0.0773
0.0846
0.0477
0.0730
0.0776
0.0831
0.0880
0.0664
A0
A1
B0
B1
C0
XL
X1
X2
X4
0.0037
0.0036
0.0037
0.0034
0.0033
0.0051
0.0048
0.0050
0.0046
0.0043
0.0097
0.0097
0.0098
0.0095
0.0087
0.0034
0.0033
0.0033
0.0031
0.0031
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
A0
A0
A1
A1
B0
B0
B1
B1
C0
C0
→
→
→
→
→
→
→
→
→
→
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
XL
X1
X2
X4
XL
X1
X2
X4
0.088
0.051
0.099
0.059
0.124
0.060
0.133
0.067
0.041
0.044
0.083
0.047
0.092
0.054
0.117
0.054
0.125
0.062
0.040
0.041
0.078
0.045
0.087
0.052
0.109
0.051
0.118
0.059
0.034
0.038
0.228
0.170
0.238
0.179
0.261
0.179
0.271
0.188
0.154
0.163
9.494
4.420
9.489
4.426
9.499
4.420
9.497
4.427
6.252
4.420
6.738
3.016
6.737
3.019
6.736
3.016
6.735
3.019
4.528
3.016
3.370
1.525
3.368
1.527
3.369
1.525
3.368
1.527
2.265
1.525
1.168
0.605
1.168
0.605
1.168
0.605
1.168
0.605
1.168
0.605
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
164
OAI222
Your logo here
Cell Description
Logic Symbol
The OAI222 cell provides the logical inverted AND
of three OR groups. The output (Y) is represented
by the logic equation:
Y = ( A0 + A1 ) • ( B0 + B1 ) • ( C0 + C1 )
A0
A1
B0
B1
Y
Functions
A0
A1
B0
B1
C0
C1
Y
0
x
x
x
x
x
x
1
1
1
1
0
x
x
1
1
1
1
x
x
x
x
x
0
x
x
x
1
1
x
x
1
1
x
0
x
1
1
x
x
1
1
x
x
x
x
0
1
x
1
x
1
x
1
x
x
x
0
x
1
x
1
x
1
x
1
1
1
1
0
0
0
0
0
0
0
0
C0
C1
Cell Size
Drive Strength
OAI222XL
OAI222X1
OAI222X2
OAI222X4
Height (µm) Width (µm)
5.0
5.0
5.0
5.0
Functional Schematic
A0
A1
B0
B1
Y
C0
C1
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
165
5.3
5.9
9.9
7.9
OAI222
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
A0
A1
B0
B1
C0
C1
XL
X1
X2
X4
0.0303
0.0336
0.0372
0.0404
0.0208
0.0249
0.0405
0.0442
0.0482
0.0534
0.0293
0.0326
0.0795
0.0874
0.0973
0.1057
0.0559
0.0647
0.0807
0.0866
0.0895
0.0936
0.0701
0.0746
A0
A1
B0
B1
C0
C1
XL
X1
X2
X4
0.0035
0.0036
0.0037
0.0035
0.0037
0.0035
0.0048
0.0048
0.0050
0.0047
0.0051
0.0048
0.0098
0.0097
0.0097
0.0096
0.0097
0.0100
0.0034
0.0033
0.0033
0.0032
0.0035
0.0033
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
A0
A0
A1
A1
B0
B0
B1
B1
C0
C0
C1
C1
→
→
→
→
→
→
→
→
→
→
→
→
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
XL
X1
X2
X4
XL
X1
X2
X4
0.112
0.068
0.122
0.076
0.150
0.076
0.159
0.084
0.067
0.049
0.075
0.055
0.104
0.062
0.113
0.070
0.141
0.069
0.149
0.077
0.063
0.045
0.072
0.052
0.100
0.059
0.109
0.066
0.135
0.066
0.144
0.073
0.058
0.042
0.067
0.050
0.250
0.193
0.259
0.203
0.288
0.201
0.297
0.211
0.207
0.175
0.216
0.182
9.476
4.428
9.475
4.434
9.489
4.429
9.483
4.434
9.518
4.423
9.519
4.438
6.731
3.020
6.730
3.022
6.731
3.020
6.731
3.022
6.754
3.017
6.754
3.025
3.365
1.512
3.364
1.513
3.366
1.512
3.365
1.513
3.378
1.510
3.378
1.512
1.168
0.605
1.167
0.605
1.168
0.605
1.167
0.605
1.168
0.605
1.168
0.605
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
166
OAI2BB1
Your logo here
Cell Description
Logic Symbol
The OAI2BB1 cell provides the logical inverted AND
of one OR group of two inverted inputs (A0N, A1N)
and an additional non-inverted input (B0). The output
(Y) is represented by the logic equation:
A0N
A1N
Functions
A0N A1N
1
x
x
0
1
x
0
x
Y
B0
Y = ( A0N + A1N ) • B0
Cell Size
B0
Y
Drive Strength
x
0
1
1
1
1
0
0
OAI2BB1XL
OAI2BB1X1
OAI2BB1X2
OAI2BB1X4
Height (µm) Width (µm)
5.0
5.0
5.0
5.0
Functional Schematic
A0N
A1N
Y
B0
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
167
3.3
3.3
4.6
6.6
OAI2BB1
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
A0N
A1N
B0
XL
X1
X2
X4
0.0205
0.0176
0.0101
0.0229
0.0203
0.0138
0.0395
0.0333
0.0235
0.0739
0.0657
0.0516
A0N
A1N
B0
XL
X1
X2
X4
0.0019
0.0015
0.0026
0.0018
0.0015
0.0034
0.0033
0.0026
0.0070
0.0056
0.0043
0.0126
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
A0N
A0N
A1N
A1N
B0
B0
→
→
→
→
→
→
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
XL
X1
X2
X4
XL
X1
X2
X4
0.080
0.100
0.077
0.090
0.036
0.025
0.085
0.111
0.082
0.101
0.034
0.024
0.076
0.099
0.073
0.089
0.030
0.022
0.079
0.091
0.076
0.084
0.032
0.024
6.252
3.952
6.254
3.947
6.232
3.914
4.523
2.746
4.524
2.744
4.514
2.725
2.220
1.372
2.220
1.371
2.215
1.363
1.110
0.694
1.110
0.694
1.108
0.691
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
168
OAI2BB2
Your logo here
Cell Description
Logic Symbol
The OAI2BB2 cell provides the logical inverted AND
of one OR group of two inverted inputs (A0N, A1N)
and one OR group of two non-inverted inputs (B0,
B1). The output (Y) is represented by the logic
equation:
A0N
A1N
Y
Y = ( A0N + A1N ) • ( B0 + B1 )
B0
B1
Functions
A0N A1N
1
x
x
x
0
0
1
x
0
0
x
x
B0
B1
Y
x
0
x
1
x
1
x
0
1
x
1
x
1
1
0
0
0
0
Cell Size
Drive Strength
OAI2BB2XL
OAI2BB2X1
OAI2BB2X2
OAI2BB2X4
Height (µm) Width (µm)
5.0
5.0
5.0
5.0
Functional Schematic
A0N
A1N
Y
B0
B1
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
169
4.6
4.6
6.6
9.9
OAI2BB2
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
A0N
A1N
B0
B1
XL
X1
X2
X4
0.0224
0.0185
0.0139
0.0171
0.0255
0.0212
0.0182
0.0226
0.0471
0.0387
0.0354
0.0446
0.0941
0.0713
0.0634
0.0792
A0N
A1N
B0
B1
XL
X1
X2
X4
0.0020
0.0022
0.0035
0.0034
0.0019
0.0022
0.0047
0.0045
0.0035
0.0038
0.0095
0.0097
0.0078
0.0072
0.0187
0.0176
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
A0N
A0N
A1N
A1N
B0
B0
B1
B1
→
→
→
→
→
→
→
→
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
XL
X1
X2
X4
XL
X1
X2
X4
0.083
0.112
0.080
0.093
0.070
0.034
0.079
0.040
0.088
0.122
0.085
0.104
0.064
0.032
0.073
0.038
0.087
0.117
0.083
0.099
0.061
0.032
0.071
0.038
0.081
0.111
0.077
0.092
0.055
0.031
0.064
0.037
6.261
3.946
6.251
3.943
9.472
3.916
9.469
3.924
4.530
2.742
4.525
2.742
6.725
2.725
6.722
2.729
2.264
1.387
2.262
1.387
3.363
1.380
3.362
1.382
1.113
0.696
1.111
0.696
1.627
0.693
1.627
0.694
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
170
OAI31
Your logo here
Cell Description
Logic Symbol
The OAI31 cell provides the logical inverted AND of
one OR group and an additional input. The output
(Y) is represented by the logic equation:
Y = ( A0 + A1 + A2 ) • B0
A0
A1
A2
Y
B0
Functions
A0
A1
A2
B0
Y
0
x
x
x
1
0
x
x
1
x
0
x
1
x
x
x
0
1
1
1
1
1
0
0
0
Cell Size
Drive Strength
Height (µm) Width (µm)
OAI31XL
OAI31X1
OAI31X2
OAI31X4
5.0
5.0
5.0
5.0
Functional Schematic
A0
A1
A2
Y
B0
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
171
4.0
4.0
5.9
5.9
OAI31
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
A0
A1
A2
B0
XL
X1
X2
X4
0.0171
0.0213
0.0253
0.0176
0.0228
0.0287
0.0333
0.0242
0.0454
0.0574
0.0671
0.0460
0.0758
0.0781
0.0826
0.0700
A0
A1
A2
B0
XL
X1
X2
X4
0.0037
0.0036
0.0035
0.0031
0.0049
0.0048
0.0047
0.0040
0.0097
0.0097
0.0100
0.0077
0.0035
0.0033
0.0034
0.0029
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
A0
A0
A1
A1
A2
A2
B0
B0
→
→
→
→
→
→
→
→
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
XL
X1
X2
X4
XL
X1
X2
X4
0.084
0.032
0.110
0.041
0.116
0.044
0.031
0.034
0.077
0.030
0.102
0.038
0.108
0.042
0.030
0.033
0.077
0.030
0.101
0.038
0.108
0.042
0.028
0.031
0.253
0.152
0.278
0.162
0.286
0.168
0.150
0.157
12.246
3.905
12.242
3.916
12.240
3.954
6.246
3.947
8.497
2.717
8.494
2.723
8.496
2.741
4.521
2.737
4.249
1.359
4.247
1.361
4.248
1.371
2.261
1.369
1.109
0.610
1.109
0.610
1.109
0.610
1.109
0.610
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
172
OAI32
Your logo here
Cell Description
Logic Symbol
The OAI32 cell provides the logical inverted AND of
two OR groups. The output (Y) is represented by the
logic equation:
A0
A1
A2
Y = ( A0 + A1 + A2 ) • ( B0 + B1 )
Y
B0
B1
Functions
A0
A1
A2
B0
B1
Y
0
x
x
x
x
x
1
1
0
x
x
x
1
1
x
x
0
x
1
1
x
x
x
x
x
0
x
1
1
x
1
x
x
0
1
x
x
1
x
1
1
1
0
0
0
0
0
0
Cell Size
Drive Strength
Height (µm) Width (µm)
OAI32XL
OAI32X1
OAI32X2
OAI32X4
5.0
5.0
5.04
5.0
Functional Schematic
A0
A1
A2
Y
B0
B1
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
173
4.6
4.6
7.26
6.6
OAI32
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
A0
A1
A2
B0
B1
XL
X1
X2
X4
0.0253
0.0295
0.0333
0.0203
0.0237
0.0330
0.0385
0.0431
0.0273
0.0324
0.0661
0.0781
0.0887
0.0576
0.0689
0.0827
0.0900
0.0943
0.0711
0.0735
A0
A1
A2
B0
B1
XL
X1
X2
X4
0.0037
0.0037
0.0035
0.0034
0.0034
0.0050
0.0049
0.0048
0.0047
0.0045
0.0095
0.0098
0.0099
0.0087
0.0091
0.0034
0.0034
0.0032
0.0034
0.0032
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
A0
A0
A1
A1
A2
A2
B0
B0
B1
B1
→
→
→
→
→
→
→
→
→
→
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
XL
X1
X2
X4
XL
X1
X2
X4
0.117
0.046
0.143
0.055
0.150
0.060
0.051
0.038
0.062
0.045
0.105
0.042
0.129
0.051
0.135
0.056
0.048
0.036
0.057
0.043
0.104
0.053
0.128
0.065
0.136
0.071
0.053
0.048
0.063
0.058
0.289
0.168
0.314
0.178
0.321
0.184
0.196
0.161
0.206
0.168
12.252
3.918
12.241
3.925
12.241
3.957
9.497
3.949
9.490
3.955
8.499
2.724
8.494
2.727
8.495
2.742
6.743
2.738
6.740
2.741
4.247
1.735
4.246
1.737
4.245
1.746
3.371
1.744
3.370
1.744
1.109
0.610
1.109
0.610
1.109
0.610
1.109
0.610
1.109
0.610
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
174
OAI33
Your logo here
Cell Description
Logic Symbol
The OAI33 cell provides the logical inverted AND of
two OR groups. The output (Y) is represented by the
logic equation:
A0
A1
A2
Y = ( A0 + A1 + A2 ) • ( B0 + B1 + B2 )
Y
B0
B1
B2
Functions
A0
A1
A2
B0
B1
B2
Y
0
x
x
x
x
x
x
x
1
1
1
0
x
x
x
x
1
1
1
x
x
x
0
x
1
1
1
x
x
x
x
x
x
x
0
x
x
1
x
x
1
x
x
1
x
0
x
1
x
x
1
x
x
1
x
x
0
1
x
x
1
x
x
1
x
x
1
1
0
0
0
0
0
0
0
0
0
Cell Size
Drive Strength
Height (µm) Width (µm)
OAI33XL
OAI33X1
OAI33X2
OAI33X4
5.0
5.0
5.04
5.0
Functional Schematic
A0
A1
A2
Y
B0
B1
B2
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
175
5.3
5.3
8.58
7.3
OAI33
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
A0
A1
A2
B0
B1
B2
XL
X1
X2
X4
0.0247
0.0283
0.0320
0.0330
0.0372
0.0413
0.0328
0.0383
0.0429
0.0432
0.0488
0.0541
0.0650
0.0763
0.0882
0.0874
0.0996
0.1107
0.0777
0.0833
0.0864
0.0915
0.0933
0.0981
A0
A1
A2
B0
B1
B2
XL
X1
X2
X4
0.0038
0.0036
0.0037
0.0037
0.0036
0.0035
0.0051
0.0050
0.0050
0.0050
0.0049
0.0048
0.0097
0.0099
0.0108
0.0095
0.0099
0.0099
0.0036
0.0033
0.0032
0.0035
0.0033
0.0034
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
A0
A0
A1
A1
A2
A2
B0
B0
B1
B1
B2
B2
→
→
→
→
→
→
→
→
→
→
→
→
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
XL
X1
X2
X4
XL
X1
X2
X4
0.074
0.043
0.099
0.052
0.107
0.058
0.142
0.057
0.168
0.067
0.174
0.072
0.066
0.041
0.093
0.051
0.102
0.057
0.128
0.054
0.152
0.064
0.159
0.069
0.067
0.051
0.091
0.063
0.100
0.072
0.127
0.068
0.152
0.080
0.159
0.088
0.242
0.169
0.269
0.178
0.275
0.186
0.317
0.184
0.343
0.196
0.350
0.201
12.294
3.938
12.290
3.947
12.286
3.978
12.247
3.954
12.242
3.955
12.241
3.981
8.527
2.736
8.524
2.738
8.524
2.753
8.498
2.744
8.493
2.744
8.494
2.756
4.262
1.743
4.260
1.744
4.261
1.751
4.248
1.745
4.246
1.746
4.246
1.753
1.109
0.610
1.109
0.610
1.109
0.610
1.109
0.610
1.109
0.610
1.109
0.610
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
176
OR2
Your logo here
Cell Description
Logic Symbol
The OR2 cell provides the logical OR of two inputs
(A, B). The output (Y) is represented by the logic
equation:
A
Y
B
Y = ( A + B)
Cell Size
Functions
A
0
x
1
B
0
1
x
Y
Drive Strength
0
1
1
OR2XL
OR2X1
OR2X2
OR2X4
Height (µm) Width (µm)
5.0
5.0
5.0
5.0
Functional Schematic
A
B
Y
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
177
2.6
2.6
2.6
4.0
OR2
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
A
B
XL
X1
X2
X4
0.0163
0.0190
0.0191
0.0214
0.0309
0.0356
0.0553
0.0620
A
B
XL
X1
X2
X4
0.0024
0.0024
0.0024
0.0025
0.0035
0.0034
0.0061
0.0061
Delays at 25 oC, 1.8V, Typical Process
Intrinsic Delay (ns)
Description
XL
X1
X2
X4
A → Y↑
0.059
0.062
0.064
0.057
A → Y↓
B → Y↑
B → Y↓
0.117
0.065
0.130
0.134
0.069
0.146
0.125
0.070
0.135
0.126
0.063
0.136
Kload (ns/pF)
Description
A
A
B
B
→
→
→
→
Y↑
Y↓
Y↑
Y↓
XL
X1
X2
X4
6.238
3.383
6.243
3.384
4.516
2.475
4.517
2.474
2.336
1.228
2.336
1.228
1.122
0.625
1.122
0.625
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
178
OR3
Your logo here
Cell Description
Logic Symbol
The OR3 cell provides the logical OR of three inputs
(A, B, C). The output (Y) is represented by the logic
equation:
A
B
C
Y
Y = ( A + B + C)
Cell Size
Functions
A
B
C
Y
Drive Strength
0
x
x
1
0
x
1
x
0
1
x
x
0
1
1
1
OR3XL
OR3X1
OR3X2
OR3X4
Height (µm) Width (µm)
5.0
5.0
5.0
5.04
Functional Schematic
A
B
Y
C
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
179
3.3
4.0
4.0
5.94
OR3
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
A
B
C
XL
X1
X2
X4
0.0170
0.0202
0.0215
0.0210
0.0232
0.0254
0.0349
0.0410
0.0450
0.0633
0.0730
0.0829
A
B
C
XL
X1
X2
X4
0.0025
0.0025
0.0024
0.0025
0.0025
0.0024
0.0038
0.0037
0.0037
0.0076
0.0079
0.0081
Delays at 25 oC, 1.8V, Typical Process
Intrinsic Delay (ns)
Description
A → Y↑
A
B
B
C
C
→
→
→
→
→
Y↓
Y↑
Y↓
Y↑
Y↓
XL
X1
X2
X4
0.063
0.067
0.068
0.061
0.155
0.070
0.181
0.071
0.188
0.177
0.074
0.203
0.076
0.210
0.165
0.077
0.190
0.080
0.197
0.155
0.070
0.180
0.074
0.189
Kload (ns/pF)
Description
A
A
B
B
C
C
→
→
→
→
→
→
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
XL
X1
X2
X4
6.238
3.517
6.237
3.516
6.246
3.516
4.516
2.539
4.519
2.540
4.520
2.540
2.277
1.257
2.278
1.257
2.279
1.257
1.057
0.626
1.057
0.626
1.058
0.626
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
180
OR4
Your logo here
Cell Description
Logic Symbol
The OR4 cell provides the logical OR of four inputs
(A, B, C, D). The output (Y) is represented by the logic
equation:
A
B
C
D
Y = ( A + B + C + D)
Functions
Y
Cell Size
A
B
C
D
Y
Drive Strength
0
x
x
x
1
0
x
x
1
x
0
x
1
x
x
0
1
x
x
x
0
1
1
1
1
OR4XL
OR4X1
OR4X2
OR4X4
Height (µm) Width (µm)
5.0
5.0
5.0
5.04
Functional Schematic
A
B
C
D
Y
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
181
4.0
4.0
4.0
7.26
OR4
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
A
B
C
D
XL
X1
X2
X4
0.0191
0.0224
0.0249
0.0278
0.0234
0.0260
0.0294
0.0322
0.0369
0.0416
0.0462
0.0523
0.0681
0.0793
0.0904
0.1025
A
B
C
D
XL
X1
X2
X4
0.0028
0.0025
0.0028
0.0028
0.0028
0.0025
0.0028
0.0028
0.0043
0.0041
0.0040
0.0040
0.0084
0.0087
0.0088
0.0099
Delays at 25 oC, 1.8V, Typical Process
Intrinsic Delay (ns)
Description
A
A
B
B
C
C
D
D
→
→
→
→
→
→
→
→
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
XL
X1
X2
X4
0.069
0.187
0.077
0.228
0.082
0.253
0.083
0.261
0.073
0.215
0.081
0.256
0.086
0.282
0.088
0.289
0.071
0.182
0.081
0.220
0.086
0.243
0.088
0.249
0.066
0.178
0.077
0.219
0.082
0.239
0.085
0.250
Delay Table at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Description
A
A
B
B
C
C
D
D
→
→
→
→
→
→
→
→
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
XL
X1
X2
X4
6.238
3.696
6.242
3.697
6.247
3.697
6.262
3.696
4.517
2.633
4.519
2.632
4.523
2.634
4.527
2.632
2.277
1.285
2.278
1.286
2.279
1.285
2.284
1.285
1.077
0.700
1.077
0.699
1.078
0.699
1.080
0.699
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
182
RSLAT
Your logo here
Cell Description
Logic Symbol
The RSLAT cell is an RS-type latch with active-high
set (S) and reset (R).
Function
R
S
0
0
1
1
0
1
0
1
R
Q
S
QN
Q[n+1] QN[n+1]
Q[n]
1
0
IL
QN[n]
0
1
IL
Cell Size
Drive Strength
RSLATXL
RSLATX1
RSLATX2
RSLATX4
Height (µm) Width (µm)
5.0
5.0
5.0
5.0
Functional Schematic
S
R
QN
Q
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
183
6.6
6.6
7.9
11.9
RSLAT
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
S
R
Q
XL
X1
X2
X4
0.0082
0.0092
0.0338
0.0090
0.0099
0.0449
0.0114
0.0127
0.0826
0.0211
0.0224
0.1450
S
R
XL
X1
X2
X4
0.0020
0.0022
0.0021
0.0022
0.0025
0.0026
0.0045
0.0046
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
S
R
R
S
S
R
→
→
→
→
→
→
Q↑
Q↑
Q↓
QN↑
QN↓
QN↑
XL
X1
X2
X4
XL
X1
X2
X4
0.214
0.150
0.146
0.140
0.138
0.221
0.201
0.150
0.138
0.141
0.132
0.206
0.189
0.144
0.131
0.143
0.132
0.192
0.177
0.131
0.124
0.127
0.121
0.179
6.253
6.251
3.350
6.252
3.346
6.256
4.522
4.522
2.441
4.523
2.440
4.524
2.250
2.251
1.211
2.251
1.211
2.251
1.110
1.110
0.610
1.110
0.610
1.110
Timing Constraints at 25 oC, 1.8V, Typical Process
Interval (ns)
Pin
S
R
Requirement
minpwh
minpwh
XL
X1
X2
X4
0.18
0.18
0.18
0.18
0.18
0.18
0.18
0.18
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
184
RSLATN
Your logo here
Cell Description
Logic Symbol
The RSLATN cell is an RS-type latch with active-low
set (SN) and reset (RN).
Function
RN
SN
0
0
1
1
0
1
0
1
RN
Q
SN
QN
Q[n+1] QN[n+1]
IL
0
1
Q[n]
IL
1
0
QN[n]
Cell Size
Drive Strength
RSLATNXL
RSLATNX1
RSLATNX2
RSLATNX4
Height (µm) Width (µm)
5.0
5.0
5.0
5.0
Functional Schematic
SN
RN
Q
QN
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
185
6.6
7.3
7.3
11.9
RSLATN
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
SN
RN
Q
XL
X1
X2
X4
0.0099
0.0101
0.0389
0.0111
0.0103
0.0498
0.0146
0.0159
0.0856
0.0287
0.0286
0.1488
SN
RN
XL
X1
X2
X4
0.0020
0.0022
0.0021
0.0022
0.0027
0.0029
0.0049
0.0050
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
SN
SN
RN
SN
RN
RN
→
→
→
→
→
→
Q↑
Q↓
Q↓
QN↓
QN↑
QN↓
XL
X1
X2
X4
XL
X1
X2
X4
0.138
0.192
0.286
0.288
0.142
0.197
0.147
0.176
0.283
0.277
0.154
0.182
0.138
0.159
0.253
0.248
0.140
0.160
0.127
0.146
0.231
0.230
0.128
0.146
6.250
3.276
3.277
3.285
6.248
3.285
4.519
2.484
2.484
2.485
4.522
2.486
2.250
1.228
1.228
1.227
2.250
1.228
1.125
0.612
0.613
0.613
1.125
0.613
Timing Constraints at 25 oC, 1.8V, Typical Process
Interval (ns)
Pin
SN
RN
Requirement
minpwl
minpwl
XL
X1
X2
X4
0.18
0.18
0.18
0.18
0.18
0.18
0.18
0.18
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
186
SDFF
Your logo here
Cell Description
Logic Symbol
The SDFF cell is a positive-edge triggered, static Dtype flip-flop with scan input (SI) and active-high
scan enable (SE).
D
SI
SE
CK
Functions
D
SI
SE
1
0
x
x
x
x
x
x
1
0
0
0
x
1
1
CK
Q
QN
Q[n+1] QN[n+1]
1
0
Q[n]
1
0
0
1
QN[n]
0
1
Cell Size
Drive Strength
SDFFXL
SDFFX1
SDFFX2
SDFFX4
Height (µm) Width (µm)
5.0
5.0
5.0
5.0
13.2
13.9
16.5
19.1
Functional Schematic
c
cn
c
c
SI
SE
cn
cn
QN
cn
c
D
Q
cn
CK
c
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
187
SDFF
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
XL
X1
X2
X4
SI
SE
D
CK
0.0399
0.0468
0.0344
0.0400
0.0381
0.0433
0.0329
0.0390
0.0466
0.0523
0.0415
0.0446
0.0749
0.0767
0.0638
0.0621
Q
0.0208
0.0279
0.0531
0.1023
SI
SE
D
CK
XL
X1
X2
X4
0.0023
0.0046
0.0028
0.0020
0.0021
0.0039
0.0017
0.0027
0.0022
0.0041
0.0021
0.0038
0.0021
0.0048
0.0032
0.0060
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
CK
CK
CK
CK
→
→
→
→
Q↑
Q↓
QN↑
QN↓
XL
X1
X2
X4
XL
X1
X2
X4
0.227
0.188
0.246
0.312
0.200
0.170
0.225
0.282
0.184
0.154
0.197
0.255
0.155
0.134
0.180
0.219
5.696
3.407
6.241
3.340
4.287
2.551
4.521
2.442
2.262
1.275
2.258
1.219
1.140
0.611
1.139
0.605
Timing Constraints at 25 oC, 1.8V, Typical Process
Interval (ns)
Pin
SI
SE
D
CK
Requirement
setup↑ → CK
setup↓ → CK
hold↑ → CK
hold↓ → CK
setup↑ → CK
setup↓ → CK
hold↑ → CK
hold↓ → CK
setup↑ → CK
setup↓ → CK
hold↑ → CK
hold↓ → CK
minpwh
minpwl
XL
X1
X2
X4
0.12
0.31
-0.10
-0.20
0.33
0.20
-0.09
-0.09
0.08
0.20
-0.06
-0.09
0.18
0.25
0.12
0.34
-0.09
-0.23
0.36
0.35
-0.07
-0.12
0.10
0.35
-0.07
-0.25
0.18
0.25
0.14
0.37
-0.10
-0.24
0.38
0.32
-0.09
-0.14
0.12
0.31
-0.09
-0.20
0.18
0.25
0.17
0.43
-0.12
-0.30
0.45
0.27
-0.12
-0.13
0.11
0.27
-0.08
-0.16
0.18
0.25
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
188
SDFFHQ
Your logo here
Cell Description
Logic Symbol
The SDFFHQ cell is a high-speed, positive-edge
triggered, static D-type flip-flop with scan input (SI)
and active-high scan enable (SE). The cell has a
single output (Q) and fast clock-to-out path.
D
SI
SE
CK
Functions
D
SI
SE
1
0
x
x
x
x
x
x
1
0
0
0
x
1
1
CK
Q
Q[n+1]
Cell Size
1
0
Q[n]
1
0
Drive Strength
Height (µm) Width (µm)
SDFFHQXL
SDFFHQX1
SDFFHQX2
SDFFHQX4
5.0
5.0
5.0
5.0
13.2
13.2
15.8
17.2
Functional Schematic
c
cn
c
c
SI
SE
cn
cn
cn
c
D
Q
cn
CK
c
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
189
SDFFHQ
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
XL
X1
X2
X4
SI
SE
D
CK
0.0440
0.0499
0.0387
0.0404
0.0476
0.0528
0.0434
0.0406
0.0623
0.0696
0.0562
0.0456
0.0837
0.0897
0.0754
0.0566
Q
0.0086
0.0105
0.0225
0.0380
SI
SE
D
CK
XL
X1
X2
X4
0.0022
0.0044
0.0025
0.0021
0.0022
0.0039
0.0018
0.0028
0.0022
0.0040
0.0020
0.0035
0.0021
0.0045
0.0027
0.0050
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
CK → Q↑
CK → Q↓
XL
X1
X2
X4
XL
X1
X2
X4
0.207
0.209
0.175
0.167
0.174
0.162
0.148
0.136
6.252
3.518
4.282
2.594
2.261
1.298
1.118
0.611
Timing Constraints at 25 oC, 1.8V, Typical Process
Interval (ns)
Pin
SI
SE
D
CK
Requirement
setup↑ → CK
setup↓ → CK
hold↑ → CK
hold↓ → CK
setup↑ → CK
setup↓ → CK
hold↑ → CK
hold↓ → CK
setup↑ → CK
setup↓ → CK
hold↑ → CK
hold↓ → CK
minpwh
minpwl
XL
X1
X2
X4
0.12
0.36
-0.09
-0.19
0.38
0.28
-0.08
-0.11
0.09
0.28
-0.05
-0.11
0.18
0.25
0.13
0.39
-0.09
-0.23
0.41
0.39
-0.08
-0.13
0.12
0.40
-0.08
-0.24
0.18
0.25
0.14
0.41
-0.09
-0.25
0.43
0.39
-0.08
-0.13
0.12
0.39
-0.08
-0.23
0.18
0.25
0.17
0.45
-0.12
-0.28
0.46
0.33
-0.10
-0.14
0.13
0.33
-0.08
-0.17
0.18
0.25
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
190
SDFFN
Your logo here
Cell Description
Logic Symbol
The SDFFN cell is a negative-edge triggered, static
D-type flip-flop with scan input (SI) and active-high
scan enable (SE).
D
SI
SE
CKN
Function
D
SI
SE
1
0
x
x
x
x
x
x
1
0
0
0
x
1
1
Q
QN
CKN Q[n+1] QN[n+1]
1
0
Q[n]
1
0
0
1
QN[n]
0
1
Cell Size
Drive Strength
Height (µm) Width (µm)
SDFFNXL
SDFFNX1
SDFFNX2
SDFFNX4
5.0
5.0
5.0
5.0
13.9
13.9
16.5
18.5
Functional Schematic
c
cn
c
SI
SE
c
cn
cn
QN
cn
c
D
Q
c
CKN
cn
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
191
SDFFN
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
XL
X1
X2
X4
SI
SE
D
CKN
0.0404
0.0479
0.0350
0.0336
0.0391
0.0444
0.0338
0.0362
0.0475
0.0532
0.0424
0.0501
0.0745
0.0764
0.0634
0.0758
Q
0.0372
0.0426
0.0671
0.1159
SI
SE
D
CKN
XL
X1
X2
X4
0.0022
0.0044
0.0025
0.0020
0.0020
0.0038
0.0016
0.0027
0.0021
0.0039
0.0019
0.0038
0.0020
0.0045
0.0029
0.0060
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
CKN
CKN
CKN
CKN
→
→
→
→
Q↑
Q↓
QN↑
QN↓
XL
X1
X2
X4
XL
X1
X2
X4
0.179
0.299
0.357
0.264
0.145
0.263
0.317
0.227
0.131
0.241
0.283
0.201
0.110
0.205
0.252
0.174
5.701
3.406
6.241
3.341
4.288
2.552
4.520
2.443
2.261
1.276
2.260
1.219
1.140
0.612
1.139
0.605
Timing Constraints at 25 oC, 1.8V, Typical Process
Interval (ns)
Pin
SI
SE
D
CKN
Requirement
setup↑ → CKN
setup↓ → CKN
hold↑ → CKN
hold↓ → CKN
setup↑ → CKN
setup↓ → CKN
hold↑ → CKN
hold↓ → CKN
setup↑ → CKN
setup↓ → CKN
hold↑ → CKN
hold↓ → CKN
minpwl
minpwh
XL
X1
X2
X4
0.11
0.30
0.03
-0.27
0.32
0.19
0.04
-0.01
0.08
0.18
0.05
-0.16
0.18
0.25
0.13
0.34
0.01
-0.29
0.35
0.34
0.02
-0.04
0.12
0.34
0.02
-0.29
0.18
0.25
0.16
0.35
-0.01
-0.30
0.36
0.30
0.01
-0.05
0.14
0.30
0.00
-0.25
0.18
0.25
0.19
0.41
-0.04
-0.34
0.44
0.24
-0.03
-0.06
0.13
0.24
-0.01
-0.20
0.18
0.25
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
192
SDFFNR
Your logo here
Cell Description
Logic Symbol
The SDFFNR cell is a negative-edge triggered,
static D-type flip-flop with scan input (SI),
active-high scan enable (SE), and asynchronous
active-low reset (RN).
D
SI
SE
CKN
Function
RN
D
SI
SE
1
1
1
1
1
0
1
0
x
x
x
x
x
x
x
1
0
x
0
0
x
1
1
x
Q
QN
CKN Q[n+1] QN[n+1]
x
1
0
Q[n]
1
0
0
RN
0
1
QN[n]
0
1
1
Cell Size
Drive Strength
SDFFNRXL
SDFFNRX1
SDFFNRX2
SDFFNRX4
Height (µm) Width (µm)
5.0
5.0
5.04
5.0
18.5
17.8
19.80
23.1
Functional Schematic
c
cn
c
c
SI
SE
cn
cn
Q
cn
c
D
QN
RN
c
CKN
cn
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
193
SDFFNR
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
SI
SE
D
CKN
RN
Q
XL
X1
X2
X4
0.0429
0.0494
0.0369
0.0374
0.0167
0.0448
0.0391
0.0445
0.0334
0.0366
0.0184
0.0516
0.0457
0.0542
0.0409
0.0464
0.0216
0.0811
0.0536
0.0590
0.0465
0.0546
0.0323
0.1348
SI
SE
D
CKN
RN
XL
X1
X2
X4
0.0019
0.0045
0.0026
0.0022
0.0021
0.0019
0.0039
0.0018
0.0027
0.0026
0.0021
0.0043
0.0018
0.0032
0.0033
0.0020
0.0045
0.0023
0.0037
0.0054
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
CKN
CKN
RN
CKN
CKN
RN
→
→
→
→
→
→
Q↑
Q↓
Q↓
QN↑
QN↓
QN↑
XL
X1
X2
X4
XL
X1
X2
X4
0.368
0.426
0.238
0.375
0.340
0.187
0.324
0.418
0.243
0.353
0.289
0.179
0.328
0.440
0.239
0.362
0.278
0.161
0.284
0.374
0.212
0.305
0.235
0.144
6.240
3.300
3.301
6.237
3.516
6.242
4.517
2.434
2.434
4.516
2.490
4.518
2.077
1.345
1.344
2.078
1.366
2.080
1.137
0.615
0.615
1.138
0.625
1.139
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
194
SDFFNR
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Timing Constraints at 25 oC, 1.8V, Typical Process
Interval (ns)
Pin
SI
SE
D
CKN
RN
Requirement
setup↑ → CKN
setup↓ → CKN
hold↑ → CKN
hold↓ → CKN
setup↑ → CKN
setup↓ → CKN
hold↑ → CKN
hold↓ → CKN
setup↑ → CKN
setup↓ → CKN
hold↑ → CKN
hold↓ → CKN
minpwl
minpwh
minpwl
recovery
XL
X1
X2
X4
0.12
0.32
0.04
-0.27
0.33
0.20
0.05
0.00
0.09
0.20
0.05
-0.16
0.18
0.25
0.50
0.04
0.13
0.34
0.01
-0.30
0.37
0.34
0.02
-0.05
0.12
0.34
0.01
-0.29
0.18
0.25
0.50
0.07
0.17
0.41
0.00
-0.35
0.41
0.41
0.02
-0.05
0.16
0.41
0.01
-0.34
0.18
0.25
0.50
0.09
0.17
0.38
-0.02
-0.31
0.39
0.29
-0.01
-0.06
0.15
0.29
-0.01
-0.23
0.18
0.25
0.50
0.08
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
195
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TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
196
SDFFNS
Your logo here
Cell Description
Logic Symbol
The SDFFNS cell is a negative-edge triggered, static
D-type flip-flop with scan input (SI), active-high scan
enable (SE), and asynchronous active-low set (SN).
SN
D
SI
SE
CKN
Function
SN
D
SI
SE
1
1
1
1
1
0
1
0
x
x
x
x
x
x
x
1
0
x
0
0
x
1
1
x
CKN Q[n+1] QN[n+1]
x
1
0
Q[n]
1
0
1
0
1
QN[n]
0
1
0
Q
QN
Cell Size
Drive Strength
SDFFNSXL
SDFFNSX1
SDFFNSX2
SDFFNSX4
Height (µm) Width (µm)
5.0
5.0
5.0
5.0
15.8
15.8
16.5
21.8
Functional Schematic
c
cn
c
c
SI
SE
cn
cn
Q
cn
c
D
QN
SN
c
CKN
cn
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
197
SDFFNS
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
SI
SE
D
CKN
SN
Q
XL
X1
X2
X4
0.0417
0.0476
0.0355
0.0351
0.0050
0.0424
0.0355
0.0401
0.0307
0.0339
0.0059
0.0501
0.0389
0.0436
0.0342
0.0368
0.0092
0.0772
0.0472
0.0518
0.0415
0.0480
0.0166
0.1334
SI
SE
D
CKN
SN
XL
X1
X2
X4
0.0019
0.0045
0.0025
0.0020
0.0047
0.0019
0.0039
0.0017
0.0026
0.0052
0.0019
0.0039
0.0016
0.0026
0.0069
0.0019
0.0042
0.0018
0.0034
0.0117
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
CKN
CKN
SN
CKN
CKN
SN
→
→
→
→
→
→
Q↑
Q↓
Q↑
QN↑
QN↓
QN↓
XL
X1
X2
X4
XL
X1
X2
X4
0.292
0.398
0.156
0.350
0.262
0.126
0.267
0.392
0.147
0.330
0.230
0.109
0.271
0.379
0.151
0.311
0.220
0.101
0.255
0.362
0.142
0.294
0.206
0.093
6.241
3.299
6.239
6.253
3.362
3.342
4.518
2.431
4.515
4.522
2.441
2.439
2.276
1.211
2.276
2.279
1.214
1.216
1.137
0.606
1.137
1.139
0.608
0.610
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
198
SDFFNS
Your logo here
Timing Constraints at 25 oC, 1.8V, Typical Process
Interval (ns)
Pin
SI
SE
D
CKN
SN
Requirement
setup↑ → CKN
setup↓ → CKN
hold↑ → CKN
hold↓ → CKN
setup↑ → CKN
setup↓ → CKN
hold↑ → CKN
hold↓ → CKN
setup↑ → CKN
setup↓ → CKN
hold↑ → CKN
hold↓ → CKN
minpwl
minpwh
minpwl
recovery
XL
X1
X2
X4
0.09
0.32
0.03
-0.28
0.33
0.19
0.04
0.00
0.06
0.20
0.05
-0.17
0.18
0.25
0.50
-0.08
0.11
0.34
0.01
-0.30
0.35
0.33
0.02
-0.04
0.10
0.34
0.02
-0.30
0.18
0.25
0.50
-0.05
0.11
0.35
0.02
-0.30
0.37
0.35
0.02
-0.04
0.10
0.35
0.02
-0.30
0.18
0.25
0.50
-0.05
0.12
0.36
0.00
-0.31
0.38
0.30
0.02
-0.05
0.12
0.30
0.01
-0.27
0.18
0.25
0.50
-0.04
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
199
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TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
200
SDFFNSR
Your logo here
Cell Description
Logic Symbol
The SDFFNSR cell is a negative-edge triggered,
static D-type flip-flop with scan input (SI), activehigh scan enable (SE), and asynchronous activelow reset (RN) and set (SN). Set (SN) dominates
reset (RN).
SN
D
SI
SE
CKN
Functions
RN SN
1
1
1
1
1
0
1
0
1
1
1
1
1
1
0
0
D
SI
1
0
x
x
x
x
x
x
x
x
x
1
0
x
x
x
Q
QN
SE CKN Q[n+1] QN[n+1]
0
0
x
1
1
x
x
x
x
x
x
1
0
Q[n]
1
0
0
1
1
0
1
QN[n]
0
1
1
0
0
RN
Cell Size
Drive Strength
SDFFNSRXL
SDFFNSRX1
SDFFNSRX2
SDFFNSRX4
Height (µm) Width (µm)
5.0
5.0
5.0
5.0
19.1
19.1
19.1
25.1
Functional Schematic
c
cn
c
c
SI
SE
cn
cn
Q
cn
c
D
QN
RN
SN
c
CKN
cn
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
201
SDFFNSR
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
SI
SE
D
CKN
SN
RN
Q
XL
X1
X2
X4
0.0441
0.0508
0.0384
0.0348
0.0051
0.0176
0.0450
0.0390
0.0454
0.0337
0.0346
0.0056
0.0196
0.0535
0.0443
0.0503
0.0388
0.0385
0.0092
0.0234
0.0828
0.0567
0.0627
0.0504
0.0542
0.0170
0.0402
0.1441
SI
SE
D
CKN
SN
RN
XL
X1
X2
X4
0.0019
0.0042
0.0021
0.0022
0.0061
0.0021
0.0018
0.0039
0.0015
0.0027
0.0066
0.0024
0.0018
0.0040
0.0016
0.0027
0.0088
0.0035
0.0018
0.0044
0.0023
0.0040
0.0148
0.0060
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
CKN
CKN
SN
SN
RN
CKN
CKN
SN
SN
RN
→
→
→
→
→
→
→
→
→
→
Q↑
Q↓
Q↑
Q↓
Q↓
QN↑
QN↓
QN↑
QN↓
QN↑
XL
X1
X2
X4
XL
X1
X2
X4
0.361
0.425
0.182
0.186
0.277
0.366
0.327
0.127
0.145
0.218
0.327
0.421
0.171
0.179
0.266
0.350
0.289
0.109
0.130
0.195
0.319
0.389
0.166
0.160
0.229
0.321
0.265
0.092
0.113
0.161
0.291
0.366
0.156
0.155
0.223
0.298
0.243
0.088
0.109
0.155
6.235
3.311
6.237
3.312
3.312
6.259
3.580
6.278
3.386
6.278
4.516
2.437
4.517
2.437
2.437
4.522
2.501
4.533
2.455
4.532
2.276
1.211
2.276
1.211
1.211
2.279
1.239
2.284
1.221
2.285
1.137
0.610
1.137
0.610
0.610
1.139
0.624
1.142
0.618
1.142
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
202
SDFFNSR
Your logo here
Timing Constraints at 25 oC, 1.8V, Typical Process
Interval (ns)
Pin
SI
SE
D
CKN
SN
RN
Requirement
setup↑
setup↓
hold↑
hold↓
setup↑
setup↓
hold↑
hold↓
setup↑
setup↓
hold↑
hold↓
→
→
→
→
→
→
→
→
→
→
→
→
CKN
CKN
CKN
CKN
CKN
CKN
CKN
CKN
CKN
CKN
CKN
CKN
minpwl
minpwh
minpwl
recovery
minpwl
recovery
XL
X1
X2
X4
0.16
0.33
0.01
-0.28
0.35
0.26
0.02
-0.03
0.12
0.26
0.02
-0.21
0.18
0.25
0.50
-0.06
0.50
0.08
0.19
0.37
-0.02
-0.31
0.38
0.38
-0.01
-0.08
0.17
0.38
-0.02
-0.31
0.18
0.25
0.50
-0.03
0.50
0.12
0.18
0.38
-0.02
-0.32
0.40
0.36
-0.01
-0.07
0.16
0.36
-0.01
-0.30
0.18
0.25
0.50
-0.03
0.50
0.10
0.19
0.38
-0.02
-0.31
0.40
0.27
-0.02
-0.05
0.15
0.27
0.00
-0.22
0.18
0.25
0.50
-0.04
0.50
0.09
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
203
SDFFR
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Cell Description
Logic Symbol
The SDFFR cell is a positive-edge triggered, static
D-type flip-flop with scan input (SI), active-high
scan enable (SE), and asynchronous active-low
reset (RN).
D
SI
SE
CK
Functions
RN
D
SI
SE
1
1
1
1
1
0
1
0
x
x
x
x
x
x
x
1
0
x
0
0
x
1
1
x
CK
x
Q
QN
Q[n+1] QN[n+1]
1
0
Q[n]
1
0
0
0
1
QN[n]
0
1
1
RN
Cell Size
Drive Strength
SDFFRXL
SDFFRX1
SDFFRX2
SDFFRX4
Height (µm) Width (µm)
5.0
5.0
5.04
5.0
18.5
18.5
19.80
23.1
Functional Schematic
c
cn
c
c
SI
SE
cn
cn
Q
cn
c
D
QN
RN
cn
CK
c
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
204
SDFFR
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AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
SI
SE
D
CK
RN
Q
XL
X1
X2
X4
0.0420
0.0484
0.0361
0.0436
0.0165
0.0282
0.0391
0.0442
0.0334
0.0420
0.0185
0.0343
0.0443
0.0525
0.0395
0.0481
0.0213
0.0817
0.0535
0.0590
0.0464
0.0498
0.0313
0.1210
SI
SE
D
CK
RN
XL
X1
X2
X4
0.0021
0.0047
0.0028
0.0022
0.0020
0.0022
0.0041
0.0020
0.0027
0.0025
0.0023
0.0045
0.0020
0.0032
0.0033
0.0022
0.0047
0.0025
0.0037
0.0054
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
CK
CK
RN
CK
CK
RN
→
→
→
→
→
→
Q↑
Q↓
Q↓
QN↑
QN↓
QN↑
XL
X1
X2
X4
XL
X1
X2
X4
0.412
0.291
0.238
0.240
0.384
0.187
0.382
0.315
0.243
0.250
0.347
0.179
0.388
0.307
0.238
0.228
0.340
0.161
0.335
0.272
0.211
0.203
0.283
0.143
6.239
3.300
3.301
6.237
3.517
6.241
4.516
2.434
2.434
4.516
2.490
4.519
2.077
1.344
1.345
2.078
1.471
2.079
1.137
0.615
0.615
1.138
0.625
1.138
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
205
SDFFR
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Timing Constraints at 25 oC, 1.8V, Typical Process
Interval (ns)
Pin
SI
SE
D
CK
RN
Requirement
setup↑ → CK
setup↓ → CK
hold↑ → CK
hold↓ → CK
setup↑ → CK
setup↓ → CK
hold↑ → CK
hold↓ → CK
setup↑ → CK
setup↓ → CK
hold↑ → CK
hold↓ → CK
minpwh
minpwl
minpwl
recovery
XL
X1
X2
X4
0.14
0.33
-0.12
-0.20
0.34
0.21
-0.11
-0.09
0.09
0.21
-0.08
-0.09
0.18
0.25
0.50
0.03
0.13
0.34
-0.11
-0.23
0.37
0.34
-0.09
-0.16
0.12
0.34
-0.09
-0.23
0.18
0.25
0.50
0.05
0.17
0.41
-0.13
-0.28
0.42
0.41
-0.12
-0.18
0.15
0.41
-0.11
-0.28
0.18
0.25
0.50
0.08
0.16
0.39
-0.12
-0.27
0.41
0.30
-0.12
-0.16
0.13
0.30
-0.10
-0.19
0.18
0.25
0.50
0.05
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
206
SDFFRHQ
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Cell Description
Logic Symbol
The SDFFRHQ cell is a high-speed, positive-edge
triggered, static D-type flip-flop with scan input (SI),
active-high scan enable (SE), and asynchronous
active-low reset (RN). The cell has a single output
(Q) and fast clock-to-out path.
D
SI
SE
CK
Q
Functions
RN
D
SI
SE
1
1
1
1
1
0
1
0
x
x
x
x
x
x
x
1
0
x
0
0
x
1
1
x
CK
Q[n+1]
x
1
0
Q[n]
1
0
0
RN
Cell Size
Drive Strength
SDFFRHQXL
SDFFRHQX1
SDFFRHQX2
SDFFRHQX4
Height (µm) Width (µm)
5.0
5.0
5.0
5.0
16.5
16.5
19.8
24.4
Functional Schematic
c
cn
c
c
SI
SE
cn
cn
Q
cn
c
D
RN
cn
CK
c
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
207
SDFFRHQ
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AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
SI
SE
D
CK
RN
Q
Pin
XL
X1
X2
X4
0.0434
0.0520
0.0369
0.0416
0.0212
0.0136
0.0523
0.0598
0.0465
0.0419
0.0253
0.0183
0.0756
0.0828
0.0673
0.0496
0.0351
0.0318
0.1129
0.1146
0.0975
0.0664
0.0543
0.0535
SI
SE
D
CK
RN
XL
X1
X2
X4
0.0021
0.0048
0.0027
0.0020
0.0023
0.0021
0.0041
0.0019
0.0029
0.0039
0.0021
0.0045
0.0022
0.0039
0.0053
0.0021
0.0052
0.0036
0.0060
0.0093
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
CK → Q↑
CK → Q↓
RN → Q↓
XL
X1
X2
X4
XL
X1
X2
X4
0.236
0.251
0.171
0.196
0.175
0.137
0.172
0.151
0.117
0.158
0.139
0.096
9.483
3.620
2.885
6.726
2.467
1.941
3.364
1.225
1.081
1.832
0.676
0.646
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
208
SDFFRHQ
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Timing Constraints at 25 oC, 1.8V, Typical Process
Interval (ns)
Pin
SI
SE
D
CK
RN
Requirement
setup↑
setup↓
hold↑
hold↓
setup↑
setup↓
hold↑
hold↓
setup↑
setup↓
hold↑
hold↓
→ CK
→ CK
→ CK
→ CK
→ CK
→ CK
→ CK
→ CK
→ CK
→ CK
→ CK
→ CK
minpwh
minpwl
minpwl
recovery
X1
X2
X4
X8
0.16
0.38
-0.11
-0.20
0.39
0.27
-0.10
-0.09
0.12
0.27
-0.07
-0.09
0.18
0.25
0.50
0.09
0.18
0.43
-0.12
-0.25
0.44
0.41
-0.10
-0.16
0.16
0.41
-0.09
-0.23
0.18
0.25
0.50
0.10
0.21
0.48
-0.13
-0.28
0.48
0.38
-0.12
-0.16
0.19
0.38
-0.11
-0.20
0.18
0.25
0.50
0.12
0.23
0.52
-0.14
-0.32
0.55
0.31
-0.14
-0.14
0.16
0.32
-0.08
-0.15
0.18
0.25
0.50
0.10
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
209
SDFFS
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Cell Description
Logic Symbol
The SDFFS cell is a positive-edge triggered, static
D-type flip-flop with scan input (SI), active-high scan
enable (SE), and asynchronous active-low set (SN).
SN
D
SI
SE
CK
Functions
SN
D
SI
SE
1
1
1
1
1
0
1
0
x
x
x
x
x
x
x
1
0
x
0
0
x
1
1
x
CK
x
Q[n+1] QN[n+1]
1
0
Q[n]
1
0
1
0
1
QN[n]
0
1
0
Q
QN
Cell Size
Drive Strength
SDFFSXL
SDFFSX1
SDFFSX2
SDFFSX4
Height (µm) Width (µm)
5.0
5.0
5.0
5.0
15.8
15.8
16.5
21.1
Functional Schematic
c
cn
c
c
SI
SE
cn
cn
Q
cn
c
D
QN
SN
cn
CK
c
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
210
SDFFS
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AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
SI
SE
D
CK
SN
Q
XL
X1
X2
X4
0.0405
0.0466
0.0339
0.0377
0.0050
0.0283
0.0354
0.0398
0.0298
0.0397
0.0060
0.0288
0.0390
0.0437
0.0340
0.0430
0.0102
0.0596
0.0458
0.0501
0.0396
0.0451
0.0169
0.1160
SI
SE
D
CK
SN
XL
X1
X2
X4
0.0021
0.0047
0.0027
0.0020
0.0050
0.0020
0.0042
0.0017
0.0028
0.0054
0.0020
0.0042
0.0017
0.0028
0.0073
0.0021
0.0044
0.0019
0.0035
0.0125
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
CK
CK
SN
CK
CK
SN
→
→
→
→
→
→
Q↑
Q↓
Q↑
QN↑
QN↓
QN↓
XL
X1
X2
X4
XL
X1
X2
X4
0.329
0.274
0.156
0.226
0.299
0.126
0.311
0.292
0.142
0.234
0.278
0.108
0.329
0.293
0.152
0.223
0.279
0.102
0.306
0.268
0.141
0.200
0.258
0.094
6.239
3.299
6.239
6.254
3.361
3.341
4.516
2.432
4.517
4.721
2.696
2.695
2.248
1.210
2.248
2.251
1.215
1.217
1.109
0.609
1.109
1.111
0.611
0.614
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
211
SDFFS
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Timing Constraints at 25 oC, 1.8V, Typical Process
Interval (ns)
Pin
SI
SE
D
CK
SN
Requirement
setup↑
setup↓
hold↑
hold↓
setup↑
setup↓
hold↑
hold↓
setup↑
setup↓
hold↑
hold↓
→ CK
→ CK
→ CK
→ CK
→ CK
→ CK
→ CK
→ CK
→ CK
→ CK
→ CK
→ CK
minpwh
minpwl
minpwl
recovery
XL
X1
X2
X4
0.12
0.33
-0.10
-0.23
0.35
0.22
-0.09
-0.11
0.09
0.22
-0.07
-0.12
0.18
0.25
0.50
-0.02
0.12
0.35
-0.09
-0.27
0.37
0.36
-0.08
-0.13
0.10
0.36
-0.08
-0.27
0.18
0.25
0.50
-0.01
0.12
0.38
-0.09
-0.27
0.39
0.38
-0.08
-0.13
0.10
0.38
-0.08
-0.28
0.18
0.25
0.50
-0.01
0.12
0.37
-0.10
-0.27
0.38
0.32
-0.09
-0.14
0.11
0.32
-0.08
-0.22
0.18
0.25
0.50
0.00
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
212
SDFFSHQ
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Cell Description
Logic Symbol
The SDFFSHQ cell is a high-speed, positive-edge
triggered, static D-type flip-flop with scan input (SI),
active-high scan enable (SE), and asynchronous
active-low set (SN). The cell has a single output (Q)
and fast clock-to-out path.
SN
D
SI
SE
CK
Functions
SN
D
SI
SE
1
1
1
1
1
0
1
0
x
x
x
x
x
x
x
1
0
x
0
0
x
1
1
x
CK
Q[n+1]
x
1
0
Q[n]
1
0
1
Q
Cell Size
Drive Strength
SDFFSHQXL
SDFFSHQX1
SDFFSHQX2
SDFFSHQX4
Height (µm) Width (µm)
5.0
5.0
5.0
5.0
15.8
15.8
18.5
21.1
Functional Schematic
c
cn
c
c
SI
SE
cn
cn
Q
cn
c
D
SN
cn
CK
c
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
213
SDFFSHQ
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
SI
SE
D
CK
SN
Q
Pin
XL
X1
X2
X4
0.0457
0.0527
0.0392
0.0387
0.0091
0.0152
0.0507
0.0559
0.0462
0.0394
0.0102
0.0177
0.0682
0.0739
0.0605
0.0467
0.0173
0.0261
0.1048
0.1061
0.0871
0.0649
0.0317
0.0513
SI
SE
D
CK
SN
XL
X1
X2
X4
0.0021
0.0048
0.0027
0.0021
0.0079
0.0023
0.0043
0.0018
0.0028
0.0085
0.0021
0.0044
0.0021
0.0036
0.0135
0.0022
0.0050
0.0030
0.0056
0.0215
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
CK → Q↑
CK → Q↓
SN → Q↑
XL
X1
X2
X4
XL
X1
X2
X4
0.231
0.268
0.071
0.193
0.173
0.081
0.174
0.151
0.082
0.155
0.136
0.087
6.272
4.293
3.443
4.523
2.772
2.424
2.250
1.382
1.251
1.125
0.690
0.665
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
214
SDFFSHQ
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Timing Constraints at 25 oC, 1.8V, Typical Process
Interval (ns)
Pin
SI
SE
D
CK
SN
Requirement
setup↑
setup↓
hold↑
hold↓
setup↑
setup↓
hold↑
hold↓
setup↑
setup↓
hold↑
hold↓
→ CK
→ CK
→ CK
→ CK
→ CK
→ CK
→ CK
→ CK
→ CK
→ CK
→ CK
→ CK
minpwh
minpwl
minpwl
recovery
X1
X2
X4
X8
0.14
0.34
-0.11
-0.23
0.35
0.21
-0.10
-0.12
0.10
0.22
-0.07
-0.12
0.18
0.25
0.50
-0.02
0.15
0.45
-0.10
-0.27
0.46
0.46
-0.09
-0.14
0.13
0.46
-0.08
-0.29
0.18
0.25
0.50
0.05
0.16
0.46
-0.11
-0.28
0.48
0.40
-0.10
-0.15
0.14
0.40
-0.09
-0.22
0.18
0.25
0.50
0.06
0.20
0.50
-0.13
-0.33
0.52
0.34
-0.12
-0.14
0.14
0.34
-0.09
-0.17
0.18
0.25
0.50
0.06
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
215
SDFFSR
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Cell Description
Logic Symbol
The SDFFSR cell is a positive-edge triggered, static
D-type flip-flop with scan input (SI), active-high scan
enable (SE), and asynchronous active-low reset
(RN) and set (SN). Set (SN) dominates reset (RN).
SN
D
SI
SE
CK
Functions
RN SN
1
1
1
1
1
0
1
0
1
1
1
1
1
1
0
0
D
SI
1
0
x
x
x
x
x
x
x
x
x
1
0
x
x
x
SE CK
0
0
x
1
1
x
x
x
x
x
x
Q[n+1]
QN[n+1]
1
0
Q[n]
1
0
0
1
1
0
1
QN[n]
0
1
1
0
0
Q
QN
RN
Cell Size
Drive Strength
SDFFSRXL
SDFFSRX1
SDFFSRX2
SDFFSRX4
Height (µm) Width (µm)
5.0
5.0
5.0
5.0
19.1
19.8
19.1
25.7
Functional Schematic
c
cn
c
c
SI
SE
cn
cn
Q
cn
c
D
QN
RN
SN
cn
CK
c
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
216
SDFFSR
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
SI
SE
D
CK
SN
RN
Q
XL
X1
X2
X4
0.0438
0.0504
0.0380
0.0382
0.0058
0.0173
0.0312
0.0376
0.0448
0.0331
0.0375
0.0062
0.0191
0.0382
0.0425
0.0495
0.0379
0.0377
0.0098
0.0229
0.0718
0.0557
0.0619
0.0495
0.0477
0.0177
0.0400
0.1354
SI
SE
D
CK
SN
RN
XL
X1
X2
X4
0.0020
0.0044
0.0023
0.0024
0.0060
0.0022
0.0019
0.0041
0.0017
0.0029
0.0064
0.0024
0.0019
0.0042
0.0018
0.0029
0.0087
0.0035
0.0020
0.0046
0.0025
0.0040
0.0148
0.0060
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
CK
CK
SN
SN
RN
CK
CK
SN
SN
RN
→
→
→
→
→
→
→
→
→
→
Q↑
Q↓
Q↑
Q↓
Q↓
QN↑
QN↓
QN↑
QN↓
QN↑
XL
X1
X2
X4
XL
X1
X2
X4
0.402
0.307
0.181
0.185
0.276
0.248
0.369
0.127
0.144
0.218
0.368
0.319
0.171
0.178
0.264
0.248
0.330
0.109
0.130
0.194
0.366
0.285
0.166
0.160
0.228
0.216
0.312
0.091
0.112
0.159
0.341
0.275
0.156
0.155
0.223
0.207
0.293
0.088
0.109
0.155
6.237
3.310
6.233
3.311
3.311
6.260
3.577
6.276
3.386
6.275
4.514
2.437
4.514
2.437
2.437
4.524
2.501
4.531
2.455
4.531
2.276
1.211
2.276
1.211
1.211
2.279
1.239
2.283
1.220
2.283
1.137
0.610
1.137
0.610
0.610
1.139
0.624
1.142
0.618
1.142
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
217
SDFFSR
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Timing Constraints at 25 oC, 1.8V, Typical Process
Interval (ns)
Pin
SI
SE
D
CK
SN
RN
Requirement
setup↑
setup↓
hold↑
hold↓
setup↑
setup↓
hold↑
hold↓
setup↑
setup↓
hold↑
hold↓
→ CK
→ CK
→ CK
→ CK
→ CK
→ CK
→ CK
→ CK
→ CK
→ CK
→ CK
→ CK
minpwh
minpwl
minpwl
recovery
minpwl
recovery
XL
X1
X2
X4
0.16
0.34
-0.12
-0.21
0.36
0.27
-0.11
-0.15
0.12
0.27
-0.09
-0.15
0.18
0.25
0.50
-0.01
0.50
0.06
0.18
0.37
-0.12
-0.25
0.38
0.38
-0.12
-0.17
0.16
0.38
-0.11
-0.25
0.18
0.25
0.50
0.01
0.50
0.11
0.17
0.38
-0.12
-0.25
0.40
0.37
-0.11
-0.17
0.15
0.36
-0.11
-0.23
0.18
0.25
0.50
0.01
0.50
0.09
0.17
0.39
-0.12
-0.26
0.41
0.29
-0.12
-0.15
0.13
0.29
-0.09
-0.16
0.18
0.25
0.50
0.02
0.50
0.07
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
218
SDFFSRHQ
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Cell Description
Logic Symbol
The SDFFSRHQ cell is a high-speed, positive-edge
triggered, static D-type flip-flop with scan input (SI),
active-high scan enable (SE), and asynchronous
active-low reset (RN) and set (SN), and set
dominating reset. The cell has a single output (Q)
and fast clock-to-out path.
SN
D
SI
SE
CK
Functions
RN
SN
D
SI
SE
1
1
1
1
1
0
1
0
1
1
1
1
1
1
0
0
1
0
x
x
x
x
x
x
x
x
x
1
0
x
x
x
0
0
x
1
1
x
x
x
CK
Q[n+1]
x
x
x
1
0
Q[n]
1
0
0
1
1
Q
RN
Cell Size
Drive Strength
SDFFSRHQXL
SDFFSRHQX1
SDFFSRHQX2
SDFFSRHQX4
Height (µm) Width (µm)
5.0
5.0
5.0
5.0
19.8
19.8
25.1
33.7
Functional Schematic
c
cn
c
c
SI
SE
cn
cn
Q
cn
c
D
RN
SN
cn
CK
c
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
219
SDFFSRHQ
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AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
SI
SE
D
CK
SN
RN
Q
XL
X1
X2
X4
0.0480
0.0537
0.0408
0.0429
0.0092
0.0240
0.0160
0.0534
0.0599
0.0475
0.0410
0.0103
0.0267
0.0192
0.0752
0.0888
0.0711
0.0524
0.0173
0.0418
0.0365
0.1225
0.1352
0.1124
0.0735
0.0310
0.0671
0.0653
SI
SE
D
CK
SN
RN
XL
X1
X2
X4
0.0020
0.0054
0.0027
0.0022
0.0105
0.0022
0.0020
0.0049
0.0018
0.0028
0.0112
0.0035
0.0020
0.0051
0.0026
0.0043
0.0166
0.0057
0.0021
0.0058
0.0043
0.0064
0.0272
0.0100
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
CK
CK
SN
SN
RN
→
→
→
→
→
Q↑
Q↓
Q↑
Q↓
Q↓
XL
X1
X2
X4
XL
X1
X2
X4
0.245
0.247
0.077
0.049
0.177
0.204
0.170
0.084
0.051
0.128
0.188
0.158
0.088
0.048
0.114
0.174
0.143
0.090
0.038
0.099
9.492
4.196
4.006
3.736
3.773
6.731
2.761
2.838
2.484
2.484
3.365
1.432
1.451
1.362
1.361
1.683
0.717
0.771
0.712
0.712
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
220
SDFFSRHQ
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Timing Constraints at 25 oC, 1.8V, Typical Process
Interval (ns)
Pin
SI
SE
D
CK
SN
RN
Requirement
setup↑
setup↓
hold↑
hold↓
setup↑
setup↓
hold↑
hold↓
setup↑
setup↓
hold↑
hold↓
→ CK
→ CK
→ CK
→ CK
→ CK
→ CK
→ CK
→ CK
→ CK
→ CK
→ CK
→ CK
minpwh
minpwl
minpwl
recovery
minpwl
recovery
X1
X2
X4
X8
0.18
0.42
-0.12
-0.22
0.45
0.29
-0.10
-0.09
0.13
0.30
-0.07
-0.09
0.18
0.25
0.50
0.05
0.50
0.11
0.19
0.43
-0.12
-0.24
0.45
0.38
-0.10
-0.16
0.17
0.39
-0.09
-0.21
0.18
0.25
0.50
0.06
0.50
0.12
0.22
0.48
-0.13
-0.28
0.50
0.36
-0.12
-0.16
0.18
0.36
-0.09
-0.17
0.18
0.25
0.50
0.08
0.50
0.12
0.27
0.58
-0.16
-0.37
0.61
0.33
-0.16
-0.14
0.17
0.33
-0.08
-0.15
0.18
0.25
0.50
0.08
0.50
0.12
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
221
SDFFTR
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Cell Description
Logic Symbol
The SDFFTR cell is a positive-edge triggered, static
D-type flip-flop with scan input (SI), active-high scan
enable (SE), and synchronous active-low reset
(RN). Scan enable (SE) dominates reset (RN).
D
SI
SE
CK
Functions
RN
D
SI
SE
x
x
0
1
1
x
x
x
x
0
1
x
0
1
x
x
x
x
1
1
0
0
0
x
CK
Q[n+1] QN[n+1]
0
1
0
0
1
Q[n]
Q
QN
RN
1
0
1
1
0
QN[n]
Cell Size
Drive Strength
Height (µm) Width (µm)
SDFFTRXL
SDFFTRX1
SDFFTRX2
SDFFTRX4
5.0
5.0
5.0
5.0
14.5
14.5
17.2
19.8
Functional Schematic
c
cn
c
SI
SE
c
cn
cn
QN
cn
D
RN
c
Q
cn
CK
c
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
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SDFFTR
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AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
SI
SE
D
CK
RN
Q
XL
X1
X2
X4
0.0418
0.0495
0.0353
0.0431
0.0392
0.0142
0.0398
0.0453
0.0344
0.0415
0.0378
0.0220
0.0487
0.0541
0.0427
0.0500
0.0469
0.0522
0.0753
0.0781
0.0620
0.0664
0.0673
0.0944
SI
SE
D
CK
RN
XL
X1
X2
X4
0.0022
0.0048
0.0024
0.0020
0.0027
0.0022
0.0041
0.0017
0.0028
0.0018
0.0021
0.0044
0.0019
0.0039
0.0020
0.0023
0.0052
0.0025
0.0064
0.0038
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
CK
CK
CK
CK
→
→
→
→
Q↑
Q↓
QN↑
QN↓
XL
X1
X2
X4
XL
X1
X2
X4
0.218
0.179
0.225
0.286
0.192
0.160
0.207
0.265
0.193
0.150
0.206
0.267
0.157
0.137
0.186
0.227
6.246
3.185
6.242
3.328
4.520
2.631
4.518
2.441
2.250
1.225
2.249
1.213
1.110
0.617
1.109
0.610
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
223
SDFFTR
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Timing Constraints at 25 oC, 1.8V, Typical Process
Interval (ns)
Pin
SI
SE
D
Requirement
setup↑
setup↓
hold↑
hold↓
setup↑
setup↓
hold↑
hold↓
setup↑
setup↓
hold↑
hold↓
CK
RN
setup↑
setup↓
hold↑
hold↓
→ CK
→ CK
→ CK
→ CK
→ CK
→ CK
→ CK
→ CK
→ CK
→ CK
→ CK
→ CK
minpwh
minpwl
→ CK
→ CK
→ CK
→ CK
XL
X1
X2
X4
0.14
0.38
-0.12
-0.27
0.39
0.27
-0.10
-0.15
0.12
0.24
-0.09
-0.14
0.18
0.25
0.12
0.29
-0.10
-0.16
0.12
0.40
-0.09
-0.29
0.41
0.41
-0.09
-0.17
0.14
0.40
-0.11
-0.28
0.18
0.25
0.15
0.45
-0.12
-0.33
0.15
0.39
-0.12
-0.27
0.39
0.35
-0.10
-0.18
0.16
0.34
-0.12
-0.21
0.18
0.25
0.17
0.38
-0.13
-0.24
0.17
0.48
-0.13
-0.35
0.48
0.29
-0.12
-0.16
0.13
0.27
-0.09
-0.16
0.18
0.25
0.14
0.31
-0.11
-0.20
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
224
SEDFF
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Cell Description
Logic Symbol
The SEDFF cell is a positive-edge triggered, static
D-type flip-flop with scan input (SI), active-high
scan enable (SE), and synchronous active-high
enable (E).
D
E
SI
SE
CK
Functions
D
E
SI
SE
x
x
x
0
1
x
x
x
0
1
1
x
1
0
x
x
x
x
1
1
0
0
0
x
CK
Q
QN
Q[n+1] QN[n+1]
1
0
Q[n]
0
1
Q[n]
0
1
QN[n]
1
0
QN[n]
Cell Size
Drive Strength
Height (µm) Width (µm)
SEDFFXL
SEDFFX1
SEDFFX2
SEDFFX4
5.0
5.0
5.0
5.0
17.8
17.8
19.8
23.1
Functional Schematic
c
cn
c
SI
SE
c
cn
cn
Q
cn
D
E
c
cn
CK
c
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
225
QN
SEDFF
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AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
SI
SE
D
CK
E
Q
XL
X1
X2
X4
0.0460
0.0546
0.0386
0.0621
0.0528
0.0026
0.0483
0.0566
0.0421
0.0676
0.0561
0.0061
0.0619
0.0701
0.0532
0.0849
0.0675
0.0249
0.0884
0.0981
0.0748
0.1243
0.0949
0.0498
SI
SE
D
CK
E
XL
X1
X2
X4
0.0020
0.0039
0.0019
0.0020
0.0047
0.0017
0.0038
0.0017
0.0029
0.0044
0.0021
0.0043
0.0021
0.0039
0.0048
0.0033
0.0050
0.0032
0.0066
0.0057
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
CK
CK
CK
CK
→
→
→
→
Q↑
Q↓
QN↑
QN↓
XL
X1
X2
X4
XL
X1
X2
X4
0.223
0.180
0.254
0.326
0.203
0.160
0.221
0.291
0.175
0.144
0.204
0.258
0.157
0.135
0.192
0.233
6.240
3.408
6.246
3.410
4.936
2.636
4.519
2.455
2.250
1.263
2.249
1.255
1.110
0.598
1.109
0.592
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
226
SEDFF
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Timing Constraints at 25 oC, 1.8V, Typical Process
Interval (ns)
Pin
SI
SE
D
Requirement
setup↑
setup↓
hold↑
hold↓
setup↑
setup↓
hold↑
hold↓
setup↑
setup↓
hold↑
hold↓
CK
E
setup↑
setup↓
hold↑
hold↓
→ CK
→ CK
→ CK
→ CK
→ CK
→ CK
→ CK
→ CK
→ CK
→ CK
→ CK
→ CK
minpwh
minpwl
→ CK
→ CK
→ CK
→ CK
XL
X1
X2
X4
0.16
0.33
-0.14
-0.30
0.44
0.47
-0.11
-0.22
0.16
0.42
-0.13
-0.30
0.18
0.25
0.46
0.35
-0.14
-0.20
0.15
0.47
-0.12
-0.46
0.59
0.62
-0.10
-0.21
0.16
0.56
-0.12
-0.42
0.18
0.25
0.60
0.50
-0.14
-0.20
0.16
0.39
-0.14
-0.37
0.50
0.52
-0.12
-0.22
0.18
0.47
-0.13
-0.34
0.18
0.25
0.51
0.41
-0.15
-0.21
0.14
0.32
-0.12
-0.29
0.42
0.45
-0.10
-0.21
0.16
0.41
-0.12
-0.29
0.18
0.25
0.45
0.34
-0.12
-0.20
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
227
SEDFFHQ
Your logo here
Cell Description
Logic Symbol
The SEDFFHQ cell is a positive-edge triggered,
static D-type flip-flop with scan input (SI), activehigh scan enable (SE), and synchronous activehigh enable (E). The cell has a single output (Q)
and fast clock-to-output path.
D
E
SI
SE
CK
Q
Functions
D
E
SI
SE
x
x
x
0
1
x
x
x
0
1
1
x
1
0
x
x
x
x
1
1
0
0
0
x
CK
Q[n+1]
Cell Size
1
0
Q[n]
0
1
Q[n]
Drive Strength
Height (µm) Width (µm)
SEDFFHQXL
SEDFFHQX1
SEDFFHQX2
SEDFFHQX4
5.0
5.0
5.0
5.0
20.5
20.5
22.4
25.1
Functional Schematic
c
cn
c
SI
SE
c
cn
cn
Q
cn
D
E
c
cn
CK
c
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
228
SEDFFHQ
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
SI
SE
D
CK
E
Q
Pin
XL
X1
X2
X4
0.0529
0.0742
0.0726
0.0581
0.0937
-0.0046
0.0641
0.0837
0.0830
0.0756
0.0984
-0.0054
0.0822
0.1010
0.0999
0.1019
0.1171
-0.0107
0.1202
0.1399
0.1385
0.1488
0.1510
-0.0158
SI
SE
D
CK
E
XL
X1
X2
X4
0.0021
0.0020
0.0026
0.0020
0.0020
0.0021
0.0020
0.0029
0.0034
0.0021
0.0021
0.0020
0.0029
0.0045
0.0021
0.0021
0.0020
0.0029
0.0064
0.0021
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
CK → Q↑
CK → Q↓
XL
X1
X2
X4
XL
X1
X2
X4
0.260
0.306
0.173
0.215
0.165
0.202
0.139
0.182
6.247
3.443
4.517
2.433
2.218
1.223
1.109
0.612
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
229
SEDFFHQ
Your logo here
Timing Constraints at 25 oC, 1.8V, Typical Process
Interval (ns)
Pin
SI
SE
D
Requirement
setup↑
setup↓
hold↑
hold↓
setup↑
setup↓
hold↑
hold↓
setup↑
setup↓
hold↑
hold↓
CK
E
setup↑
setup↓
hold↑
hold↓
→ CK
→ CK
→ CK
→ CK
→ CK
→ CK
→ CK
→ CK
→ CK
→ CK
→ CK
→ CK
minpwh
minpwl
→ CK
→ CK
→ CK
→ CK
XL
X1
X2
X4
0.10
0.18
-0.09
-0.17
0.27
0.24
-0.16
-0.13
0.30
0.30
-0.16
-0.27
0.18
0.25
0.36
0.31
-0.23
-0.12
0.13
0.18
-0.12
-0.17
0.30
0.26
-0.18
-0.16
0.28
0.26
-0.16
-0.22
0.18
0.25
0.35
0.27
-0.24
-0.12
0.16
0.19
-0.14
-0.18
0.32
0.27
-0.20
-0.19
0.31
0.27
-0.19
-0.23
0.18
0.25
0.38
0.28
-0.27
-0.16
0.20
0.21
-0.18
-0.20
0.36
0.29
-0.23
-0.23
0.35
0.30
-0.23
-0.25
0.18
0.25
0.42
0.30
-0.30
-0.27
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
230
SEDFFTR
Your logo here
Cell Description
Logic Symbol
The SEDFFTR cell is a positive-edge triggered,
static D-type flip-flop with scan input (SI), active-high
scan enable (SE), synchronous active-high enable
(E) and synchronous active low reset (RN). Scan
enable (SE) dominates reset (RN) and enable (E).
D
E
SI
SE
CK
Q
QN
Functions
RN
D
E
SI
SE
x
x
1
0
1
1
x
x
x
x
x
1
0
x
x
x
0
x
1
1
x
0
1
x
x
x
x
x
1
1
0
0
0
0
x
CK
RN
Q[n+1] QN[n+1]
0
1
Q[n]
0
1
0
Q[n]
1
0
QN[n]
1
0
1
QN[n]
Cell Size
Drive Strength
SEDFFTRXL
SEDFFTRX1
SEDFFTRX2
SEDFFTRX4
Functional Schematic
c
c
5.0
5.0
5.0
5.0
25.1
25.7
26.4
27.7
c
cn
SI
SE
Height (µm) Width (µm)
cn
cn
Q
cn
RN
c
D
E
cn
CK
c
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
231
QN
SEDFFTR
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
SI
SE
D
CK
E
RN
Q
XL
X1
X2
X4
0.0557
0.0801
0.0727
0.0624
0.0932
0.0510
0.0037
0.0692
0.0918
0.0915
0.0865
0.1116
0.0669
0.0017
0.0692
0.0918
0.0914
0.0866
0.1119
0.0669
0.0234
0.0692
0.0919
0.0918
0.0869
0.1107
0.0669
0.0733
SI
SE
D
CK
E
RN
XL
X1
X2
X4
0.0022
0.0039
0.0020
0.0019
0.0020
0.0026
0.0022
0.0039
0.0030
0.0035
0.0021
0.0026
0.0022
0.0039
0.0030
0.0035
0.0021
0.0026
0.0022
0.0039
0.0030
0.0035
0.0021
0.0026
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
CK
CK
CK
CK
→
→
→
→
Q↑
Q↓
QN↑
QN↓
XL
X1
X2
X4
XL
X1
X2
X4
0.316
0.342
0.203
0.217
0.197
0.227
0.161
0.150
0.217
0.234
0.169
0.171
0.257
0.253
0.186
0.212
6.253
3.478
6.260
3.611
4.516
2.435
4.519
2.466
2.281
1.261
2.284
1.288
1.109
0.605
1.113
0.633
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
232
SEDFFTR
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Timing Constraints at 25 oC, 1.8V, Typical Process
Interval (ns)
Pin
SI
SE
D
CK
E
RN
Requirement
setup↑ → CK
setup↓ → CK
hold↑ → CK
hold↓ → CK
setup↑ → CK
setup↓ → CK
hold↑ → CK
hold↓ → CK
setup↑ → CK
setup↓ → CK
hold↑ → CK
hold↓ → CK
minpwh
minpwl
setup↑ → CK
setup↓ → CK
hold↑ → CK
hold↓ → CK
setup↑ → CK
setup↓ → CK
hold↑ → CK
hold↓ → CK
XL
X1
X2
X4
0.27
0.20
-0.14
-0.19
0.34
0.37
-0.20
-0.17
0.37
0.31
-0.21
-0.29
0.18
0.25
0.43
0.33
-0.30
-0.10
0.26
0.20
-0.12
-0.18
0.31
0.23
-0.19
-0.20
0.38
0.38
-0.23
-0.23
0.35
0.27
-0.22
-0.23
0.18
0.25
0.43
0.31
-0.29
-0.12
0.29
0.22
-0.16
-0.19
0.31
0.23
-0.18
-0.20
0.38
0.37
-0.23
-0.23
0.35
0.27
-0.22
-0.23
0.18
0.25
0.42
0.31
-0.29
-0.14
0.29
0.22
-0.16
-0.19
0.27
0.23
-0.18
-0.20
0.34
0.34
-0.23
-0.23
0.31
0.27
-0.22
-0.23
0.18
0.25
0.39
0.30
-0.29
-0.25
0.25
0.22
-0.15
-0.19
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
233
TBUF
Your logo here
Cell Description
Logic Symbol
The TBUF cell provides the logical buffer of a single
input (A) with an active-high output enable (OE).
When the enable is high, the output (Y) is
represented by the logic equation:
A
Y
OE
Y = A
Functions
Cell Size
OE
A
Y
Drive Strength
0
1
1
x
0
1
Z
0
1
TBUFXL
TBUFX1
TBUFX2
TBUFX3
TBUFX4
TBUFX8
TBUFX12
TBUFX16
TBUFX20
Height (µm) Width (µm)
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
Functional Schematic
A
Y
OE
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
234
4.6
4.6
4.6
5.3
5.9
7.9
9.9
11.2
15.2
TBUF
Your logo here
AC Power
Power (µW/MHz)
Pin
A
OE
XL
X1
X2
X3
X4
X8
X12
X16
X20
0.0229
0.0161
0.0251
0.0168
0.0338
0.0224
0.0398
0.0278
0.0506
0.0350
0.0922
0.0690
0.1332
0.0970
0.1679
0.1281
0.2168
0.1596
Pin Capacitance
Capacitance (pF)
Pin
A
OE
Y
XL
X1
X2
X3
X4
X8
X12
X16
X20
0.0022
0.0039
0.0019
0.0022
0.0041
0.0024
0.0031
0.0040
0.0039
0.0043
0.0041
0.0036
0.0057
0.0045
0.0047
0.0115
0.0066
0.0093
0.0167
0.0095
0.0137
0.0201
0.0120
0.0179
0.0264
0.0151
0.0222
Delays at 25 oC, 1.8V, Typical Process
Intrinsic Delay (ns)
Description
A
A
OE
OE
→
→
→
→
Y↑
Y↓
Y↑
Y↓
XL
X1
X2
X3
X4
X8
X12
X16
X20
0.092
0.148
0.063
0.103
0.099
0.162
0.068
0.108
0.101
0.143
0.075
0.103
0.098
0.135
0.078
0.098
0.092
0.129
0.073
0.100
0.088
0.118
0.070
0.095
0.080
0.113
0.066
0.095
0.080
0.114
0.064
0.093
0.080
0.110
0.065
0.091
Kload (ns/pF)
Description
A
A
OE
OE
→
→
→
→
Y↑
Y↓
Y↑
Y↓
XL
X1
X2
X3
X4
X8
X12
X16
X20
6.248
4.376
6.242
4.365
4.527
2.532
4.522
2.522
2.342
1.282
2.340
1.276
1.549
0.811
1.548
0.806
1.142
0.626
1.142
0.623
0.571
0.330
0.571
0.330
0.371
0.226
0.370
0.225
0.278
0.169
0.278
0.169
0.229
0.131
0.229
0.130
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
235
TBUFI
Your logo here
Cell Description
Logic Symbol
The TBUFI cell provides the logical inversion of a
single input (A) with an active-high output enable
(OE). When the enable is high, the output (Y) is
represented by the logic equation:
A
Y
OE
Y = A
Cell Size
Drive Strength
Function
OE
A
Y
0
1
1
x
0
1
Z
1
0
TBUFIXL
TBUFIX1
TBUFIX2
TBUFIX3
TBUFIX4
TBUFIX8
TBUFIX12
TBUFIX16
TBUFIX20
Height (µm) Width (µm)
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
Functional Schematic
A
Y
OE
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
236
2.6
2.6
4.0
6.6
6.6
8.6
11.2
12.5
16.5
TBUFI
Your logo here
AC Power
Power (µW/MHz)
Pin
A
OE
XL
X1
X2
X3
X4
X8
X12
X16
X20
0.0215
0.0136
0.0217
0.0137
0.0410
0.0227
0.0484
0.0296
0.0594
0.0360
0.1079
0.0675
0.1576
0.1014
0.1978
0.1300
0.2582
0.1732
Pin Capacitance
Capacitance (pF)
Pin
A
OE
Y
XL
X1
X2
X3
X4
X8
X12
X16
X20
0.0046
0.0037
0.0031
0.0046
0.0037
0.0031
0.0092
0.0056
0.0037
0.0020
0.0035
0.0037
0.0026
0.0036
0.0043
0.0046
0.0049
0.0090
0.0066
0.0070
0.0137
0.0086
0.0086
0.0184
0.0105
0.0110
0.0226
Delays at 25 oC, 1.8V, Typical Process
Intrinsic Delay (ns)
Description
A
A
OE
OE
→
→
→
→
Y↑
Y↓
Y↑
Y↓
XL
X1
X2
X3
X4
X8
X12
X16
X20
0.062
0.029
0.060
0.019
0.062
0.030
0.060
0.019
0.055
0.026
0.059
0.015
0.179
0.176
0.079
0.101
0.170
0.165
0.078
0.097
0.154
0.155
0.067
0.096
0.149
0.153
0.067
0.096
0.142
0.149
0.065
0.094
0.143
0.146
0.066
0.092
Kload (ns/pF)
Description
A
A
OE
OE
→
→
→
→
Y↑
Y↓
Y↑
Y↓
XL
X1
X2
X3
X4
X8
X12
X16
X20
6.724
2.665
6.750
2.661
6.719
2.722
6.731
2.723
3.361
1.362
3.366
1.363
1.525
0.813
1.523
0.809
1.178
0.634
1.177
0.631
0.600
0.299
0.600
0.298
0.371
0.214
0.370
0.213
0.278
0.159
0.278
0.159
0.229
0.123
0.229
0.122
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
237
TIEHI
Your logo here
Cell Description
Logic Symbol
The TIEHI cell drives the output (Y) to a logic high.
The output is driven through diffusion and not tied
directly to the power rail to provide some ESD
protection. The output (Y) is represented by the logic
equation:
Y = 1
Y
Function
Cell Size
Y
Drive Strength
1
TIEHI
Height (µm) Width (µm)
5.0
Functional Schematic
Y
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
238
1.3
TIELO
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Cell Description
Logic Symbol
The TIELO cell drives the output (Y) to a logic low.
The output is driven through diffusion and not tied
directly to the power rail to provide some ESD
protection. The output (Y) is represented by the logic
equation:
Y
Y = 0
Function
Cell Size
Y
Drive Strength
0
TIELO
Height (µm) Width (µm)
5.0
Functional Schematic
Y
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
239
1.3
TLAT
Your logo here
Cell Description
Logic Symbol
The TLAT cell is an active-high D-type transparent
latch. When the enable (G) is high, data is transferred
to the outputs (Q, QN).
Functions
G
D
1
1
0
0
1
x
D
Q
G
QN
Q[n+1] QN[n+1]
0
1
Q[n]
1
0
QN[n]
Cell Size
Drive Strength
TLATXL
TLATX1
TLATX2
TLATX4
Height (µm) Width (µm)
5.0
5.0
5.0
5.0
Functional Schematic
g
gn
gn
D
QN
g
Q
gn
G
g
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
240
7.3
7.3
7.9
11.2
TLAT
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
D
G
Q
XL
X1
X2
X4
0.0050
0.0204
0.0311
0.0061
0.0223
0.0362
0.0100
0.0260
0.0642
0.0215
0.0414
0.1057
D
G
XL
X1
X2
X4
0.0033
0.0020
0.0041
0.0026
0.0060
0.0027
0.0136
0.0045
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
D
D
G
G
D
D
G
G
→
→
→
→
→
→
→
→
Q↑
Q↓
Q↑
Q↓
QN↑
QN↓
QN↑
QN↓
XL
X1
X2
X4
XL
X1
X2
X4
0.089
0.146
0.182
0.157
0.193
0.160
0.205
0.254
0.086
0.149
0.173
0.156
0.201
0.165
0.209
0.252
0.079
0.134
0.179
0.150
0.200
0.168
0.216
0.270
0.070
0.124
0.152
0.137
0.193
0.162
0.206
0.245
6.248
3.398
6.245
3.394
6.244
3.336
6.246
3.336
4.522
2.471
4.519
2.469
4.520
2.444
4.518
2.444
2.278
1.227
2.279
1.226
2.277
1.219
2.277
1.219
1.153
0.617
1.152
0.617
1.152
0.614
1.152
0.614
Timing Constraints at 25 oC, 1.8V, Typical Process
Interval (ns)
Pin
D
G
Requirement
setup↑ → G
setup↓ → G
hold↑ → G
hold↓ → G
minpwh
XL
X1
X2
X4
-0.02
0.09
0.03
-0.09
0.18
-0.01
0.10
0.02
-0.09
0.18
-0.02
0.08
0.04
-0.07
0.18
-0.02
0.08
0.04
-0.06
0.18
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
241
TLATN
Your logo here
Cell Description
Logic Symbol
The TLATN cell is an active-low D-type transparent
latch. When the enable (GN) is low, data is
transferred to the outputs (Q, QN).
GN
Functions
GN
D
0
0
1
0
1
x
Q
D
QN
Q[n+1] QN[n+1]
0
1
Q[n]
1
0
QN[n]
Cell Size
Drive Strength
TLATNXL
TLATNX1
TLATNX2
TLATNX4
Height (µm) Width (µm)
5.0
5.0
5.0
5.0
Functional Schematic
g
gn
gn
D
QN
g
Q
g
GN
gn
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
242
7.3
7.3
7.9
11.2
TLATN
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
D
GN
Q
XL
X1
X2
X4
0.0051
0.0232
0.0342
0.0063
0.0259
0.0408
0.0100
0.0316
0.0697
0.0216
0.0552
0.1133
D
GN
XL
X1
X2
X4
0.0034
0.0020
0.0040
0.0025
0.0061
0.0027
0.0136
0.0045
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
D
D
GN
GN
D
D
GN
GN
→
→
→
→
→
→
→
→
Q↑
Q↓
Q↑
Q↓
QN↑
QN↓
QN↑
QN↓
XL
X1
X2
X4
XL
X1
X2
X4
0.088
0.145
0.156
0.235
0.193
0.160
0.284
0.229
0.083
0.144
0.135
0.223
0.197
0.162
0.276
0.215
0.078
0.136
0.136
0.225
0.202
0.169
0.292
0.228
0.069
0.125
0.113
0.210
0.195
0.161
0.279
0.206
6.251
3.397
6.250
3.395
6.247
3.336
6.245
3.335
4.519
2.465
4.522
2.465
4.518
2.444
4.518
2.445
2.251
1.228
2.251
1.228
2.249
1.219
2.249
1.219
1.152
0.617
1.153
0.617
1.152
0.615
1.152
0.614
Timing Constraints at 25 oC, 1.8V, Typical Process
Interval (ns)
Pin
D
GN
Requirement
setup↑ → GN
setup↓ → GN
hold↑ → GN
hold↓ → GN
minpwl
XL
X1
X2
X4
0.05
0.06
-0.04
-0.05
0.18
0.05
0.07
-0.04
-0.05
0.18
0.05
0.05
-0.04
-0.03
0.18
0.05
0.04
-0.03
-0.03
0.18
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
243
TLATNR
Your logo here
Cell Description
Logic Symbol
The TLATNR cell is an active-low D-type transparent
latch with asynchronous active-low reset (RN).
When the enable (GN) is low, data is transferred to
the outputs (Q, QN).
D
Q
GN
QN
Function
RN
GN
D
1
1
1
0
0
0
1
x
0
1
x
x
Q[n+1] QN[n+1]
0
1
Q[n]
0
RN
1
0
QN[n]
1
Cell Size
Drive Strength
TLATNRXL
TLATNRX1
TLATNRX2
TLATNRX4
Height (µm) Width (µm)
5.0
5.0
5.0
5.0
8.6
8.6
9.2
11.9
Functional Schematic
g
r
gn
D
gn
g
Q
r
QN
g
GN
RN
gn
r
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
244
TLATNR
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
D
GN
RN
Q
XL
X1
X2
X4
0.0035
0.0259
0.0039
0.0373
0.0042
0.0275
0.0042
0.0455
0.0075
0.0351
0.0053
0.0745
0.0144
0.0585
0.0071
0.1233
D
GN
RN
XL
X1
X2
X4
0.0026
0.0020
0.0038
0.0031
0.0020
0.0040
0.0052
0.0024
0.0051
0.0098
0.0036
0.0068
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
D
D
GN
GN
RN
RN
D
D
GN
GN
RN
RN
→
→
→
→
→
→
→
→
→
→
→
→
Q↑
Q↓
Q↑
Q↓
Q↑
Q↓
QN↑
QN↓
QN↑
QN↓
QN↑
QN↓
XL
X1
X2
X4
XL
X1
X2
X4
0.129
0.214
0.200
0.309
0.126
0.139
0.265
0.208
0.361
0.280
0.193
0.206
0.124
0.211
0.197
0.309
0.120
0.160
0.266
0.210
0.365
0.284
0.214
0.207
0.107
0.190
0.170
0.283
0.102
0.232
0.259
0.202
0.352
0.265
0.303
0.196
0.099
0.175
0.153
0.271
0.092
0.370
0.247
0.199
0.343
0.253
0.458
0.192
6.272
3.545
6.273
3.544
6.272
3.431
6.248
3.353
6.248
3.354
6.247
3.354
4.532
2.524
4.530
2.524
4.532
2.511
4.521
2.452
4.521
2.453
4.519
2.452
2.255
1.249
2.256
1.249
2.255
1.306
2.249
1.220
2.249
1.220
2.248
1.220
1.113
0.627
1.114
0.627
1.113
0.721
1.110
0.615
1.110
0.615
1.110
0.615
Timing Constraints at 25 oC, 1.8V, Typical Process
Interval (ns)
Pin
D
GN
RN
Requirement
setup↑ → GN
setup↓ → GN
hold↑ → GN
hold↓ → GN
minpwl
minpwl
recovery
XL
X1
X2
X4
0.09
0.12
-0.09
-0.11
0.18
0.50
0.09
0.09
0.12
-0.08
-0.10
0.18
0.50
0.09
0.08
0.09
-0.06
-0.08
0.18
0.50
0.07
0.07
0.07
-0.05
-0.06
0.18
0.50
0.06
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
245
TLATNS
Your logo here
Cell Description
Logic Symbol
The TLATNS cell is an active-low D-type transparent
latch with asynchronous active-low set (SN). When
the enable (GN) is low, data is transferred to the
outputs (Q, QN).
SN
D
Function
Q
GN
SN
GN
D
1
1
1
0
0
0
1
x
0
1
x
x
QN
Q[n+1] QN[n+1]
0
1
Q[n]
1
1
0
QN[n]
0
Cell Size
Drive Strength
TLATNSXL
TLATNSX1
TLATNSX2
TLATNSX4
Height (µm) Width (µm)
5.0
5.0
5.0
5.0
10.6
10.6
11.2
13.9
Functional Schematic
g
sn
gn
D
gn
g
Q
sn
QN
g
GN
SN
gn
sn
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
246
TLATNS
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AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
D
GN
SN
Q
XL
X1
X2
X4
0.0040
0.0247
0.0142
0.0468
0.0049
0.0264
0.0146
0.0538
0.0083
0.0310
0.0158
0.0854
0.0152
0.0449
0.0220
0.1365
D
GN
SN
XL
X1
X2
X4
0.0026
0.0021
0.0019
0.0031
0.0026
0.0019
0.0049
0.0027
0.0025
0.0091
0.0039
0.0037
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
D
D
GN
GN
SN
SN
D
D
GN
GN
SN
SN
→
→
→
→
→
→
→
→
→
→
→
→
Q↑
Q↓
Q↑
Q↓
Q↑
Q↓
QN↑
QN↓
QN↑
QN↓
QN↑
QN↓
XL
X1
X2
X4
XL
X1
X2
X4
0.134
0.289
0.218
0.378
0.193
0.322
0.361
0.229
0.450
0.314
0.393
0.287
0.125
0.283
0.185
0.353
0.205
0.315
0.345
0.233
0.417
0.295
0.377
0.312
0.108
0.251
0.171
0.330
0.233
0.277
0.325
0.210
0.405
0.274
0.351
0.338
0.102
0.235
0.151
0.300
0.311
0.259
0.309
0.201
0.374
0.251
0.333
0.422
6.279
3.632
6.276
3.633
6.247
3.633
6.242
3.155
6.244
3.154
6.244
3.150
4.533
2.716
4.536
2.715
4.522
2.716
4.520
2.464
4.521
2.463
4.523
2.461
2.255
1.289
2.256
1.289
2.256
1.290
2.249
1.223
2.249
1.223
2.250
1.223
1.113
0.646
1.114
0.646
1.119
0.646
1.110
0.615
1.109
0.615
1.109
0.616
Timing Constraints at 25 oC, 1.8V, Typical Process
Interval (ns)
Pin
D
GN
SN
Requirement
setup↑ → GN
setup↓ → GN
hold↑ → GN
hold↓ → GN
minpwl
minpwl
recovery
XL
X1
X2
X4
0.11
0.20
-0.10
-0.16
0.18
0.50
0.23
0.10
0.19
-0.09
-0.15
0.18
0.50
0.22
0.09
0.16
-0.07
-0.12
0.18
0.50
0.18
0.08
0.14
-0.07
-0.12
0.18
0.50
0.16
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
247
TLATNSR
Your logo here
Cell Description
Logic Symbol
The TLATNSR cell is an active-low D-type
transparent latch with asynchronous active-low set
(SN) and reset (RN), and set dominating reset. When
the enable (GN) is low, data is transferred to the
outputs (Q, QN).
SN
D
Q
GN
Functions
RN
SN
GN
D
1
1
1
0
1
0
1
1
1
1
0
0
0
0
1
x
x
x
0
1
x
x
x
x
QN
Q[n+1] QN[n+1]
0
1
Q[n]
0
1
1
1
0
QN[n]
1
0
0
RN
Cell Size
Drive Strength
Height (µm) Width (µm)
TLATNSRXL
TLATNSRX1
TLATNSRX2
TLATNSRX4
5.0
5.0
5.0
5.0
11.2
11.2
11.9
16.5
Functional Schematic
g
sn
gn
r
D
gn
g
r
Q
sn
QN
RN
r
SN
sn
g
GN
gn
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
248
TLATNSR
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
D
GN
SN
RN
Q
XL
X1
X2
X4
0.0039
0.0254
0.0161
0.0048
0.0504
0.0048
0.0266
0.0177
0.0056
0.0596
0.0081
0.0341
0.0236
0.0096
0.0967
0.0164
0.0611
0.0445
0.0186
0.1593
D
GN
SN
RN
XL
X1
X2
X4
0.0028
0.0020
0.0020
0.0038
0.0033
0.0026
0.0025
0.0042
0.0051
0.0028
0.0039
0.0060
0.0109
0.0041
0.0066
0.0108
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
D
D
GN
GN
SN
SN
RN
RN
D
D
GN
GN
SN
SN
RN
RN
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
Q↑
Q↓
Q↑
Q↓
Q↑
Q↓
Q↑
Q↓
QN↑
QN↓
QN↑
QN↓
QN↑
QN↓
QN↑
QN↓
XL
X1
X2
X4
XL
X1
X2
X4
0.172
0.329
0.243
0.400
0.222
0.360
0.168
0.242
0.400
0.272
0.473
0.345
0.432
0.321
0.312
0.269
0.161
0.323
0.210
0.380
0.205
0.352
0.158
0.235
0.387
0.275
0.445
0.325
0.416
0.315
0.297
0.271
0.154
0.293
0.203
0.361
0.180
0.319
0.150
0.211
0.368
0.256
0.437
0.306
0.394
0.280
0.281
0.253
0.139
0.272
0.180
0.341
0.173
0.298
0.135
0.192
0.346
0.241
0.416
0.284
0.372
0.273
0.261
0.238
6.310
4.023
6.312
4.027
6.259
4.006
6.314
3.901
6.246
3.375
6.246
3.377
6.248
3.367
6.244
3.376
4.548
2.801
4.546
2.802
4.527
2.794
4.548
2.763
4.520
2.466
4.521
2.466
4.520
2.463
4.520
2.467
2.262
1.339
2.262
1.338
2.253
1.335
2.261
1.318
2.249
1.222
2.249
1.222
2.249
1.221
2.250
1.222
1.116
0.667
1.116
0.668
1.111
0.666
1.115
0.659
1.110
0.616
1.110
0.615
1.110
0.615
1.110
0.615
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
249
TLATNSR
Your logo here
Timing Constraints at 25 oC, 1.8V, Typical Process
Interval (ns)
Pin
D
GN
SN
RN
Requirement
setup↑ → GN
setup↓ → GN
hold↑ → GN
hold↓ → GN
minpwl
minpwl
recovery
minpwl
recovery
XL
X1
X2
X4
0.15
0.25
-0.13
-0.20
0.18
0.50
0.30
0.50
0.14
0.14
0.23
-0.12
-0.20
0.18
0.50
0.27
0.50
0.14
0.12
0.20
-0.11
-0.17
0.18
0.50
0.21
0.50
0.12
0.12
0.16
-0.10
-0.14
0.18
0.50
0.20
0.50
0.11
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
250
TLATR
Your logo here
Cell Description
Logic Symbol
The TLATR cell is an active-high D-type transparent
latch with asynchronous active-low reset (RN).
When the enable (G) is high, data is transferred to
the outputs (Q, QN).
D
Q
G
QN
Function
RN
G
D
1
1
1
0
1
1
0
x
0
1
x
x
Q[n+1] QN[n+1]
0
1
Q[n]
0
RN
1
0
QN[n]
1
Cell Size
Drive Strength
TLATRXL
TLATRX1
TLATRX2
TLATRX4
Height (µm) Width (µm)
5.0
5.0
5.0
5.0
8.6
8.6
9.2
11.9
Functional Schematic
g
r
gn
D
gn
g
Q
r
QN
gn
G
RN
g
r
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
251
TLATR
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
D
G
RN
Q
XL
X1
X2
X4
0.0033
0.0250
0.0040
0.0289
0.0039
0.0255
0.0040
0.0377
0.0074
0.0292
0.0052
0.0693
0.0145
0.0505
0.0073
0.1238
D
G
RN
XL
X1
X2
X4
0.0025
0.0020
0.0038
0.0031
0.0021
0.0039
0.0052
0.0024
0.0051
0.0099
0.0038
0.0069
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
D
D
G
G
RN
RN
D
D
G
G
RN
RN
→
→
→
→
→
→
→
→
→
→
→
→
Q↑
Q↓
Q↑
Q↓
Q↑
Q↓
QN↑
QN↓
QN↑
QN↓
QN↑
QN↓
XL
X1
X2
X4
XL
X1
X2
X4
0.131
0.215
0.229
0.220
0.127
0.141
0.267
0.210
0.273
0.310
0.194
0.207
0.125
0.212
0.221
0.218
0.121
0.160
0.267
0.211
0.274
0.309
0.215
0.207
0.108
0.190
0.215
0.201
0.102
0.232
0.259
0.203
0.271
0.310
0.304
0.197
0.101
0.174
0.210
0.184
0.094
0.370
0.246
0.201
0.257
0.310
0.457
0.194
6.268
3.552
6.269
3.550
6.270
3.434
6.245
3.353
6.247
3.356
6.246
3.354
4.531
2.527
4.531
2.526
4.530
2.513
4.520
2.451
4.522
2.452
4.521
2.452
2.255
1.249
2.254
1.249
2.255
1.307
2.248
1.220
2.248
1.220
2.249
1.220
1.113
0.627
1.113
0.627
1.113
0.721
1.110
0.615
1.110
0.615
1.109
0.615
Timing Constraints at 25 oC, 1.8V, Typical Process
Interval (ns)
Pin
D
G
RN
Requirement
setup↑ → G
setup↓ → G
hold↑ → G
hold↓ → G
minpwh
minpwl
recovery
XL
X1
X2
X4
0.03
0.16
0.00
-0.16
0.18
0.50
0.02
0.03
0.16
0.00
-0.15
0.18
0.50
0.02
0.00
0.14
0.02
-0.13
0.18
0.50
-0.02
-0.01
0.12
0.03
-0.12
0.18
0.50
-0.02
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
252
TLATS
Your logo here
Cell Description
Logic Symbol
The TLATS cell is an active-high D-type transparent
latch with asynchronous active-low set (SN). When
the enable (G) is high, data is transferred to the
outputs (Q, QN).
SN
Function
SN
G
D
1
1
1
0
1
1
0
x
0
1
x
x
D
Q
G
QN
Q[n+1] QN[n+1]
0
1
Q[n]
1
1
0
QN[n]
0
Cell Size
Drive Strength
TLATSXL
TLATSX1
TLATSX2
TLATSX4
Height (µm) Width (µm)
5.0
5.0
5.0
5.0
10.6
10.6
11.2
13.9
Functional Schematic
g
sn
gn
D
gn
g
Q
sn
QN
gn
G
SN
g
sn
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
253
TLATS
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
D
G
SN
Q
XL
X1
X2
X4
0.0040
0.0257
0.0143
0.0386
0.0049
0.0268
0.0146
0.0427
0.0084
0.0292
0.0158
0.0759
0.0152
0.0374
0.0221
0.1316
D
G
SN
XL
X1
X2
X4
0.0026
0.0021
0.0020
0.0031
0.0027
0.0019
0.0050
0.0027
0.0025
0.0091
0.0040
0.0037
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
D
D
G
G
SN
SN
D
D
G
G
SN
SN
→
→
→
→
→
→
→
→
→
→
→
→
Q↑
Q↓
Q↑
Q↓
Q↑
Q↓
QN↑
QN↓
QN↑
QN↓
QN↑
QN↓
XL
X1
X2
X4
XL
X1
X2
X4
0.134
0.287
0.246
0.266
0.192
0.320
0.359
0.229
0.339
0.343
0.392
0.287
0.126
0.282
0.236
0.257
0.203
0.314
0.343
0.234
0.319
0.346
0.375
0.311
0.110
0.250
0.222
0.237
0.233
0.276
0.325
0.212
0.312
0.325
0.352
0.339
0.104
0.233
0.202
0.219
0.311
0.257
0.307
0.203
0.294
0.301
0.332
0.422
6.279
3.627
6.278
3.628
6.244
3.629
6.244
3.156
6.246
3.155
6.245
3.151
4.534
2.798
4.532
2.798
4.523
2.798
4.520
2.464
4.520
2.464
4.520
2.464
2.255
1.290
2.254
1.289
2.256
1.290
2.250
1.223
2.250
1.223
2.250
1.224
1.113
0.646
1.113
0.646
1.119
0.646
1.110
0.615
1.110
0.615
1.110
0.616
Timing Constraints at 25 oC, 1.8V, Typical Process
Interval (ns)
Pin
D
G
SN
Requirement
setup↑ → G
setup↓ → G
hold↑ → G
hold↓ → G
minpwh
minpwl
recovery
XL
X1
X2
X4
0.01
0.23
0.00
-0.22
0.18
0.50
0.27
0.02
0.22
-0.01
-0.21
0.18
0.50
0.26
-0.01
0.20
0.02
-0.18
0.18
0.50
0.22
-0.01
0.18
0.02
-0.16
0.18
0.50
0.20
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
254
TLATSR
Your logo here
Cell Description
Logic Symbol
The TLATSR cell is an active-high D-type
transparent latch with asynchronous active-low set
(SN) and reset (RN), and set dominating reset. When
the enable (G) is high, data is transferred to the
outputs (Q, QN).
D
Q
Functions
G
QN
RN
SN
G
D
1
1
1
0
1
0
1
1
1
1
0
0
1
1
0
x
x
x
0
1
x
x
x
x
SN
Q[n+1] QN[n+1]
0
1
Q[n]
0
1
1
1
0
QN[n]
1
0
0
RN
Cell Size
Drive Strength
Height (µm) Width (µm)
TLATSRXL
TLATSRX1
TLATSRX2
TLATSRX4
5.0
5.0
5.0
5.0
11.2
11.2
11.9
16.5
Functional Schematic
g
sn
gn
r
D
gn
g
r
Q
sn
QN
RN
r
SN
sn
gn
G
g
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
255
TLATSR
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
D
G
SN
RN
Q
XL
X1
X2
X4
0.0039
0.0278
0.0161
0.0047
0.0426
0.0048
0.0278
0.0178
0.0056
0.0510
0.0081
0.0296
0.0239
0.0095
0.0904
0.0164
0.0520
0.0447
0.0185
0.1524
D
G
SN
RN
XL
X1
X2
X4
0.0028
0.0020
0.0020
0.0038
0.0033
0.0025
0.0025
0.0042
0.0051
0.0028
0.0039
0.0060
0.0109
0.0041
0.0067
0.0109
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
D
D
G
G
SN
SN
RN
RN
D
D
G
G
SN
SN
RN
RN
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
Q↑
Q↓
Q↑
Q↓
Q↑
Q↓
Q↑
Q↓
QN↑
QN↓
QN↑
QN↓
QN↑
QN↓
QN↑
QN↓
XL
X1
X2
X4
XL
X1
X2
X4
0.173
0.330
0.273
0.321
0.222
0.362
0.169
0.243
0.402
0.273
0.394
0.375
0.433
0.322
0.313
0.269
0.164
0.326
0.258
0.313
0.206
0.355
0.160
0.238
0.389
0.276
0.377
0.372
0.418
0.316
0.299
0.273
0.155
0.293
0.251
0.281
0.180
0.318
0.151
0.211
0.370
0.259
0.360
0.357
0.396
0.282
0.283
0.256
0.140
0.271
0.228
0.260
0.172
0.296
0.137
0.192
0.345
0.242
0.334
0.331
0.371
0.272
0.261
0.239
6.311
4.029
6.312
4.030
6.260
4.012
6.311
3.906
6.242
3.375
6.247
3.377
6.245
3.367
6.243
3.376
4.548
2.808
4.546
2.808
4.529
2.801
4.547
2.765
4.519
2.466
4.520
2.467
4.521
2.463
4.521
2.467
2.262
1.338
2.261
1.339
2.253
1.335
2.263
1.319
2.249
1.222
2.250
1.222
2.250
1.222
2.250
1.223
1.116
0.667
1.115
0.668
1.112
0.666
1.116
0.659
1.110
0.615
1.110
0.615
1.110
0.615
1.110
0.615
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
256
TLATSR
Your logo here
Timing Constraints at 25 oC, 1.8V, Typical Process
Interval (ns)
Pin
D
G
SN
RN
Requirement
setup↑ → G
setup↓ → G
hold↑ → G
hold↓ → G
minpwh
minpwl
recovery
minpwl
recovery
XL
X1
X2
X4
0.06
0.27
-0.03
-0.26
0.18
0.50
0.32
0.50
0.05
0.08
0.27
-0.05
-0.25
0.18
0.50
0.30
0.50
0.06
0.05
0.24
-0.02
-0.22
0.18
0.50
0.26
0.50
0.03
0.02
0.21
0.00
-0.20
0.18
0.50
0.24
0.50
0.01
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
257
TTLAT
Your logo here
Cell Description
Logic Symbol
The TTLAT cell is an active-high D-type transparent
latch with active-high output enable (OE). When the
enable (G) is high and the output enable (OE) is high,
data is transferred to the output (Q).
Q
D
G
Function
OE
G
D
Q[n+1]
0
1
1
1
x
1
1
0
x
0
1
x
Z
0
1
Q[n]
OE
Cell Size
Drive Strength
TTLATXL
TTLATX1
TTLATX2
TTLATX4
Height (µm) Width (µm)
5.0
5.0
5.0
5.0
Functional Schematic
g
gn
gn
D
g
Q
OE
gn
G
g
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
258
8.6
8.6
12.5
15.2
TTLAT
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
D
G
OE
Q
XL
X1
X2
X4
0.0049
0.0238
0.0340
0.0261
0.0099
0.0245
0.0571
0.0571
0.0186
0.0372
0.1055
0.1060
0.0187
0.0525
0.1668
0.1575
D
G
OE
Q
XL
X1
X2
X4
0.0034
0.0020
0.0025
0.0020
0.0061
0.0026
0.0032
0.0043
0.0113
0.0041
0.0055
0.0047
0.0113
0.0067
0.0097
0.0089
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
D
D
G
G
OE
OE
→
→
→
→
→
→
Q↑
Q↓
Q↑
Q↓
Q↑
Q↓
XL
X1
X2
X4
XL
X1
X2
X4
0.118
0.175
0.216
0.191
0.028
0.016
0.101
0.147
0.198
0.163
0.023
0.016
0.103
0.146
0.198
0.162
0.017
0.012
0.113
0.179
0.180
0.185
0.021
0.014
8.134
5.085
8.139
5.081
8.065
4.994
2.678
1.629
2.679
1.627
2.637
1.586
1.394
0.808
1.394
0.807
1.372
0.786
0.718
0.460
0.719
0.460
0.708
0.445
Timing Constraints at 25 oC, 1.8V, Typical Process
Interval (ns)
Pin
D
G
Requirement
setup↑ → G
setup↓ → G
hold↑ → G
hold↓ → G
minpwh
XL
X1
X2
X4
-0.02
0.10
0.04
-0.08
0.18
-0.02
0.08
0.04
-0.06
0.18
-0.03
0.08
0.05
-0.06
0.18
0.01
0.12
0.01
-0.09
0.18
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
259
XNOR2
Your logo here
Cell Description
Logic Symbol
The XNOR2 cell provides a logical EXCLUSIVE
NOR of two inputs (A, B). The output (Y) is
represented by the logic equation:
A
Y
B
Y = ( A • B) + ( A • B)
Cell Size
Functions
A
0
0
1
1
B
0
1
0
1
Y
Drive Strength
1
0
0
1
XNOR2XL
XNOR2X1
XNOR2X2
XNOR2X4
Height (µm) Width (µm)
5.0
5.0
5.0
5.0
Functional Schematic
A
Y
B
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
260
5.3
5.3
7.3
11.2
XNOR2
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
A
B
XL
X1
X2
X4
0.0349
0.0357
0.0378
0.0512
0.0641
0.0995
0.1150
0.1814
A
B
XL
X1
X2
X4
0.0058
0.0021
0.0054
0.0064
0.0085
0.0141
0.0152
0.0266
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
A
A
B
B
→
→
→
→
Y↑
Y↓
Y↑
Y↓
XL
X1
X2
X4
XL
X1
X2
X4
0.131
0.124
0.183
0.192
0.126
0.111
0.124
0.139
0.131
0.101
0.107
0.123
0.118
0.103
0.105
0.122
6.246
3.500
6.252
3.493
4.522
2.466
4.520
2.474
2.249
1.221
2.249
1.226
1.214
0.576
1.214
0.578
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
261
XOR2
Your logo here
Cell Description
Logic Symbol
The XOR2 cell provides a logical EXCLUSIVE OR
of two inputs (A, B). The output (Y) is represented
by the logic equation:
A
Y
B
Y = ( A • B) + ( A • B)
Cell Size
Functions
A
0
0
1
1
B
0
1
0
1
Y
Drive Strength
0
1
1
0
XOR2XL
XOR2X1
XOR2X2
XOR2X4
Height (µm) Width (µm)
5.0
5.0
5.0
5.0
Functional Schematic
A
Y
B
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
262
5.3
5.3
6.6
11.2
XOR2
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
A
B
XL
X1
X2
X4
0.0345
0.0344
0.0355
0.0487
0.0612
0.0987
0.1054
0.1681
A
B
XL
X1
X2
X4
0.0058
0.0022
0.0054
0.0064
0.0084
0.0141
0.0162
0.0266
Delays at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Intrinsic Delay (ns)
Description
A
A
B
B
→
→
→
→
Y↑
Y↓
Y↑
Y↓
XL
X1
X2
X4
XL
X1
X2
X4
0.130
0.125
0.177
0.183
0.117
0.114
0.121
0.140
0.122
0.113
0.106
0.127
0.105
0.107
0.101
0.124
6.251
3.255
6.248
3.256
4.516
2.474
4.518
2.474
2.248
1.226
2.250
1.226
1.213
0.578
1.214
0.578
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
263
Synthesis Optimized Arithmetics
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
264
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
265
AFHCIN
Your logo here
Cell Description
Logic Symbol
The AFHCIN cell is a full adder that provides the
arithmetic sum (S) and carry-out (CO) of two
operands (A, B) with active-low carry-in (CIN). The
outputs (S, CO) are represented by the logic
equations:
A
S
B
CO
CIN
S = A ⊕ B ⊕ CIN
CO = ( A • B ) + ( A • CIN ) + ( B • CIN )
Cell Size
Functions
A
B
CIN
S
CO
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
0
0
1
0
1
1
0
0
0
1
0
1
0
1
1
Drive Strength
AFHCINX2
AFHCINX4
Height (µm) Width (µm)
5.04
5.04
Functional Schematic
A
B
CIN
S
CO
TSMC 0.18µm Process SAGE-X Standard Cell Library Databook
264
16.50
18.48
AFHCIN
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
A
B
CIN
X2
X4
0.1714
0.1796
0.1234
0.1933
0.1990
0.1799
A
B
CIN
X2
X4
0.0072
0.0176
0.0135
0.0072
0.0155
0.0265
Delays at 25 oC, 3.3V, Typical Process
Intrinsic Delay (ns)
Description
A
A
B
B
CIN
CIN
A
A
B
B
CIN
CIN
→
→
→
→
→
→
→
→
→
→
→
→
S↑
S↓
S↑
S↓
S↑
S↓
CO↑
CO↓
CO↑
CO↓
CO↑
CO↓
Kload (ns/pF)
X2
X4
X2
X4
0.245
0.292
0.220
0.220
0.140
0.156
0.174
0.214
0.132
0.181
0.052
0.042
0.261
0.314
0.236
0.241
0.124
0.157
0.200
0.250
0.153
0.214
0.046
0.041
2.876
1.406
2.877
1.405
2.876
1.410
3.030
1.902
3.009
1.882
2.785
1.662
2.261
1.281
2.262
1.281
2.261
1.282
3.021
1.876
3.014
1.868
1.400
0.837
TSMC 0.18µm Process SAGE-X Standard Cell Library Databook
265
AFHCON
Your logo here
Cell Description
Logic Symbol
The AFHCON cell is a full adder that provides the
arithmetic sum (S) and active-low carry-out (CON)
of two operands (A, B) with carry-in (CI). The outputs
(S, CON) are represented by the logic equations:
S = A ⊕ B ⊕ CI
A
S
B
CON
CI
CON = ( A • B ) + ( A • CI ) + ( B • CI )
Functions
Cell Size
A
B
CI
S
CON
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
0
1
1
1
1
0
1
0
0
0
Drive Strength
AFHCONX2
AFHCONX4
Height (µm) Width (µm)
5.04
5.04
Functional Schematic
A
B
CI
S
CON
TSMC 0.18µm Process SAGE-X Standard Cell Library Databook
266
15.84
17.16
AFHCON
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
A
B
CI
X2
X4
0.1822
0.1658
0.1194
0.2036
0.1854
0.1721
A
B
CI
X2
X4
0.0071
0.0213
0.0135
0.0072
0.0224
0.0270
Delays at 25 oC, 3.3V, Typical Process
Intrinsic Delay (ns)
Description
A
A
B
B
CI
CI
A
A
B
B
CI
CI
→
→
→
→
→
→
→
→
→
→
→
→
S↑
S↓
S↑
S↓
S↑
S↓
CON↑
CON↓
CON↑
CON↓
CON↑
CON↓
Kload (ns/pF)
X2
X4
X2
X4
0.237
0.275
0.168
0.191
0.135
0.151
0.225
0.187
0.150
0.118
0.067
0.046
0.253
0.290
0.175
0.208
0.122
0.157
0.249
0.219
0.172
0.147
0.052
0.039
2.876
1.611
2.877
1.611
2.874
1.612
3.128
1.935
3.169
1.952
2.778
1.657
2.873
1.599
2.872
1.599
2.873
1.600
2.990
1.857
3.010
1.866
1.366
0.830
TSMC 0.18µm Process SAGE-X Standard Cell Library Databook
267
AFCSHCIN
Your logo here
Cell Description
Logic Symbol
The AFCSHCIN cell provides a carry-select adder
function that produces the arithmetic sum (S) and
carry-outs (CO0, CO1) of the operands (A,B) with
active-low carry-ins (CI0N, CI1N).The three outputs
(S, CO0, CO1) are represented by the logic
equations:
A
B
S = CS • ( A ⊕ B ⊕ CI 1N ) + CS • ( A ⊕ B ⊕ CI 0N )
S
CI0N
CO0
CI1N
CO1
CS
CO0 = ( A • B ) + ( A • CI 0N ) + ( B • CI 0N )
CO1 = ( A • B ) + ( A • CI 1N ) + ( B • CI 1N )
Cell Size
Drive Strength
Height (µm) Width (µm)
AFCSHCINX2
AFCSHCINX4
5.04
5.04
33.00
38.28
Functions
A
B
CI0N
CI1N
CS
S
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
0
0
1
0
0
0
0
0
1
1
0
1
1
CO0 CO1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
A
B
CI0N
CI1N
CS
S
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
1
1
0
1
1
1
1
1
0
0
1
0
0
TSMC 0.18µm Process SAGE-X Standard Cell Library Databook
276
CO0 CO1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
1
1
1
1
1
1
AFCSHCIN
Your logo here
Functional Schematic
A
B
1
S
0
CS
CO1
CO0
CI1N
CI0N
AC Power
Pin Capacitance
Power (µW/MHz)
Pin
CS
A
B
CI0N
CI1N
Capacitance (pF)
Pin
X2
X4
0.0666
0.3490
0.3126
0.1311
0.1322
0.0666
0.3860
0.3444
0.1644
0.1636
CS
A
B
CI0N
CI1N
X2
X4
0.0056
0.0075
0.0170
0.0085
0.0085
0.0056
0.0075
0.0170
0.0146
0.0144
TSMC 0.18µm Process SAGE-X Standard Cell Library Databook
277
AFCSHCIN
Your logo here
Delays at 25 oC, 3.3V, Typical Process
Intrinsic Delay (ns)
Description
CS
CS
A
A
B
B
CI0N
CI0N
CI1N
CI1N
A
A
B
B
CI0N
CI0N
A
A
B
B
CI1N
CI1N
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
S↑
S↓
S↑
S↓
S↑
S↓
S↑
S↓
S↑
S↓
CO0↑
CO0↓
CO0↑
CO0↓
CO0↑
CO0↓
CO1↑
CO1↓
CO1↑
CO1↓
CO1↑
CO1↓
Kload (ns/pF)
X2
X4
X2
X4
0.147
0.131
0.454
0.423
0.372
0.364
0.284
0.301
0.255
0.284
0.218
0.270
0.177
0.205
0.090
0.049
0.214
0.285
0.150
0.205
0.086
0.051
0.148
0.135
0.485
0.447
0.397
0.391
0.291
0.307
0.251
0.279
0.253
0.325
0.208
0.250
0.069
0.041
0.264
0.337
0.192
0.254
0.065
0.041
2.265
1.303
2.266
1.306
2.266
1.306
2.266
1.306
2.266
1.303
3.130
1.630
3.048
1.608
3.159
1.571
3.030
1.692
3.047
1.680
3.092
1.636
2.261
1.281
2.261
1.282
2.261
1.283
2.261
1.283
2.261
1.282
3.069
1.597
3.062
1.589
1.590
0.817
2.756
1.665
2.747
1.657
1.543
0.817
TSMC 0.18µm Process SAGE-X Standard Cell Library Databook
278
AFCSHCON
Your logo here
Cell Description
Logic Symbol
The AFCSHCON cell provides a carry-select adder
function that produces the arithmetic sum (S) and
active-low carry-outs (CO0N, CO1N) of two
operands (A,B) with carry-ins (CI0, CI1). The three
outputs (S, CO0N, CO1N) are represented by the
logic equations:
A
B
S
CI0
CO0N
S = CS • ( A ⊕ B ⊕ CI 1 ) + CS • ( A ⊕ B ⊕ CI 0 )
CI1
CO1N
CO0N = ( A • B ) + ( A • CI 0 ) + ( B • CI 0 )
CS
CO1N = ( A • B ) + ( A • CI 1 ) + ( B • CI 1 )
Cell Size
Drive Strength
Height (µm) Width (µm)
AFCSHCONX2
AFCSHCONX4
5.04
5.04
33.66
38.94
Functions
A
B
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
CI0 CI1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
CS
S
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
1
1
0
1
1
1
1
1
0
0
1
0
0
CO0N CO1N
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
A
B
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
CI0 CI1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
CS
S
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
0
0
1
0
0
0
0
0
1
1
0
1
1
TSMC 0.18µm Process SAGE-X Standard Cell Library Databook
279
CO0N CO1N
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
AFCSHCON
Your logo here
Functional Schematic
A
B
1
S
0
CS
CO1N
CO0N
CI1
CI0
AC Power
Pin Capacitance
Power (µW/MHz)
Pin
CS
A
B
CI0
CI1
Capacitance (pF)
Pin
X2
X4
0.0663
0.3524
0.3292
0.1636
0.1379
0.0664
0.3942
0.3722
0.2092
0.1822
CS
A
B
CI0
CI1
X2
X4
0.0092
0.0136
0.0156
0.0128
0.0125
0.0092
0.0137
0.0156
0.0255
0.0253
TSMC 0.18µm Process SAGE-X Standard Cell Library Databook
280
AFCSHCON
Your logo here
Delays at 25 oC, 3.3V, Typical Process
Intrinsic Delay (ns)
Description
CS
CS
A
A
B
B
CI0
CI0
CI1
CI1
A
A
B
B
CI0
CI0
A
A
B
B
CI1
CI1
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
S↑
S↓
S↑
S↓
S↑
S↓
S↑
S↓
S↑
S↓
CO0N↑
CO0N↓
CO0N↑
CO0N↓
CO0N↑
CO0N↓
CO1N↑
CO1N↓
CO1N↑
CO1N↓
CO1N↑
CO1N↓
Kload (ns/pF)
X2
X4
X2
X4
0.148
0.131
0.481
0.431
0.430
0.396
0.278
0.278
0.234
0.247
0.279
0.276
0.235
0.222
0.078
0.053
0.289
0.271
0.255
0.219
0.072
0.049
0.149
0.135
0.526
0.471
0.472
0.421
0.272
0.264
0.224
0.233
0.333
0.338
0.298
0.281
0.066
0.043
0.339
0.338
0.304
0.281
0.058
0.037
2.265
1.303
2.266
1.307
2.266
1.306
2.266
1.305
2.265
1.304
2.718
1.702
2.985
1.701
3.068
1.771
3.042
1.658
3.043
1.649
3.062
1.772
2.261
1.281
2.262
1.284
2.261
1.284
2.262
1.283
2.261
1.282
2.711
1.667
2.710
1.667
1.636
0.915
3.108
1.635
3.108
1.635
1.556
0.829
TSMC 0.18µm Process SAGE-X Standard Cell Library Databook
281
AHHCIN
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Cell Description
Logic Symbol
The AHHCIN cell is a half adder that provides the
arithmetic sum (S) and carry-out (CO) of the input
operand (A) with an active-low carry-in (CIN). The
outputs (S, CO) are represented by the logic
equations:
A
S
CIN
CO
S = A ⊕ CIN
CO = A • CIN
Cell Size
Functions
A
CIN
S
CO
0
0
1
1
0
1
0
1
1
0
0
1
0
0
1
0
Drive Strength
AHHCINX2
AHHCINX4
Height (µm) Width (µm)
5.04
5.04
Functional Schematic
A
CIN
S
CO
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272
7.92
9.24
AHHCIN
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
A
CIN
X2
X4
0.0909
0.0762
0.1114
0.1024
A
CIN
X2
X4
0.0081
0.0157
0.0102
0.0211
Delays at 25 oC, 3.3V, Typical Process
Intrinsic Delay (ns)
Description
X2
A
A
CIN
CIN
A
A
CIN
CIN
→
→
→
→
→
→
→
→
S↑
S↓
S↑
S↓
CO↑
CO↓
CO↑
CO↓
0.094
0.101
0.056
0.073
0.080
0.101
0.054
0.025
X4
0.093
0.092
0.055
0.070
0.073
0.095
0.051
0.024
Kload (ns/pF)
X2
3.322
1.868
3.320
1.909
4.917
1.665
4.915
1.655
X4
3.327
1.912
3.326
1.930
2.458
0.832
2.458
0.827
TSMC 0.18µm Process SAGE-X Standard Cell Library Databook
273
AHHCON
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Cell Description
Logic Symbol
The AHHCON cell is a half adder that provides the
arithmetic sum (S) and active-low carry-out (CON)
of the input operand (A) with carry-in (CI). The
outputs (S, CON) are represented by the logic
equations:
A
S
CI
CON
S = A ⊕ CI
CON = A • CI
Cell Size
Functions
A
CI
S
CON
0
0
1
1
0
1
0
1
0
1
1
0
1
1
1
0
Drive Strength
AHHCONX2
AHHCONX4
Height (µm) Width (µm)
5.04
5.04
Functional Schematic
A
CI
S
CON
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
278
7.26
8.58
AHHCON
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
A
CI
X2
X4
0.0995
0.0606
0.1255
0.0786
A
CI
X2
X4
0.0119
0.0172
0.0181
0.0231
Delays at 25 oC, 1.8V, Typical Process
Intrinsic Delay (ns)
Description
A
A
CI
CI
A
A
CI
CI
→
→
→
→
→
→
→
→
S↑
S↓
S↑
S↓
CON↑
CON↓
CON↑
CON↓
Kload (ns/pF)
X2
X4
X2
X4
0.103
0.111
0.058
0.074
0.039
0.026
0.032
0.023
0.104
0.110
0.056
0.069
0.039
0.024
0.030
0.020
3.240
1.858
3.223
1.814
2.988
2.002
2.990
2.002
3.235
1.854
3.230
1.835
1.494
0.924
1.495
0.924
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
279
BENC
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Cell Description
Logic Symbol
The booth encoder block (BENC) cell performs
a 2-bit multiplier recoding per a modified
Booth’s algorithm. Each BENC cell examines
3 bits of the multiplier (M0, M1, M2) and
generates the appropriate control signals to
adjust the multiplicand for subsequent partial
product reduction. The outputs (S, A, X2) are
represented by the logic equations:
S = M2 • ( M1 + M0 )
M2
S
M1
A
M0
X2
Cell Size
A = M2 • ( M1 + M0 )
Drive Strength
X 2 = M1 ⊕ M0
BENCX1
BENCX2
BENCX4
Functions
M2
M1
M0
X2
A
S
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
x
0
0
1
1
0
0
x
1
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
Height (µm) Width (µm)
5.04
5.04
5.04
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
280
20.46
27.06
40.26
BENC
Your logo here
Functional Schematic
M0
M1
X2
M2
A
S
AC Power
Pin Capacitance
Power (µW/MHz)
Pin
M2
M1
M0
Capacitance (pF)
Pin
X1
X2
X4
0.0793
0.1639
0.1885
0.1390
0.2840
0.3208
0.2528
0.5764
0.5996
M2
M1
M0
X1
X2
X4
0.0079
0.0104
0.0095
0.0099
0.0173
0.0155
0.0160
0.0302
0.0245
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
281
BENC
Your logo here
Delays at 25 oC, 1.8V, Typical Process
Intrinsic Delay (ns)
Kload (ns/pF)
Description
M2
M2
M1
M1
M0
M0
M2
M2
M1
M1
M0
M0
M1
M1
M0
M0
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
A↑
A↓
A↑
A↓
A↑
A↓
S↑
S↓
S↑
S↓
S↑
S↓
X2↑
X2↓
X2↑
X2↓
X1
X2
X4
X1
X2
X4
0.228
0.208
0.254
0.179
0.245
0.172
0.177
0.138
0.312
0.305
0.285
0.247
0.211
0.259
0.266
0.276
0.229
0.215
0.233
0.169
0.220
0.159
0.176
0.128
0.277
0.269
0.245
0.236
0.180
0.228
0.216
0.258
0.214
0.221
0.206
0.183
0.192
0.170
0.168
0.137
0.254
0.280
0.234
0.236
0.186
0.216
0.225
0.253
1.117
0.664
1.116
0.665
1.116
0.665
1.174
0.656
1.174
0.657
1.174
0.657
1.104
0.709
1.104
0.710
0.562
0.326
0.562
0.327
0.562
0.327
0.562
0.325
0.562
0.326
0.562
0.326
0.552
0.455
0.551
0.455
0.281
0.163
0.281
0.163
0.281
0.163
0.279
0.156
0.279
0.157
0.279
0.156
0.253
0.174
0.253
0.174
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
282
BMX
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Cell Description
Logic Symbol
The BMX cell performs the shifting and 2’s
complement inversion of the multiplicand bits (M1
and M0) based on the recode control signals (X2, A,
and S) from the BENC cell. The partial product
output (PP) is represented by the logic equation:
M0
PP
M1
PP = X 2 • ( ( M0 • A ) + ( M0 • S ) ) + X 2 • ( ( M1 • A ) + ( M1 • S ) )
A S X2
Functions1
1
X2
A
S
M0
M1
PP
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
1
1
0
0
1
0
1
1
0
0
1
x
x
x
x
x
x
x
0
1
0
1
x
x
0
1
0
1
x
x
x
x
x
x
x
x
0
1
1
0
0
x
0
1
1
0
0
Cell Size
Drive Strength
BMXX1
Height (µm) Width (µm)
5.04
Shaded areas represent illegal conditions.
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
283
12.54
BMX
Your logo here
Functional Schematic
M0
A
1
S
0
1
PP
0
1
0
M1
X2
AC Power
Pin Capacitance
Power (µW/MHz)
Pin
Capacitance (pF)
Pin
X1
X2
M0
A
S
M1
0.0404
0.0596
0.0623
0.0816
0.0517
X1
X2
M0
A
S
M1
0.0034
0.0057
0.0046
0.0044
0.0053
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
284
BMX
Your logo here
Delays at 25 oC, 1.8V, Typical Process
Intrinsic Delay (ns)
Kload (ns/pF)
Description
X2
X2
M0
M0
A
A
S
S
M1
M1
→
→
→
→
→
→
→
→
→
→
PP↑
PP↓
PP↑
PP↓
PP↑
PP↓
PP↑
PP↓
PP↑
PP↓
X1
X1
0.146
0.130
0.210
0.257
0.232
0.226
0.253
0.241
0.193
0.231
4.516
2.495
4.521
2.500
4.520
2.499
4.521
2.499
4.521
2.489
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
285
CMPR22
Your logo here
Cell Description
Logic Symbol
The CMPR22 cell provides the arithmetic sum (S)
and carry out (CO) of two operands (A, B). The two
outputs (S, CO) are represented by the logic
equations:
S = ( A • B) + ( A • B)
A
S
B
CO
CO = A • B
Functions
Cell Size
A
B
S
CO
Drive Strength
0
0
1
1
0
1
0
1
0
1
1
0
0
0
0
1
CMPR22X1
Height (µm) Width (µm)
5.04
Functional Schematic
A
B
S
CO
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
286
7.92
CMPR22
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
X1
A
B
X1
A
B
0.1120
0.0621
0.0108
0.0089
Delays (25 oC, 1.8V, Typical Process)
Intrinsic Delay (ns)
Kload (ns/pF)
X1
X1
0.090
0.095
0.060
0.080
0.089
0.127
0.089
0.122
2.756
1.627
2.735
1.551
4.522
2.620
4.520
2.617
Description
A
A
B
B
A
A
B
B
→
→
→
→
→
→
→
→
S↑
S↓
S↑
S↓
CO↑
CO↓
CO↑
CO↓
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
287
CMPR32
Your logo here
Cell Description
Logic Symbol
The CMPR32 cell takes in 3 bits of the partial product
(A, B, C) and compresses them into 2-bits of partial
product (S, CO). The two outputs (S, CO) are
represented by the logic equations:
S = A⊕B⊕C
A
S
B
CO
C
CO = ( A • B ) + ( A • C ) + ( B • C )
Functions
Cell Size
A
B
C
S
CO
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
0
1
0
0
0
1
0
1
1
1
Drive Strength
Height (µm) Width (µm)
CMPR32X1
5.04
Functional Schematic
A
B
C
S
CO
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
288
13.86
CMPR32
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
X1
A
B
C
X1X2
A
B
C
0.1196
0.1533
0.0630
0.0072
0.0070
0.0066
Delays at 25 oC, 1.8V, Typical Process
Intrinsic Delay (ns)
Description
A
A
B
B
C
C
A
A
B
B
C
C
→
→
→
→
→
→
→
→
→
→
→
→
S↑
S↓
S↑
S↓
S↑
S↓
CO↑
CO↓
CO↑
CO↓
CO↑
CO↓
Kload (ns/pF)
X1
X1
0.231
0.311
0.271
0.354
0.182
0.158
0.285
0.279
0.327
0.302
0.143
0.190
4.532
2.614
4.538
2.613
4.533
2.614
4.512
2.514
4.512
2.465
4.527
2.537
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
289
XOR3
Your logo here
Cell Description
Logic Symbol
The XOR3 cell provides a logical EXCLUSIVE OR
of three inputs (A,B,C). The output (Y) is represented
by the following equation:
A
B
C
Y = A⊕B⊕C
Y
Functions
A
B
C
Y
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
0
1
Cell Size
Drive Strength
XOR3X2
XOR3X4
Height (µm) Width (µm)
5.04
5.04
Functional Schematic
A
B
Y
C
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
290
11.88
19.80
XOR3
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
A
B
C
X2
X4
0.1477
0.1283
0.0601
0.2802
0.2402
0.1099
A
B
C
X2
X4
0.0069
0.0151
0.0088
0.0137
0.0285
0.0163
Delays at 25 oC, 1.8V, Typical Process
Description
A
A
B
B
C
C
→
→
→
→
→
→
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
Intrinsic Delay
(ns)
Kload (ns/pF)
X2
X4
X2
X4
0.276
0.301
0.180
0.221
0.147
0.144
0.260
0.280
0.168
0.210
0.139
0.139
2.226
1.319
2.225
1.308
2.224
1.301
1.113
0.655
1.113
0.653
1.113
0.650
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
291
XNOR3
Your logo here
Cell Description
Logic Symbol
The XNOR3 cell provides a logical EXCLUSIVE
NOR of three inputs (A,B,C). The output (Y) is
represented by the following equation:
A
B
C
Y = A⊕B⊕C
Y
Functions
A
B
C
Y
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
0
0
1
0
1
1
0
Cell Size
Drive Strength
XNOR3X2
XNOR3X4
Height (µm) Width (µm)
5.04
5.04
Functional Schematic
A
B
Y
C
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
292
11.88
19.80
XNOR3
Your logo here
AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
A
B
C
X2
X4
0.1475
0.1252
0.0606
0.2786
0.2308
0.1100
A
B
C
X2
X4
0.0069
0.0151
0.0052
0.0137
0.0284
0.0093
Delays at 25 oC, 1.8V, Typical Process
Intrinsic Delay (ns)
Description
A
A
B
B
C
C
→
→
→
→
→
→
Y↑
Y↓
Y↑
Y↓
Y↑
Y↓
X2
X4
0.275
0.303
0.181
0.219
0.148
0.143
0.260
0.283
0.169
0.207
0.139
0.139
Kload (ns/pF
X2
X4
2.225
1.318
2.225
1.309
2.224
1.303
1.113
0.655
1.113
0.653
1.113
0.650
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
293
Advanced Arithmetics
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
294
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
295
CMPR42
Your logo here
Cell Description
Logic Symbol
The CMPR42 cell takes in 4 bits of the partial product
(A, B, C, D) and compresses them into 2-bits of
partial product (S, CO). The cell requires an
intermediate carry-in input (ICI) from the n-1
compressor and an intermediate carry-out output
(CO) to the n+1 compressor. The CMPR42 cell also
contains an internal sum (IS). The internal sum (IS),
carry-in output (ICO), and the two outputs (S, CO)
are represented by the logic equations:
A
S
B
CO
C
ICO
D
ICI
IS = A ⊕ B ⊕ C
ICO = ( A • B ) + ( A • C ) + ( B • C )
S = IS ⊕ D ⊕ ICI
Cell Size
CO = ( IS • D ) + ( IS • ICI ) + ( D • ICI )
Drive Strength
CMPR42X1
CMPR42X2
Functions
A
B
C
IS
ICO
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
0
1
0
0
0
1
0
1
1
1
IS
D
ICI
S
CO
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
0
1
0
0
0
1
0
1
1
1
Height (µm) Width (µm)
5.04
5.04
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
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22.44
26.40
CMPR42
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Functional Schematic
A
B
IS
C
D
ICI
S
ICO
CO
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
297
CMPR42
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AC Power
Power (µW/MHz)
Pin
A
B
C
D
ICI
X1
X2
0.1702
0.1642
0.1542
0.1267
0.0677
0.2942
0.2798
0.2668
0.2124
0.1189
Pin Capacitance
Capacitance (pF)
Pin
A
B
C
D
ICI
X1
X2
0.0086
0.0086
0.0082
0.0047
0.0029
0.0162
0.0164
0.0136
0.0095
0.0061
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CMPR42
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Delays at 25 oC, 1.8V, Typical Process
Intrinsic Delay (ns)
Description
A
A
B
B
C
C
D
D
ICI
ICI
A
A
B
B
C
C
A
A
B
B
C
C
D
D
ICI
ICI
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
S↑
S↓
S↑
S↓
S↑
S↓
S↑
S↓
S↑
S↓
ICO↑
ICO↓
ICO↑
ICO↓
ICO↑
ICO↓
CO↑
CO↓
CO↑
CO↓
CO↑
CO↓
CO↑
CO↓
CO↑
CO↓
Kload (ns/pF)
X1
X2
X1
X2
0.549
0.647
0.479
0.569
0.425
0.523
0.438
0.452
0.251
0.270
0.123
0.197
0.123
0.185
0.107
0.160
0.533
0.614
0.473
0.544
0.420
0.456
0.387
0.401
0.154
0.198
0.542
0.648
0.445
0.551
0.402
0.512
0.339
0.410
0.191
0.210
0.091
0.166
0.092
0.159
0.082
0.139
0.526
0.618
0.462
0.554
0.389
0.432
0.315
0.321
0.101
0.158
4.532
2.493
4.528
2.493
4.530
2.493
4.525
2.491
4.528
2.495
4.531
2.496
4.530
2.514
4.526
2.520
4.532
2.511
4.522
2.510
4.531
2.511
4.525
2.508
4.534
2.556
2.238
1.291
2.238
1.291
2.238
1.291
2.235
1.291
2.237
1.291
2.238
1.230
2.239
1.234
2.236
1.236
2.237
1.230
2.238
1.229
2.237
1.230
2.235
1.223
2.238
1.246
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Register File Cells
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TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
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RF1R1W
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Cell Description
Logic Symbol
The RF1R1W register file cell is an active-high
D-type transparent latch with an active-high tri-state
output. The output (RB) is inverted.
RB
WB
WW
Functions for Write Operations
WW
WB
Q[n+1]
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
Q[n]
Q[n]
Q[n]
0
1
Q[n]
1
RW
RWN
Cell Size
Drive Strength
RF1R1WX2
Height (µm) Width (µm)
5.04
Functions for Read Operations1
RW
RWN
Q
RB
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
Hi-Z
Hi-Z
Hi-Z
1
0
Hi-Z
0
1 Shaded areas represent operations that are legal only
during RW/RWN transitions.
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6.60
RF1R1W
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Functional Schematic
WW
RW
Q
WB
RB
RWN
AC Power
Pin Capacitance
Power (µW/MHz)
Capacitance (pF)
Pin
Pin
X2
WW
WB
RW
RB
X2
0.0375
0.0379
0.0119
0.0226
WW
WB
RW
RWN
RB
0.0054
0.0023
0.0030
0.0020
0.0091
Delays at 25 oC, 1.8V, Typical Process
Intrinsic Delay (ns)
Description
WW
WW
WB
WB
RW
RW
→
→
→
→
→
→
RB↑
RB↓
RB↑
RB↓
RB↑
RB↓
Kload (ns/pF)
X2
X2
0.291
0.175
0.273
0.190
0.033
0.014
4.358
1.810
4.358
1.810
4.354
1.804
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RF1R1W
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Timing Constraints at 25 oC, 1.8V, Typical Process
Interval (ns)
Pin
Requirement
X2
WW
WB
minpwh
setup↑ → WW
setup↓ → WW
hold↑ → WW
hold↓ → WW
0.18
0.10
0.15
-0.09
-0.14
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RF2R1W
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Cell Description
Logic Symbol
The RF2R1W register file cell is an active-high Dtype transparent latch with two independently
controlled, active-high tri-state outputs. The cell has
two read ports and one write port. The outputs (R1B,
R2B) are inverted.
WB
R1B
WW
R2B
R1W
R2W
Functions for Write Operations
WW
WB
Q[n+1]
0
0
1
1
0
1
0
1
Q[n]
Q[n]
0
1
Cell Size
Drive Strength
RF2R1WX2
Height (µm) Width (µm)
5.04
10.56
Functions for Read Operations
R1W/ R2W
Q
R1B/ R2B
0
0
1
1
0
1
0
1
Hi-Z
Hi-Z
1
0
Functional Schematic
R1W
R1B
WW
Q
r1wn
WB
R2W
wwn
WW
wwn
R1W
r1wn
R2W
r2wn
wwn
R2B
r2wn
WW
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RF2R1W
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AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
X2
WB
WW
R1W
R2W
R1B
X2
WB
WW
R1W
R2W
R1B
R2B
0.0519
0.0141
0.0131
0.0129
0.0973
0.0024
0.0045
0.0034
0.0045
0.0051
0.0050
Delays at 25 oC, 1.8V, Typical Process
Intrinsic Delay (ns)
Description
WB
WB
WW
WW
R1W
R1W
WB
WB
WW
WW
R2W
R2W
→
→
→
→
→
→
→
→
→
→
→
→
R1B↑
R1B↓
R1B↑
R1B↓
R1B↑
R1B↓
R2B↑
R2B↓
R2B↑
R2B↓
R2B↑
R2B↓
Kload (ns/pF)
X2
X2
0.313
0.228
0.328
0.214
0.071
0.016
0.312
0.228
0.327
0.214
0.070
0.016
4.359
1.818
4.360
1.818
4.354
1.803
4.360
1.818
4.359
1.817
4.354
1.803
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
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RF2R1W
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Timing Constraints at 25 oC, 1.8V, Typical Process
Interval (ns)
Pin
Requirement
X2
WB
WW
setup↑ → WW
setup↓ → WW
hold↑ → WW
hold↓ → WW
minpwh
0.12
0.17
-0.10
-0.15
0.18
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
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RFRD
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Cell Description
Logic Symbol
The RFRD output buffer has a “keeper” function that
holds the input and output ports at the present level
when the input (RB) is in a state of high-impedance.
BRB
RB
Functions
RB
BRB
0
1
Hi-Z
1
0
Keep
Cell Size
Drive Strength
RFRDX1
RFRDX2
RFRDX4
Height (µm) Width (µm)
5.04
5.04
5.04
Functional Schematic
RB
BRB
TSMC 0.18µm Process 1.8-Volt SAGE-XTM Standard Cell Library Databook
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3.30
3.30
3.96
RFRD
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AC Power
Pin Capacitance
Capacitance (pF)
Power (µW/MHz)
Pin
Pin
RB
X1
X2
X4
0.0303
0.0385
0.0555
RB
X1
X2
X4
0.0251
0.0260
0.0329
Delays at 25 oC, 1.8V, Typical Process
Intrinsic Delay (ns)
Kload (ns/pF)
Description
RB → BRB↑
RB → BRB↓
X1
X2
X4
X1
X2
X4
0.051
0.031
0.035
0.021
0.026
0.015
4.519
2.401
2.234
1.194
1.117
0.597
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