Improving Isolated SMPS, UPS and other Power Systems with CMOS
Isolation Products
Fully-integrated isolated gate drivers and PMBus communication interfaces can significantly increase
efficiency, performance and reliability compared to legacy solutions
Introduction
As today’s emerging “green” energy standards challenge designers to deliver systems with increased
power efficiency and system reliability while decreasing cost and size, the need for more highly-integrated
power components becomes increasingly important. Isolated gate drivers and digital isolators are critical
building blocks within today’s ac-dc and isolated dc-dc power supplies. This paper describes how SMPS,
UPS and other similar power system designers can improve their products by adopting fully-integrated
isolation solutions from Silicon Labs.
Rectifier
PFC
PRIMARY
400VDC
VIN
SECONDARY
FULL BRIDGE
TOPOLOGY
Local VDD
Q1 I1
HIGH SIDE
DRIVER
Q3
Q4
XFMR
PRIMARY
LOW SIDE
DRIVER
AC
LINE IN
Q2
LOW SIDE
DRIVER
Q6
OUTPUT
VS
XFMR
SECONDARY
VS
HIGH SIDE
DRIVER
SYNCHRONOUS
RECTIFIERS
I2
ISOLATION BARRIER
SMPS
Controller
Q5
AC CURRENT
SENSOR
AC CURRENT
SENSOR
ISOLATED
DRIVER
ISOLATED
DRIVER
FEEDBACK
ISOLATION
PMBus
ISOLATION
4
PMBus or I2C
Interface
Figure 1: AC/DC Converter Using Full Bridge Topology
Silicon Laboratories, Inc.
1
Example System:
Isolated power converters require power stage and signal isolation to meet safety standards. The
example of Figure 1 shows an ac-dc converter typical of 500 W to 5 kW power systems, such as those
used in central office telecom rectifier supplies. The first stage of this two-stage system is a power factor
correction circuit (PFC) that increases system efficiency by forcing the ac line current to be in-phase with
the line voltage (i.e. purely resistive load). The resulting 400 VDC PFC output voltage is supplied to the
second stage isolated PWM full-bridge dc/dc converter that converts the input to a lower value useable
by the end application (e.g. 72 V). The full bridge operates by alternately turning corner switch pairs Q1,
Q2 and Q3, Q4 on and off, causing alternating current to flow through the transformer primary (I1 and I2
current in Figure 1). This results in an ac waveform at the transformer secondary, which is then converted
to dc by synchronous rectifier switches Q5 and Q6.
The primary-side high-side switch driver inputs in Figure 1 are referenced to the primary-side ground
while the driver outputs are referenced to the high-side MOSFET source pins. The high-side drivers must,
therefore, be able to withstand the 400 VDC common-mode voltage present at the source pin during highside drive. The corresponding low-side drivers operate from a low-voltage local supply (e.g. 18 V) and
referenced to the primary-side ground. Note also the two ac current sensors in the low-side legs of the
bridge that monitor the current in each leg to facilitate flux balancing if voltage mode control is used. The
isolation barrier of Figure 1 ensures no current flow between the primary and secondary-side grounds;
consequently, the drivers for synchronous MOSFETs Q5 and Q6 must be isolated. The secondary-side
feedback path (and PMBus or I2C communication interface, if used) must also be isolated for the same
reason.
While optocouplers are commonly used for feedback isolation, they are not fast enough for use in the
synchronous MOSFET gate drive isolation circuit. While faster optocouplers are available, they tend to be
expensive and exhibit performance and reliability liabilities typical of optocouplers, such as loss of
performance over temperature and device age. For example, published opto-coupler and opto-driver
failure rates (FITs) are typically 10 times higher than couplers based on CMOS technology. As a result, gate
drive transformers have become popular in isolated synchronous rectifier applications. Advancements in
CMOS-based (Complementary Metallic Oxide Semiconductor) isolation technology make possible isolators
having near-ideal performance, power, integration and reliability characteristics. These devices are well
positioned to supersede both optocouplers and gate drive transformers in switch mode power
applications. For a more detailed comparison between ISOpro and optocouplers, see Silicon Labs white
paper: “ISOpro RF Isolators Supersede Optocouplers in Industrial Applications”.
Silicon Laboratories, Inc.
2
ISOpro Technology Overview
ISOpro is an RF carrier-based isolation technology fabricated in main-stream CMOS, supplied in standard
IC packaging and offered in 1 kV, 2.5 kV and 5 kV isolation ratings. This technology offers uniform, stable
performance over operating voltage and temperature with none of the fundamental weaknesses of
optocouplers. A block diagram of an ISOpro isolator channel is shown in Figure 2a.
ISOdriver Channel
Die #1
VDD
Die #2
ISOLATION
IN
INPUT
CONDITIONING
+
+
-
-
XMITTER
RECVR
DIFFERENTIAL ISOLATION
BARRIER
DRIVER
Input
Die
Output
Die
OUT
GND
Input Pin
RF ENERGY
Transmitter Output
RF ENERGY
Receiver Input
Output Pin
a) Block Diagram
b) Decapsulated Die Photo
Figure 2: ISOpro Isolator
The operation of the ISOpro is analogous to that of an optocoupler, except an RF carrier is used instead of
light. ISOpro isolators consist of two identical semiconductor dies in a standard IC package where each die
contains both transmit and receive circuits. When wire-bonded together (Figure 2b), the two die form an
RF transmitter and receiver separated by a differential capacitive isolation barrier. Data is transferred
from input to output by simple on/off keying (OOK) modulation, i.e. when an input pin (VIN) is high, the
transmitter generates an RF carrier that propagates across the isolation barrier to the receiver. The
receiver asserts logic 1 on the output pin (VOUT) when sufficient in-band carrier energy is detected. When
VIN is low, the transmitter is off, and the receiver drives VOUT low because no in-band RF energy is
detected.
This deceptively simple architecture offers significant benefits compared to other isolation schemes,
including:
 Greater operating stability over supply voltage, temperature and device age
 Wider operating range: -40 to +125 °C
 Significantly lower power consumption
 Tighter timing characteristics for more consistent end-system performance
 Significantly higher speed data transmission
 Higher reliability (mainstream CMOS process technology)
 Higher common-mode transient immunity (CMTI)
 High RF and magnetic field immunity
 Significantly higher device integration (up to 6 channels per package)
 Low EMI - meets FCC Class B Part 15
 Highly competitive price per channel
Silicon Laboratories, Inc.
3
ISOpro vs. Gate Drive Transformers:
Gate drive transformers (Figure 3) are miniature torroidal transformers that are preferred over
optocouplers in gate drive applications because of their shorter delay times. While they are faster than
optocouplers, gate drive transformers cannot propagate a dc level; they can pass only a finite voltagetime product across the isolation boundary. These transformers must be reset after each ON cycle to
avoid core saturation (requiring external circuitry) and restrict both tON and duty cycle range, which
compromise transient load performance.
+5V
-5V
10V
0
Basic Circuit
+
-
-
+
DC Restore
a)
Typical Gate Drive Transformer
b) Gate Drive Transformer Circuits
Figure 3: Gate Drive Transformers
A basic transformer-isolated gate drive circuit (Figure 3b) places a dc blocking capacitor in series with the
gate drive transformer. During operation, a dc bias develops across the blocking capacitor in an amount
equal to the gate drive voltage amplitude multiplied by the duty cycle (VBC = VDRIVE x D). As a result, this
scheme is not practical for designs requiring duty cycles greater than 50% because the peak output
amplitude decreases as duty cycle increases. Also, the duty cycle-dependant bias changes across the
coupling capacitor can ring with the transformer magnetizing inductance in an amount sufficient to turnon the MOSFET periodically. Compensating for this issue by increasing the blocking capacitor value and/or
gate resistance or slowing down duty cycle rate of change can help, but too large a capacitor value can
cause the transformer to saturate during transients. The bottom graphic of Figure 3b shows a dc restored
isolated gate drive circuit in which the secondary side diode and capacitor restores the dc value of the
gate drive, allowing operation at duty cycles beyond 50%. While higher duty cycles are supported, this
circuit suffers from the same ringing and possible transformer saturation problems previously described.
In addition, during extended off times, the charged primary side capacitor is connected directly across the
transformer primary where it can saturate the transformer. In this case, the transformer secondary
becomes a short circuit, enabling the secondary side capacitor to inadvertently turn-on the MOSFET.
In summary, the transformer-isolated gate drive design is best suited for systems having duty cycles of
50% or less. However, applications like the one shown in Figure 1 typically require a maximum duty cycle
well over 50%. For such applications, transformer isolation will require the dc restore circuit (bottom
graphic, Figure 3b), and its potential pitfalls. The transformer-based design will also have lower efficiency
and higher EMI (and lower/worse transient load performance) and will occupy more board space than the
ISOpro-based solution.
Silicon Laboratories, Inc.
4
ISOpro-Based Solutions
As of the publication date of this paper, ISOpro-based technology addresses isolated gate drive and
PMBus isolation for the example power system of Figure 1. ISOdrivers combine ISOpro isolation
technology with gate driver circuits to create integrated, low-latency isolated driver solutions for MOSFET
and IGBT applications. ISOdrivers are available in three basic configurations (Figure 4): high-side/low-side
isolated drivers with separate control inputs for each output (Figure 4a) or a single PWM input (Figure 4b),
and dual isolated drivers (Figure 4c). All devices are available in 0.5 A and 4.0 A peak output current and
all are available in 1 kV, 2.5 kV and 5 kV isolation ratings. The high-side/low-side versions have built-in
overlap protection and an adjustable dead time generator, while the dual ISOdriver version has no
overlap protection or dead time generator. As such, the dual ISOdriver variants can be used as dual lowside, dual high-side, or high-side/low-side isolated drivers. The single-channel Si826x series ISOdrivers
feature an input circuit that mimics that of an optocoupler. These devices directly replace legacy
optodrivers, and provide substantial gains in performance, power and reliability.
VDDI
VDDI
ISOLATION
VOA
UVLO
GNDA
VDDI
VDD1
DISABLE
VDD1
VDDI
VDDB
VOB
UVLO
DISABLE
ISOLATION
ISOLATION
UVLO
VDDI
VDDI
VDDB
UVLO
VDD1
VDDB
VOB
UVLO
DISABLE
GNDB
UVLO
GNDB
VOA
UVLO
GNDA
STEERING
LOGIC &
DT CONTROL
DT
VDDI
VIA
UVLO
GNDA
VDDI
VDDA
VOA
ISOLATION
ISOLATION
LPWM
DT CONTROL
&
OVERLAP
PROTECTION
DT
VDDI
VDDA
PWM
ISOLATION
VDDA
VIA
VOB
UVLO
LPWM
GNDB
VIB
GND
GND
VIB
HS/LS PWM Input ISOdriver
GND
HS/LS Two Wire Input ISOdriver
Dual ISOdriver
a) Two-Wire Input High-Side/Low-Side
b) One Wire (PWM) Input High-Side/Low-Side
c) Dual ISOdriver
Figure 4: ISOdriver Family
These devices are based on a 3-die architecture that enables drive channels to be isolated from each
other as well as from the input side. This allows the polarity of the high-side and low-side channel to
reverse without latch-up or other damage, a critical system safety and reliability consideration for power
systems and motor control/drives.
Output Die
Input Die
Output Die
Figure 5: Decapsulated ISOdriver
Silicon Laboratories, Inc.
5
Low Side Driver Selection:
Among other considerations, system voltage, output power and efficiency requirements drive the
selection of the system switching MOSFETs, which, in turn, drive the selection of the gate driver. Power
MOSFET selection is made by extracting the key operating parameters from the system specification, then
finding the most cost-effective MOSFET that can meet the requirements as demonstrated by Design
Example 1.
Design Example 1:
Select an ISOdriver to drive the secondary-side full-wave synchronous MOSFETs of Figure 1, assuming a
system output voltage of 12 VDC, and switch rise and fall times of 35 ns, and a MOSFET input capacitance
(Ciss) of 5,180 pF. Assume VGS = 12 V for full enhancement.
Solution:
Referring to Figure 1, the output-side MOSFETs have grounded source terminals; so, 12 V gate drive will
be applied from the MOSFET gate to ground. As a result, the MOSFET gates can be driven with an isolated
dual low-side driver (i.e. Si823x), and the peak current is calculated by first determining the required gate
charge (QG) to fully enhance the MOSFET, then dividing QG by the required rise time as shown in
Equations 1 and 2:
QG = ∆ VGS * Ciss
(Equation1 )
Where ∆ VGS is the gate-to-source voltage
= 12 * 5,180 x 10-12
= 62nC
IPK = QG
tR
(Equation 2)
= 62 x 10-9
35 x 10-9
= 1.8A
While the calculated peak drive current is 1.8 A, the specified 12 V gate drive voltage must be taken into
account in driver selection. For example, a driver specified at 2 A at 18 V will produce a lower peak output
current at a supply voltage of 12 V. The ISOdriver has a 2 A peak sourcing current output at VDD = 12 V,
which is perfect for this application. The ISOdriver application diagram for Design Example 1 is shown in
Figure 6. Note that the bypass capacitors on the Si823x should be located as close to the chip as possible;
the recommended VDD bypass circuit is a 0.1 µF capacitor in parallel with either a 1 μF or 10 μF bypass
capacitor (depending on peak current requirements). Note that resistors R1 and R2 are usually added to
minimize ringing, while diodes D1 and D2 provide fast turn-off to prevent transformer reverse current
flow.
Silicon Laboratories, Inc.
6
12V
5V
C3
0.1uF
C2
1uF
GND
VIA
SYNCHRONOUS
RECTIFIERS
GNDA
Si823x
From
Controller
C4
10uF
Q6
12V
OUTPUT
C1
0.1uF
VDDA
XFMR
SECONDARY
VDDI
VDDB
C3
0.1uF
VIB
C4
10uF
DISABLE
Q5
D1
GNDB
VOA
R2
VOB
R1
D2
Figure 6: Secondary-Side Isolated Driver
Figure 6 is checked for operation within safe thermal limits across the entire load range using Equation 3.
Note that FPWM = 200 kHz, and the input MOSFET input capacitance (CL) is 5,180 pF:
PD = VDDI IDDI + 2(VDDO IQOUT + CINTVDDO2F) + 2n(CLVDDO2F)
(Equation 3)
where:
PD is the total ISOdriver device power dissipation (W)
IDDI is the input-side maximum bias current (3 mA)
IQOUT is the driver die maximum bias current (2.5 mA)
Cint is the internal parasitic capacitance (75 pF for the 0.5 A driver and 370 pF for the 4.0 A driver)
CL is the load capacitance
VDDI is the input-side VDD supply voltage (4.5 to 5.5 V)
VDDO is the driver-side supply voltage (10 to 24 V)
F is the switching frequency (Hz)
n is the overlap constant (max value = 2)
PD = 5(3 x 10-3) + 2(12 x 2.5 x 10-3 + 370 x 10-12 x 122 x 200 x 103) + 2(5,180e-12 x 122 x 200 x 103) = 96 mW
ISOdriver operating temperature: 16SOW ja = (100 C/W) x 96 x 10-3 + 25 C ambient = 34 C.
34 °C is well within the extended temperature range of -40 to 125 °C of the Si823x.
Silicon Laboratories, Inc.
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High-Side Driver Considerations:
Because ISOdriver output channels are isolated from the input and from each other (see Figure 5), they
exhibit less channel-to-channel capacitive coupling, and higher output-side dV/dt immunity compared to
the non-isolated, high-voltage drivers of Figure 1. Like the high-voltage driver, the ISOdriver requires a
high-side bootstrap circuit to provide bias and gate voltage drive current during the high-side switch cycle.
Capacitor CB (Figure 7) charges during the low-side drive period (i.e. when Q2 is on and Q1 off). During
this time, charge current flows from VDD into both the ISOdriver VDDA input and into bootstrap CB. At the
end of the low-side drive period, Q2 is turned off, and Q1 is turned on causing its source terminal to
quickly rise toward VIN. This action reverse biases bootstrap diode D1 and disconnects the ground-based
VDD supply from CB. Since the low side of CB is referenced to the MOSFET source (GNDA), Q1 VGS will be
approximately VDD – 0.7V, thereby holding Q1 in its active state. From this point until the end of the highside drive period, CB supplies all of the current required to maintain high-side driver operation.
RB
D1
D1
GNDA
GNDB
VDDA
VDRAIN
GNDB
VDDA
Q1
OUTA
GNDA
RB
VDRAIN
GNDA
CB
CB
Vgs
GNDA
CB Charge Path
Vgs
CB Charge Path
Cm2
Cm2
VDDB
OUTB
Q1
OUTA
VDDB
Q2
GNDB
OUTB
Q2
GNDB
a) Bootstrap Circuit – CB Charging
b) Bootstrap Circuit – CB Sourcing
Figure 7: Bootstrap Operation
Proper bootstrap design will take into account the total charge required to fully enhance the high-side
MOSFET plus the bias current to support the high-side driver VDD. Other design considerations include
minimizing the ripple on bootstrap capacitor CB and providing additional current to offset leakage. These
considerations coalesce into a total charge CB requirement, which, in turn, drives the value of CB and
charge current. Bootstrap design is covered in detail in Silicon Labs application note “AN486: High-Side
Bootstrap Design Using Si823x ISODrivers in Power Delivery Systems.”
Silicon Laboratories, Inc.
8
Maximizing System Efficiency:
High-side/low-side drive must have a “break-before-make” execution to avoid efficiency-robbing shootthrough currents caused by both MOSFETs being on at the same time. While high-side/low-side ISOdrivers
have overlap protection that disables the outputs when both inputs are high, downstream delays in
power train can still cause shoot through. The time period between switch transitions where both
switches are off is referred to as “dead time” (Figure 8b).
Must avoid shootthrough current (Q1, Q2
on simultaneously)
Q1
A
IOUT = 10A
OUTA
VOUT
Q2 power loss when
ON = IOUT2 x RDSON
= 0.5W
Q2
OUTB
Q2 Power loss
when OFF =
VT x IOUT
= 7W
B
Dead
Time
BODY
DIODE
(VT)
a) Shoot-Through Current
b) Dead Time
Figure 8. Dead Time
A small amount of dead time can increase system efficiency, but larger amounts reduce efficiency as
shown in Figure 8a. The power dissipated by Q2 while on is 0.5 W (10 A through Q2 RDSON of 5 mΩ), but
this increases to 7 W (0.7 V x 10 A) when current flows through the Q2 body diode. Given this, the amount
of dead time added to the system timing must be only large enough to prevent shoot-through current.
OVERLAP
OVERLAP
VOB
VIA
VIA
50%
VIB
VIB
DT
DT
DT
DT
90%
VOA
VOA
10%
DT
DT
90%
VOB
VOB
10%
a)
Normal Dead Time Behavior
b) Dead Time Behavior During Overlap
Figure 9. ISOdriver Dead Time Behavior
High-side/low-side ISOdrivers have an integrated dead time generator that can be set from 4 ns to 950 µs
using an external resistor to ground. Figure 9a shows the timing behavior of the dead time generator in
normal operation. Note that the VIA, VIB timing waveforms are aligned, and dead time is automatically
added on both the rising and falling edges. Note also that overlap protection overrides dead time in the
event that both ISOdriver inputs are high at the same time (Figure 9b). A well-designed configurable
power delivery system using ISOdrivers’ dead-time control feature can, theoretically, increase overall
system efficiency ( by 4%.
Silicon Laboratories, Inc.
9
Dual ISOdrivers:
While dead time optimization can increase efficiency up to 4%, additional efficiency gains may be possible
by paralleling MOSFETs or increasing gate drive to a single, larger MOSFET. In either case, the dual
ISOdriver is useful in providing additional drive capability. Unlike the dedicated high-side/low-side
ISOdrivers, the Si823x Dual ISOdrivers do not have overlap protection or a dead time generator; so, its
output unconditionally follows that of the input as long as the device is powered. Like all ISOdrivers, the
two driver output circuits are isolated from each other, allowing the common-mode voltage between the
two channels to reverse polarity without damaging or upsetting the device (Figure 10).
5V
VDDA
Si823x
VOA Output Signal
VDDA
VOA
GNDI
OUT A
GNDA
GNDA
VIA
VDDB
From
Controller
VDDB
VIB
VOB
OUT B
VOB
GNDB
DISABLE
Common Mode Voltage (V)
VDDI
VOB Output Signal
Common Mode Voltage V1
VOB Output Signal
VOA Output Signal
Common Mode Voltage V2
Time
Figure 10: Common Mode Voltage Inversion
Many power applications, such as UPS systems and inverters, require added drive for parallel switch pairs.
The combined capacitive loading of these switches requires either a higher peak current driver or a less
desirable method of distributing the switches over multiple gate driver ICs. The circuit of Figure 11 shows
each Si823x output driving several common ground switches in parallel. When connected in this way, the
dual ISOdriver can provide an equivalent peak drive current of 8 A while 50 ns propagation delay time
ensures that all switches are driven off and on simultaneously.
Isolated
24VDC
LOAD
VDDI
5V
Si823x
VDDI
VDDA
VOA
GNDA
GNDI
From Controller
VIA
VDDB
GNDB
VIB
VOB
DISABLE
Figure 11 Paralleled Outputs for Increased Peak Output Current
Power circuits in high-voltage systems, such as imaging systems and plasma flat panels, have split ground
systems to isolate higher voltages from lower voltages. In many cases, local supply regulators are built
using a dedicated controller for each regulator or, in other cases, a transformer-coupled multi-output
design (using flyback or other transformer-coupled topology). Figure 12 shows a dual output isolated buck
converter using the Si823x dual ISOdriver. As shown, a single two-loop controller is used with the
ISOdriver to generate two stepped-down output voltages.
Silicon Laboratories, Inc.
10
The ISOdriver in Figure 12 operates as an isolated dual high-side driver where each output is isolated from
both the adjacent output and from the primary side. While this circuit uses a low-cost Schottkey freewheeling diode, a second dual ISOdriver can be added to control output synchronous rectifiers for higher
efficiency.
Isolated
V1
HV
VDDA
5V
Si823x
VDDI
VDDA
VOA
VOUT 1
GNDA
Isolated
V2
GNDI
TWO-LOOP
CONTROLLER
OUT1
VIA
OUT2
VIB
LV
VDDB
VOB
GNDB
I/O
VFB1
VOUT 2
DISABLE
ANALOG SIGNAL
ISOLATION
VFB2
Figure 12: Dual Isolated Buck Converter in Plasma or Imaging System
Isolating PMBus
PMBus is a popular communications interface for networked power system architectures and uses
SMBus/I2C as its physical interface. Most power systems place the PMBus transceiver function on the
secondary-side of the system, often implemented with a small microcontroller and support circuitry.
However, as the Industry trends toward digital control, the I2C interface is often located on the primaryside controller and requires isolation for secondary-side connection. Adding galvanic isolation to the I2C
interface is difficult because the two communication signals (SDA, SCL) are bidirectional.
At first glance, it appears that SDA and SCL can be isolated by simply placing two optocouplers in parallel
and in opposite directions. However, this technique creates feedback that latches the bus line low when a
logic low is asserted by either master or slave. As a result, additional anti-latch circuits must be added to
the design making the discrete optocoupler approach bulky and slow.
Silicon Laboratories, Inc.
11
Optocoupler
Solution
I2C
Buffer
Optocoupler
Si8605
Optocoupler
67%
smaller
Optocoupler
15 mm
300 mm2
Si8405
“I2C+” Isolator
10 mm
20 mm
Optocoupler
10 mm
Comp
15 mm
I2C
Isol.
33%
smaller
Uni
Isol.
Uni
Isol.
10 mm
150 mm
100 mm2
Digital isolator competitor “A”:
I2C + 2 x (1-ch isolator) solution
2
Figure 13: I2C Isolator: Si8600/05 versus Discrete Optocoupler Circuit
The Si860x I2C isolators integrate isolator and anti-latch functions into a single package and provide
isolation to a maximum of 2.5 kVACRMS. Since the SCL pin is bidirectional, these products support clock
stretching and operate to a maximum bus speed of 1.7 Mbps. A complete I2C isolation solution can
contain up to two bidirectional lines (SDA, SCL) and two isolated unidirectional signal lines for reset and
interrupt functions. Figure 13 compares the size and complexity of a discrete optocoupler I2C isolator
implementation (top graphic) with that of the Si8600/05 (note the 300 mm2 area required by the
optocoupler solution does not account for the area occupied by the anti-latch circuits). The 150 mm2
footprint uses a competitor’s I2C isolator but requires a second isolator to supply the extra unidirectional
signal isolators.
I2C Isolator Design Considerations:
Without anti-latch protection, both sides of the bidirectional isolators will latch when an isolator output
logic low propagates back through an adjacent isolator channel, and anti-latch protection must be added
to one side of the isolator to avoid this condition (the "A" side for the Si8600/05). The I2C isolator "A side"
output low (VOL) and input low (VIL) levels are designed so that the isolator, VOL, is greater than the
isolator, VIL (Figure 14).
Side A
Side B
Figure 14: Si860x I2C Anti-Latch Using Level Discrimination
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Ideally, the A side should connect to the bus side that:
(1) meets the isolator’s pull-up current specs (0.5 to 3 mA) and
(2) has the highest VIL (e.g. some bus devices specify VIL = 0.9 V while others specify VIL = 0.3 x Vdd).
Assuming a 3.3 V minimum power supply, the side with VIL = 0.3 x Vdd is the better side because this
side has an input low level of 1.0 V)
(3) has bus devices that can pull down below the isolator input low level and
(4) has the lowest noise.
The use of monolithic I2C isolators with additional unidirectional channels allows system designers to
simplify timing challenges in a design. Instead of being forced to isolate additional status and control
channels in multiple isolator or opto-coupler packages (which results in significant part-to-part timing
variations), monolithic I2C isolators with extra unidirectional channels exhibit timing characteristics that
track very closely across process, voltage and temperature variations. The Si8605 has two additional
unidirectional channels that are useful for isolating reset and interrupt signals. I2C design does not have to
be a mystery. By considering each of these design tips and choosing an isolator appropriate to the
demands, designers can easily implement I2C isolation in their products.
Conclusions
ISOpro technology offers substantial performance, reliability, integration and per-channel cost advantages
over legacy isolation technologies, such as optocouplers and gate drive transformers. The ISOpro-based
Si823x and Si826x ISOdrivers are single-chip, isolated gate drivers featuring ultra-fast 50 ns propagation
delays for increased timing margins, a dead time generator for higher system efficiency, stable operation
over temperature and time and lower BoM costs and PCB footprints. Supporting output power supplies to
24 V and 0.5 or 4.0 A peak output current, ISOdrivers efficiently drive MOSFET and IGBT power stages in
high-performance, isolated switch mode power supplies. The high-side/low-side versions have built-in
protection against overlap timing errors, ensuring safe and efficient operation. Built-in dead time
configurability allows the SMPS designers to tune their system for peak system efficiency. ISOpro-based
Si860x I2C isolators eliminate secondary-side PMBus communication interface circuitry in networked power
system, saving design time, cost and board area. These devices are complete solutions to the problem of
isolating the I2C interface. The Si860x series operates at data rates useful in networked power systems
where the I2C interfaces on the primary-side controller operate up to 1.7 Mbps. All of the ISOpro products
have the common thread of high-performance, integration and value and are ideal for meeting the
challenges of today’s energy-efficient power delivery systems.
Silicon Laboratories, Inc.
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