Sequential Logic
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Sequential circuits
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

Timing methodologies
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

cascading flip-flops for proper operation
clock skew
Basic registers
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
simple circuits with feedback
latches
edge-triggered flip-flops
shift registers
simple counters
Hardware description languages and sequential logic
Spring 2010
CSE370 - XII - Sequential Logic
1
Sequential versus combinational
A
C
B
clock
Apply fixed inputs A, B
Wait for clock edge and then observe C
Wait for another clock edge and observe C again
Combinational: C will always be the same
Sequential: C may change
Why a clock signal? What is a clock signal?
Spring 2010
CSE370 - XII - Sequential Logic
2
Sequential logic: circuits with feedback

Why feedback?


How else do you remember something?
But what stops values from cycling around endlessly?
X1
X2
•
•
•
Xn
Spring 2010
switching
network
Z1
Z2
•
•
•
Zn
3
CSE370 - XII - Sequential Logic
Simplest circuits with feedback

Two inverters form a static memory cell

will hold value as long as it has power applied
"1"
"stored value"
"0"

How to get a new value into the memory cell?


selectively break feedback path
load new value into cell
"remember"
"data"
Spring 2010
"load"
"stored value"
CSE370 - XII - Sequential Logic
4
Memory with cross-coupled gates
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
Set-Reset register – no clock
Cross-coupled NOR gates

similar to inverter pair, with capability to force output to 0 (reset=1)
or 1 (set=1)
R
S

R
Q
S
Q'
Q
Cross-coupled NAND gates

similar to inverter pair, with capability to force output to 0 (reset=0)
or 1 (set=0)
S'
Q
S'
R'
Q
Q'
R'
Spring 2010
5
CSE370 - XII - Sequential Logic
Timing behavior
Reset
Hold
R
Q
S
Q'
Set
Reset
Set
100
Race
R
S
Q
\Q
Spring 2010
CSE370 - XII - Sequential Logic
6
Clocked Edge-Triggered D-FF
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Basic storage element – sample and hold
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

Samples D on rising clock edge
Outputs this value on Q until the next sample
We won’t worry about how the D flip-flop is implemented

Lots of ways, mostly magic these days
D
Spring 2010
Q
7
CSE370 - XII - Sequential Logic
Edge-triggered flip-flops (cont’d)
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Positive edge-triggered
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inputs sampled on rising edge; outputs change after rising edge
Negative edge-triggered flip-flops
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inputs sampled on falling edge; outputs change after falling edge
100
D
CLK
Qpos
positive edge-triggered FF
Qpos’
Qneg
negative edge-triggered FF
Qneg’
Spring 2010
CSE370 - XII - Sequential Logic
8
Timing methodologies

Rules for interconnecting components and clocks


guarantee proper operation of system when strictly followed
Approach depends on building blocks used for memory elements

we'll focus on systems with edge-triggered flip-flops
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many custom integrated circuits focus on level-sensitive latches
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
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found in programmable logic devices such as our FPGA
smaller, faster a bit more complicated to work with (CSE467)
Basic rules for correct timing:
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
(1) correct inputs, with respect to clock, are provided to the flip-flops
(2) no flip-flop changes state more than once per clocking event
Spring 2010
9
CSE370 - XII - Sequential Logic
Timing methodologies (cont’d)

Definition of terms


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Clock: periodic event, causes state of memory element to change
can be rising edge or falling edge (or high level or low level)
Setup time: minimum time before the clocking event by which the
input must be stable (Tsetup or Tsu)
Hold time: minimum time after the clocking event until which the
input must remain stable (Thold or Th)
Tsu Th
data
D Q
D Q
input
clock
there is a timing "window"
around the clocking event
during which the input must
remain stable and unchanged
in order to be recognized
Spring 2010
clock
stable changing
data
clock
CSE370 - XII - Sequential Logic
10
Typical timing specifications
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Positive edge-triggered D flip-flop



setup and hold times
minimum clock width
propagation delays (low to high, high to low, max and typical)
Tsu T h
180 50
ps ps
Tsu T h
180 50
ps ps
D
TC 5.0 ns
Clk
Tpdhl
110 ps
Tpdlh
360 ps
Q
all measurements are made from the clocking event (the rising edge of the clock)
Spring 2010
11
CSE370 - XII - Sequential Logic
Cascading edge-triggered flip-flops


All registers sample at exactly the same time
Shift register


new value goes into first stage
while previous value of first stage goes into second stage
IN
D Q
Q0
D Q
Q1
OUT
CLK
100
IN
Q0
Q1
CLK
Spring 2010
CSE370 - XII - Sequential Logic
12
Cascading edge-triggered flip-flops (cont’d)

Long path constraint

Tsu + Tp <= Tc
In
Tsu
180ps
Q0
timing constraints
guarantee proper
operation of
cascaded components
Tp
110-360ps
Q1
Tc
assumes infinitely fast
distribution of the clock
CLK
Spring 2010
13
CSE370 - XII - Sequential Logic
Cascading edge-triggered flip-flops (cont’d)

Short path constraint



Tp > Th
propagation delays exceed hold times
this guarantees following stage will latch current value before it
changes to new value
In
Q0
Tp
110-360ps
Tp
110-360ps
Q1
assumes infinitely fast
distribution of the clock
CLK
Th
50ps
Spring 2010
timing constraints
guarantee proper
operation of
cascaded components
Th
50ps
CSE370 - XII - Sequential Logic
14
Cascading edge-triggered flip-flops (cont’d)

Why this works


propagation delays exceed hold times
this guarantees following stage will latch current value before it
changes to new value
In
Tsu
180ps
Tsu
180ps
Q0
Tp
110-360ps
timing constraints
guarantee proper
operation of
cascaded components
Tp
110-360ps
Q1
assumes infinitely fast
distribution of the clock
CLK
Th
50ps
Spring 2010
Th
50ps
15
CSE370 - XII - Sequential Logic
Clock skew

When it doesn’t work



correct behavior assumes next state of all storage elements
determined by all storage elements at the same time
this is difficult in high-performance systems because time for clock
to arrive at flip-flop is comparable to delays through logic
effect of skew on cascaded flip-flops:
100
In
CLK1 is a delayed
version of CLK0
Q0
Q1
CLK0
CLK1
original state: IN = 0, Q0 = 1, Q1 = 1
expected next state: Q0 = 0, Q1 = 1
due to skew, next state becomes: Q0 = 0, Q1 = 0 (0 races through two FFs instead of one)
Spring 2010
CSE370 - XII - Sequential Logic
16
Shift register
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Holds samples of input


store last 4 input values in sequence
4-bit shift register:
OUT1
D Q
IN
OUT2
D Q
OUT3
D Q
OUT4
D Q
CLK
Spring 2010
17
CSE370 - XII - Sequential Logic
Pattern recognizer
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Combinational function of input samples

in this case, recognizing the pattern 1001 on the single input
signal
OUT
OUT1
IN
D Q
OUT2
D Q
OUT3
D Q
OUT4
D Q
CLK
Spring 2010
CSE370 - XII - Sequential Logic
18
Multi-Bit Registers

Collection of 1-bit registers that share the same clock and
controls

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store a binary value
share clock, reset, and set lines
OUT1
OUT2
D Q
OUT3
D Q
D Q
OUT4
D Q
CLK
IN1
Spring 2010
IN2
IN3
CSE370 - XII - Sequential Logic
IN4
19
Register Control
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Reset
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Clear the register to 0
Synchronous – happens on clock edge
Asynchronous – happens immediately
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Set
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Dangerous
Set the register to 1
Synchronous or Asynchronous
Enable
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Register samples input only if enable = 1
aka “load”
Spring 2010
CSE370 - XII - Sequential Logic
20
Simple “Counter”
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Sequences through a fixed set of patterns


in this case, 1000, 0100, 0010, 0001
if one of the patterns is its initial state (by loading or set/reset)
OUT1
IN
D Q
D Q
OUT2
D Q
OUT3
OUT4
D Q
CLK
Spring 2010
21
CSE370 - XII - Sequential Logic
Activity

How does this counter work (assuming it starts in state 0000)?
OUT1
IN
D Q
D Q
OUT2
D Q
OUT3
OUT4
D Q
CLK

Counts through the sequence:


1000, 1100, 1110, 1111, 0111, 0011, 0001, 0000
Known as Mobius (or Johnson) counter
Spring 2010
CSE370 - XII - Sequential Logic
22
Binary counter
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Logic between registers (not just multiplexer)


XOR decides when bit should be toggled
always for low-order bit,
only when first bit is true for second bit,
and so on
OUT1
D Q
OUT2
D Q
OUT3
D Q
OUT4
D Q
CLK
"1"
Spring 2010
23
CSE370 - XII - Sequential Logic
How fast is our counter?

Tc > Tp + TpCL + Tsu
OUT1
D Q
OUT2
DQ
OUT3
D Q
OUT4
DQ
CLK
"1"

Frequency < 1/Tc
Spring 2010
CSE370 - XII - Sequential Logic
24
Counter Controls

Reset – return counter to 0

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
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

Usually Synchronous
Load – start counter at a given value
Enable – counter counts only when enable = 1
Up/Down – count up when 1, count down when 0
etc.
How do you design these?
Spring 2010
25
CSE370 - XII - Sequential Logic
General Synchronous Design

Combinational logic for the “next value” function

Can be a function of inputs, register value or both
inputs
outputs
Combinational
Logic
reg
Spring 2010
CSE370 - XII - Sequential Logic
26
Example: Versatile Shift Register


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Clear
Load – parallel input
Shift Left – serial input/output
Shift Right – serial input/output
Parallel output
Spring 2010
27
CSE370 - XII - Sequential Logic
Shift register application

Parallel-to-serial conversion for serial transmission
parallel outputs
parallel inputs
serial transmission
Spring 2010
CSE370 - XII - Sequential Logic
28