Vbe Current Source
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Projectos de Microelectrónica 06/07 Área Científica de Electrónica DC-DC Basic Blocks Design Microelectrónica LEEC, LEA 2006/2007 Floriberto Lima1 e Marcelino Santos 1 Chipidea, SA Projectos de Microelectrónica 06/07 Table of Contents Introduction........................................................................................................................... .............3 ∆Vbe Current Source...................................................................................................................... ...4 Specifications....................................................................................................................... ..........4 Deliverables.............................................................................................................. .....................4 Band-Gap Voltage Reference........................................................................................................... .6 Specifications....................................................................................................................... ..........6 Deliverables.............................................................................................................. .....................6 1.8V Fast Comparator................................................................................................... ....................8 Specifications....................................................................................................................... ..........8 Deliverables.............................................................................................................. .....................8 Power Good Comparator............................................................................................................... ..10 Specifications...................................................................................................................... .........10 Deliverables............................................................................................................ .....................10 2MHz Current Controlled Oscillator............................................................................................. ....12 Specifications...................................................................................................................... .........12 Deliverables............................................................................................................ .....................12 Power Block.............................................................................................................................. .......14 Specifications...................................................................................................................... .........14 Deliverables............................................................................................................ .....................14 Control Block............................................................................................................ .......................16 Specifications...................................................................................................................... .........16 Deliverables............................................................................................................ .....................16 Projectos de Microelectrónica 06/07 Introduction The seven projects described in this document form a DC-DC converter as shown in the next figure: vlx vin 10uH 6Ω DC Oscillator vfb clk2mhz 1.8V vctrl comparator Control Block swp Power Block Band-gap Power good ibp1ua ibp1ub ibp1uc ibp1ud ibp1ue ibp1uf ibp1ug ibp1uh vbg Currentsource integratedDC-DC pwrgood Each project can be assigned to a maximum of three groups. The best implementation (minimum area respecting specifications) of each block will be incorporated in a DC-DC converter project. Projectos de Microelectrónica 06/07 ∆Vbe Current Source This block is an eight-output, low power bias current generator, which supplies all the blocks in the DC-DC converter. It should include a power down pin “pd” and have maximum total power consumption below 20 uA. Although sub-threshold operation of some transistors is acceptable when dully justified, it should be avoided in the output current mirrors. It is supplied from a single 3.3 V source and all outputs are of the PMOS type. Output pins should be named “ibp1ua” to “ibp1uh”. Specifications PARAMETER Technology Analog Core Area Operating Junction Temperature Supply Voltage Digital Low Digital High Output Current Power Supply Rejection Ratio Startup time Resistor Variation Capacitor Variation SYMBOL COMMENTS Tj Vin VL VH Ibp1ux PSRR Ts ­ ­ Current Consumption All blocks ON IqON All blocks in Power­ IqOFF down MIN ­25 For PD pin For PD pin Per pin To 95% if final Iout In case there is no information In case there is no information TYP ams_035 0.1 +25 MAX UNITS +125 mm2 °C 3.0 0% 80% 0.6 ­ 3.3 ­ ­ 1 ­ 3.7 20% 100% 1.6 0.2 V Vin Vin µA µA /V ­ ­30 ­ ­ 50 30 µs % ­20 ­ 20 % ­ ­ ­ ­ 20 0.1 µA µA Deliverables 1. 2. 3. 4. 5. TAR file with design library (top cell name should be ibias8x1uap) Symbol plot (A4) Schematic plot (A4) Layout plot (A4) Verification report that should include: • Any necessary calculations • Typical op with PD=0 (block ON) • Typical op with PD=1 (block OFF) • Typical startup simulation showing the enable signal and one output current • Typical PSRR simulation showing one output current connected to a 1 V voltage source • Temperature sweep DC simulations with process and operation corners for one output current (here the usage of alters will be of great help) • DRC report • LVS report • Block size information • References used Projectos de Microelectrónica 06/07 Figure 1 shows a possible topology for the basic circuit. Research of alternative solutions is encouraged. Power down control is not included. Figure 1: Current source topology. Projectos de Microelectrónica 06/07 Band-Gap Voltage Reference This block is a medium precision voltage reference for the DC-DC converter. It should include a power down pin “pd” and have total power consumption below 50 uA. Although sub-threshold operation of some transistors is acceptable when dully justified it should be avoided as a rule. It is supplied from a single 3.3V source and uses a 1 uA bias current provided externally. The output pin should be named “vbg”. Specifications PARAMETER Technology Analog Core Area Operating Junction Temperature Supply Voltage Digital Low Digital High Output Voltage Bias Current Power Supply Rejection Ratio External Capacitor External Capacitor ESR Startup time Resistor Variation Capacitor Variation SYMBOL COMMENTS Tj Vin VL VH Vbg Ibp1u PSRR ­25 For PD pin For PD pin 1Hz­1MHz Cout ESR To filter Vbg Ts ­ To 99% if final Vout In case there is no information In case there is no information ­ Current Consumption All blocks ON IqON All blocks in Power­ IqOFF down MIN TYP ams_035 0.15 +25 MAX UNITS +125 mm2 °C 3.0 0% 80% 1.173 0.6 ­ 3.3 ­ ­ 1.235 1 ­ 3.7 20% 100% 1.296 1.6 40 V Vin Vin V µA dB ­ ­ ­ .1 .1 ­ µF Ω ­ ­30 ­ ­ 50 30 µs % ­20 ­ 20 % ­ ­ ­ ­ 50 0.1 µA µA Deliverables 1. 2. 3. 4. 5. TAR file with design library (top cell name should be vbg1v235) Symbol plot (A4) Schematic plot (A4) Layout plot (A4) Verification report that should include: • Any necessary calculations (including an estimation of the offset originated by mismatch on the amplifier transistors) • Typical op with PD=0 (block ON) • Typical op with PD=1 (block OFF) • Typical startup simulation showing the enable signal and the output • Typical PSRR simulation • Temperature sweep DC simulations with process and operation (here the usage of alters will be of great help) • DRC report • LVS report • Block size information • References used Projectos de Microelectrónica 06/07 Figure 2a shows a possible topology for the circuit. Research of alternative solutions is encouraged. Power down control is not included. Figure 2b shows the circuit basic concept. L=4u 4 uA .25 uA 1 uA 1 uA .25 uA 1 uA 1:8 .25 uA L=6u Figure 2a: Band-gap topology. Figure 2b: Band-gap basics. vbg Projectos de Microelectrónica 06/07 1.8V Fast Comparator This block is the Variable Frequency Modulation (VFM) DC-DC control comparator. It is responsible for the DC-DC regulation and should be able to respond in less than 1 us. It should include a power down pin “pd” and have total power consumption below 20 uA. Although subthreshold operation of some transistors is acceptable when dully justified it should be avoided as a rule. It is supplied from a single 3.3 V source, uses a 1 uA bias current and a 1.235 V voltage reference provided externally. The output pin should be named “out” and the input sensing pin “vfb”. Specifications PARAMETER Technology Analog Core Area Operating Junction Temperature Supply Voltage Digital Low Digital High Referene Voltage Bias Current Power Supply Rejection Ratio Response time SYMBOL COMMENTS Tj Vin VL VH Vbg Ibp1u PSRR Tr Startup time Resistor Variation Ts ­ Capacitor Variation ­ Current Consumption All blocks ON IqON All blocks in Power­ IqOFF down MIN ­25 For PD pin For PD pin 1Hz­1MHz; Measured in close loop From vfb 10mV above Vth to vfb 10 mV below To valid output In case there is no information In case there is no information TYP ams_035 0.10 +25 MAX UNITS +125 mm2 °C 3.0 0% 80% 1.173 0.6 ­ 3.3 ­ ­ 1.235 1 ­ 3.7 20% 100% 1.296 1.6 40 V Vin Vin V µA dB ­ ­ 1 µs ­ ­30 ­ ­ 10 30 µs % ­20 ­ 20 % ­ ­ ­ ­ 20 0.1 µA µA Deliverables 1. 2. 3. 4. 5. TAR file with design library (top cell name should be comp1v8) Symbol plot (A4) Schematic plot (A4) Layout plot (A4) Verification report that should include: • Any necessary calculations • Typical op with PD=0 (block ON) • Typical op with PD=1 (block OFF) • Typical startup simulation showing the enable signal and the output • Typical PSRR with the comparator connected as a unitary buffer • Comparison DC sweep simulation with process and operation corners for a typical vbg of 1.235V (here the usage of alters will be of great help) • DRC report • LVS report • Block size information • References used Projectos de Microelectrónica 06/07 Figure 3 shows a possible topology for the circuit. Research of alternative solutions is encouraged. Power down control is not included. vfb vbg 1 uA out Figure 3: Feedback comparator. Projectos de Microelectrónica 06/07 Power Good Comparator This block is the Variable Frequency Modulation (VFM) DC-DC power good comparator. It indicates when the DC-DC has achieved regulation. It should use hysteresis to avoid unstable detections. The two thresholds should be 95 % and 90 % of the expected 1.8 V regulation voltage. It should include a power down pin “pd” and have total power consumption below 5 uA. Sub-threshold operation of some transistors is acceptable when dully justified. It is supplied from a single 3.3 V source, uses a 1 uA bias current and a 1.235 V voltage reference provided externally. The output pin should be named “pwrgood” and the output sensing pin “vfb”. Specifications PARAMETER Technology Analog Core Area Operating Junction Temperature Supply Voltage Digital Low Digital High Referene Voltage Bias Current Power Supply Rejection Ratio Startup time Resistor Variation Capacitor Variation SYMBOL COMMENTS Tj Vin VL VH Vbg Ibp1u PSRR Ts ­ ­ Current Consumption All blocks ON IqON All blocks in Power­ IqOFF down MIN ­25 For PD pin For PD pin 1Hz­1MHz; Measured in close loop To valid output In case there is no information In case there is no information TYP ams_035 0.10 +25 MAX UNITS +125 mm2 °C 3.0 0% 80% 1.173 0.6 ­ 3.3 ­ ­ 1.235 1 ­ 3.7 20% 100% 1.296 1.6 20 V Vin Vin V µA dB ­ ­30 ­ ­ 20 30 µs % ­20 ­ 20 % ­ ­ ­ ­ 5 0.1 µA µA Deliverables 1. 2. 3. 4. 5. TAR file with design library (top cell name should be compok) Symbol plot (A4) Schematic plot (A4) Layout plot (A4) Verification report that should include: • Any necessary calculations • Typical op with PD=0 (block ON) • Typical op with PD=1 (block OFF) • Typical startup simulation showing the enable signal and the output • Typical PSRR with the comparator connected as a unitary buffer • Comparison level DC sweep (up and down) simulation with process and operation corners for a typical vbg of 1.235 V (here the usage of alters will be of great help) • DRC report • LVS report • Block size information • References used Projectos de Microelectrónica 06/07 Figure 4 shows a possible topology for the circuit. Research of alternative solutions is encouraged. Power down control is not included. vfb vbg 1 uA pwrgood Figure 4: Power good topology. Projectos de Microelectrónica 06/07 2MHz Current Controlled Oscillator This block is the clock generator for a DC-DC converter. It generates a 2 MHz clock. It should include a power down pin “pd” and have total power consumption below 10 uA. Sub-threshold operation of some transistors is acceptable when dully justified. It is supplied from a single 3.3 V source, uses a 1 uA bias current provided externally. The output pin should be named “clk2mhz”. The frequency should be controllable via 4 bits to approximately +200 % -50 % to enable recentering the oscillator after characterization. Specifications PARAMETER Technology Analog Core Area Operating Junction Temperature Supply Voltage Digital Low Digital High Output Frequency Bias Current Startup time Resistor Variation Capacitor Variation SYMBOL COMMENTS Tj Vin VL VH Fout Ibp1u Ts ­ ­ Current Consumption All blocks ON IqON All blocks in Power­ IqOFF down MIN ­25 For PD pin For PD pin All corners To valid output In case there is no information In case there is no information TYP ams_035 0.10 +25 MAX UNITS +125 mm2 °C 3.0 0% 80% .75 0.6 ­ ­30 3.3 ­ ­ 2 1 ­ ­ 3.7 20% 100% 3.5 1.6 20 30 V Vin Vin MHz µA µs % ­20 ­ 20 % ­ ­ ­ ­ 10 0.1 µA µA Deliverables 1. 2. 3. 4. 5. TAR file with design library (top cell name should be osc2mhz) Symbol plot (A4) Schematic plot (A4) Layout plot (A4) Verification report that should include: • Any necessary calculations • Typical op with PD=0 (block ON) • Typical op with PD=1 (block OFF) • Typical startup simulation showing the enable signal and the clock signal • Plot of the output frequency-vs-corner (here the usage of alters will be of great help) • DRC report • LVS report • Block size information • References used Projectos de Microelectrónica 06/07 Figure 5 shows a possible topology for the circuit. Research of alternative solutions is encouraged. Power down control is not included. 1 uA clk2mhz Levelconverter Figure 5: Oscilator topology. Projectos de Microelectrónica 06/07 Power Block This block is the DC-DC power block. It is constituted by a high current low RDSon PMOS power device and a driver. The typical RDSon should be below 0.2 Ohm. The drivers should include nonoverlap for the final stage to avoid large shot-trough currents. The power pins should be named “vin” and “vlx”. When the input pin “swp” is “1” the power transistor must be turned “on”. Specifications PARAMETER Technology Analog Core Area Operating Junction Temperature Supply Voltage Digital Low Digital High Rise and fall time Resistor Variation Capacitor Variation SYMBOL COMMENTS Tj Vin VL VH Tr, Tf ­ ­ Current Consumption All blocks in Power­ IqOFF down MIN ­25 For control pin SWP For control pin SWP 10% ­ 90% In case there is no information In case there is no information Leakage current from the power device TYP ams_035 0.40 +25 MAX UNITS +125 mm2 °C 3.0 0% 80% ­ ­30 3.3 ­ ­ ­ ­ 3.7 20% 100% 10 30 V Vin Vin ns % ­20 ­ 20 % ­ ­ 0.1 µA Deliverables 1. 2. 3. 4. 5. TAR file with design library (top cell name should be pwrblock) Symbol plot (A4) Schematic plot (A4) Layout plot (A4) Verification report that should include: • Any necessary calculations including a theoretical estimation of the drivers power consumption with the DC-DC switching at 2 MHz and vin=3.3V. • Typical op with PD=0 (switch ON with 300 mA) • Typical op with PD=1 (switch OFF) • Typical startup simulation showing the coil current and the vlx pin voltage. Use for conditions a Buck DC-DC topology switching at 2 MHz with 50% DC, a 1.8V load, a 10uH coil and a 0.3V Schottcky diode for the free-wheeling diode. • DC sweep of the RDSon (sweep on vin) simulation with process and operation corners • DRC report • LVS report • Block size information • References used Projectos de Microelectrónica 06/07 Figure 6 shows a possible topology for the circuit. Research of alternative solutions for the non-overlap control block is encouraged. vin DC PD swp nonoverlap control integrated powerblock Figure 6: Power block topology. vlx 10uH 6Ω Projectos de Microelectrónica 06/07 Control Block This block is the Variable Frequency Modulation (VFM) Buck DC-DC control. It has eight modes of operation, selectable by three primary inputs (“s2”, “s1” and “s0”). In mode 0 – bypass - (“s2-0” = 000) the “swp” output is controlled directly from the input “test”. In mode 1 – 500 kHz 50% duty pulse generator- (“s2-0”=001) If at the beginning of a switching period the “vctrl” signal is one the output “swp” must be set to “1” during two clock cycles of clk2mhz (pulse width); switching period = four clock cycle of clk2mhz. Otherwise the output signal “swp” should stay at “0”. In mode 2 – 1 MHz 50% duty pulse generator- (“s2-0”=010) Identical to mode 1 but with pulse width = one clock cycle of clk2mhz and switching period = two clock cycles of clk2mhz. In mode 3 – 2 MHz 50% duty pulse generator- (“s2-0”=011) Identical to mode 1 but with pulse width = half clock cycle of clk2mhz and switching period = clock cycle of clk2mhz. In mode 4 – 2 MHz pulse generator- (“s2-0”=100) If at the beginning of a switching period the “vctrl” signal is “0”, the output “swp” must be set to “0” during the next switching period. Otherwise the output signal “swp” should stay at “1”. The switching period is equal to the clk2mhz clock cycle. In mode 5 – 1 MHz pulse generator- (“s2-0”=101) Identical to mode 4 but with switching period = two clock cycles of clk2mhz. In mode 6 – 500 kHz pulse generator- (“s2-0”=110) Identical to mode 4 but with switching period = four clock cycles of clk2mhz. In mode 7 – 500 kHz pulse generator- (“s2-0”=111) Identical to mode 6 but If at the beginning of the clk2mhz clock cycle the “vctrl” signal is “0” and the “swp” is “1”, a new switching period must be started with the output “swp” set to “0”. As in mode 6, the “swp” is also set to “0” if at the beginning of a switching period the “vctrl” signal is “0” and the “swp” is set to “1” only if at the beginning of a switching period the “vctrl” signal is “1”. Specifications PARAMETER Technology Analog Core Area Operating Junction Temperature Supply Voltage Clock Frequency Output Frequency Output Duty­cycle Input Digital Low Input Digital High Output Rise and fall time Resistor Variation Capacitor Variation SYMBOL COMMENTS MIN TYP ams_035 0.1 +25 UNITS +125 mm2 °C Tj ­25 Vin Fclk Fout DC VL VH Tr, Tf 3.0 ­ 0.5 0 0% 80% ­ 3.3 2 ­ ­ ­ ­ ­ 3.7 ­ 2 100 20% 100% 200 V MHz MHz % Vin Vin ps ­30 ­ 30 % ­20 ­ 20 % ­ ­ 10% ­ 90% into 100 fF In case there is no information In case there is no information Deliverables 1. 2. 3. 4. MAX TAR file with design library (top cell name should be ctrlblock) Symbol plot (A4) Schematic plot (A4) Layout plot (A4) Projectos de Microelectrónica 06/07 5. Verification report that should include: • • • • • • • VHDL code VHDL simulation verilog netlist simulation DRC report Extracted logic simulation Typical startup simulation showing the coil current and the vlx pin voltage. Use for conditions a Buck DC-DC topology switching at 2 MHz with 50% DC, a 1.8V load, a 10uH coil and a 0.3V Schottcky diode for the free-wheeling diode. The switch controlled by swp can be modulated by an ideal switch with 0.2 ohm of rdson. References used
