ELEC 3908, Physical Electronics, Lecture 13
Diode Small Signal Modeling
Lecture Outline
• Last few lectures have dealt exclusively with modeling and
important effects in static (dc) operation
• Different modeling strategy required for small signal
operation – linearized perturbation on dc operating point
• Two important parameters considered
– Conductance – derivative of current with respect to potential
– Capacitance – derivative of stored charge with respect to potential
ELEC 3908, Physical Electronics:
Diode Small Signal Modeling
Page 13-2
Review of Small Signal Operation
• Small signal operation refers to the analysis of the
response of a network to a small perturbation
superimposed on a dc bias condition
• Basic assumption about small signal operation is that
signal levels are low enough that the operating point is not
affected, e.g. a 50mV sinusoid on top of a 1V bias point
input
small signal
perturbation
source
dc bias
source
t
ELEC 3908, Physical Electronics:
Diode Small Signal Modeling
Page 13-3
Review of Small Signal Response
•
•
•
If the perturbation is small, the
response of the network will be
approximately linear even if the
dependence on operating point is
nonlinear (analogous to retaining only
the linear term of a Taylor series)
The nature of the response will in
general be a function of operating
point – in the example shown to the
right, the response (in red) at operating
point 1 is different than at point 2
A larger signal swing, for which the
bias point changes, is a switching, or
transient analysis – will consider this
in lecture 14
output
ELEC 3908, Physical Electronics:
Diode Small Signal Modeling
1
2
input
Page 13-4
Small Signal Conductance
•
The rate of change of diode
current with respect to junction
potential is the conductance gD
dI D
q
gD =
=
I S e qVD
dVD nkT
≈
•
•
q
ID
nkT
I D = I S (e qVD
nkT
− 1)
nkT
( mhos)
ID is a strong (exponential)
function of VD, so the slope of
the ID vs VD relationship
changes with VD
Conductance is therefore a
function of operating point
ELEC 3908, Physical Electronics:
Diode Small Signal Modeling
Page 13-5
Example 13.1: Conductance
What potential is required across a diode with IS = 5x10-11 A
and n=1.3 to give a conductance of 10 mmhos? Ignore
parasitic (substrate) resistance.
ELEC 3908, Physical Electronics:
Diode Small Signal Modeling
Page 13-6
Example 13.1: Solution
• The current corresponding to this conductance is
10 x10
−3
1
=
I D → I D = 3.36 x10 − 4 A
0.02586 ⋅ 13
.
• The junction voltage is therefore
nkT ⎛
ID ⎞
VD =
ln ⎜1 + ⎟
q
IS ⎠
⎝
⎛ 336
. x10 − 4 ⎞
∴ VD = 13
. ⋅ 0.02586 ln ⎜1 +
−11 ⎟ = 0.53 V
5 x10 ⎠
⎝
ELEC 3908, Physical Electronics:
Diode Small Signal Modeling
Page 13-7
General Interpretation of Capacitance
• Capacitance is given (equivalently) as either the rate of
change of charge with voltage, or the proportionality
constant between current and the time rate of change of
voltage
dv ( t )
dq( t )
, i( t ) = C
C=
dt
dv ( t )
• The general meaning of capacitance is the requirement to
supply or sink charge to change potential
• An ideal resistor has no capacitance - no q required for ΔV
• A parallel plate structure stores charge, and hence requires
addition or removal of q for ΔV, hence it has a non-zero C
ELEC 3908, Physical Electronics:
Diode Small Signal Modeling
Page 13-8
Capacitance Measurement
•
•
•
In practice, capacitance is
measured by applying a
sinusoidal signal and measuring
v(t)-i(t) phase difference
For illustrative purposes in
devices, view capacitance
measurement as the
characterisation of the q(t)
required to support a small
potential perturbation v(t)
The constant potential V sets
the operating point, and allows
measurement as a function of
operating point
ELEC 3908, Physical Electronics:
Diode Small Signal Modeling
Page 13-9
Physical Origin of Depletion Capacitance
•
The depletion width W is a
function of the applied bias VD
W=
•
•
•
2ε Si ⎛ 1
1 ⎞
+
⎜
⎟ (V − V D )
q ⎝ N A N D ⎠ bi
Changing VD requires a change
in W, and hence ρ
A capacitive effect is therefore
present - the change in ρ must
be supplied in order to change
VD
Since the capacitive effect
arises from the change in
depletion width, it is termed
depletion capacitance
ELEC 3908, Physical Electronics:
Diode Small Signal Modeling
Page 13-10
Analytic Model for Depletion Capacitance
• Determine depletion capacitance using the chain rule
Cˆ dep (VD ) =
dQˆ dep
dVD
dQˆ dep dW
=
dW dVD
• Q associated with the positive VD terminal is –qNAxp, so the
differential charge dq is formed by
dQˆ dep
dW
=
d (− qN A x p )
dW
= − qN A
d
dW
⎛ ND
⎞
N AND
⎜⎜
W ⎟⎟ = − q
N A + ND
⎝ N A + ND ⎠
• (the negative terminal could also be used with qNDxn and a
negative sign since –dq is being found)
ELEC 3908, Physical Electronics:
Diode Small Signal Modeling
Page 13-11
Analytic Model for Depletion Capacitance (con’t)
• The derivative of W with respect to VD is
dW
d
=
dVD dVD
2ε Si
q
⎛ N AND ⎞
1 2ε Si ⎛ N A N D ⎞
⎜⎜
⎟⎟(Vbi − VD ) = −
⎜⎜
⎟⎟
2W q ⎝ N A + N D ⎠
⎝ N A + ND ⎠
• The depletion capacitance is therefore
ˆ dW ⎡
d
Q
N A N D ⎤ ⎡ 1 2ε Si N A + N D ⎤ ε Si
dep
ˆ
Cdep (VD ) =
= ⎢− q
⎥ ⎢−
⎥=
dW dVD ⎣
N A + N D ⎦ ⎣ 2W q N A N D ⎦ W
ELEC 3908, Physical Electronics:
Diode Small Signal Modeling
Page 13-12
Depletion Capacitance - Parallel Plate Analogy
•
The form of the depletion
capacitance expression suggests
an analogy to a parallel plate
structure
ε Si
C$ dep (VD ) =
W (V D )
•
The differential charges dq and
-dq act as charge plates
separated by a width W of
material with permittivity εSi
ELEC 3908, Physical Electronics:
Diode Small Signal Modeling
Page 13-13
Voltage Dependence of Depletion Capacitance
•
•
Unlike a simple parallel plate structure, pn-junction depletion
capacitance is a function of VD through W(VD)
As reverse bias increases, W increases, “plate” separation increases, so
capacitance falls (and vice versa for forward bias)
ELEC 3908, Physical Electronics:
Diode Small Signal Modeling
Page 13-14
Voltage Characteristic of Depletion Capacitance
•
•
•
•
Example plot is for NA=1016,
ND=1017 and AD=(50 μm)2
Depletion capacitance increases
as VD increases since W is
becoming narrower
The zero-bias depletion
capacitance is the value at VD=0
In simple model, depletion
capacitance goes to inf. at VD=Vbi
because W goes to 0. In
practice, the depletion
approximation breaks down at
high bias, so the simple
equation no longer applies
ELEC 3908, Physical Electronics:
Diode Small Signal Modeling
Page 13-15
Example 13.2: Depletion Capacitance Constraint
A well diode is constructed from an implant doping of ND=4x1018 /cm3
and a well doping of NA=1016 /cm3. The 1D area is (100 μm)2. What
bias range is required to ensure that the depletion capacitance does not
exceed 1.5pF? (Diagram below is for reference, essentially a duplicate
of that in the planar diode processing lecture.
ELEC 3908, Physical Electronics:
Diode Small Signal Modeling
Page 13-16
Example 13.2: Solution
• The built-in potential for this device is
⎛ 4 x1018 ⋅ 1016 ⎞
⎟ = 0.85 V
Vbi = 0.02586 ln ⎜⎜
10 2 ⎟
. x10 ) ⎠
⎝ (145
• From the specified maximum capacitance, the minimum W
is (using AD in cm2)
Cdep
ε
= AD Si
W
→
W = (100 x10
)
−4 2
11.7 ⋅ 8.854 x10 −14
= 6.9 x10 − 5 cm
−12
15
. x10
• The corresponding maximum VD (recall plot) is then
W=
2ε Si ⎛ 1
1 ⎞
+
⎜
⎟ (Vbi − VD )
q ⎝ NA ND ⎠
→ VD = −2.8 V
ELEC 3908, Physical Electronics:
Diode Small Signal Modeling
Page 13-17
Example 13.2: Solution (con’t)
• The corresponding value of VD is then
W=
2ε Si ⎛ 1
1 ⎞
+
⎜
⎟ (Vbi − VD )
q ⎝ NA ND ⎠
→ VD = −2.8 V
• If the specified value is the maximum allowable, VD must
be lower than –2.8V
Characteristic generated for different
values, but shows behavior of Cdep as
function of VD
ELEC 3908, Physical Electronics:
Diode Small Signal Modeling
Page 13-18
Grading Coefficient and General Model
• For device modeling, Cdep model written in different form
• First step is to rewrite W(VD) expression
W (V D ) =
2ε Si ⎛ 1
1 ⎞
+
⎜
⎟ (V − V D ) =
q ⎝ N A N D ⎠ bi
2ε Si ⎛ 1
1 ⎞
+
⎜
⎟ (V )
q ⎝ N A N D ⎠ bi
(V
− VD )
V
= W ( 0) 1 − D
Vbi
Vbi
bi
• Then depletion capacitance can be written
C$ dep ( 0)
ε
ε
Si
Si
C$ dep (VD ) =
=
=
1 − VD Vbi
W (VD ) W ( 0) 1 − VD Vbi
• The √ is only valid for a uniform junction - for generality
define the grading coefficient z and write
C$ dep ( 0)
$
Cdep (VD ) =
(1 − V
D
Vbi )
z
ELEC 3908, Physical Electronics:
Diode Small Signal Modeling
Page 13-19
Effect of Grading Coefficient
•
•
•
For most structures the grading
coefficient is between 1/2 and
1/3
The zero bias value is not
affected by the value of z, but
the nature of the voltage
dependence is
Characteristic to the right is for
per unit area zero bias depletion
capacitance of 10-8 F/cm2,
Vbi=0.8 and area 75 μm2
ELEC 3908, Physical Electronics:
Diode Small Signal Modeling
Page 13-20
Diode Small Signal Equivalent Circuit
•
•
•
•
A small signal equivalent
circuit can be defined for the
purpose of determining the
response to a small signal
perturbation
The conductance and
capacitance appear in parallel
because both arise from the
fundamental junction operation
Note that the capacitance is
Cdep, not per unit area
A parasitic (substrate)
resistance would appear in
series with this equiv. cct.
ELEC 3908, Physical Electronics:
Diode Small Signal Modeling
Page 13-21
Lecture Summary
• Small signal equivalent circuit includes
– Conductance – models low frequency current perturbation in
response to voltage perturbation
– Capacitance – models charge storage, and introduces frequency
dependent impedance
• Diode exhibits depletion capacitance – associated with a
parallel plate-like structure formed by conductive neutral
regions on either side of depletion region
• Conductance and depletion capacitance are functions of
bias, so the small signal equivalent circuit has to be
constructed for a particular device from the bias point
ELEC 3908, Physical Electronics:
Diode Small Signal Modeling
Page 13-22