Lecture #25
Midterm #2 Information
• Date: Monday November 3rd
• Topics to be covered:
–
–
–
–
–
capacitors and inductors
1st-order circuits (transient response)
semiconductor material properties
pn junctions & their applications
MOSFETs; common-source amplifier
• Review session: Friday October 31st 2-4 PM
OUTLINE
– The transconductance amplifier
(from Howe & Sodini Chapter 8.1)
– Summary of MOSFET
EECS40, Fall 2003
Lecture 25, Slide 1
Prof. King
Amplifier Types
1. Voltage amplifier
v
+
input & output signals are voltages in−
2. Current amplifier
amplifier
iin
input and output signals are currents
+
vout
−
iout
amplifier
3. Transconductance amplifier
input signal is voltage;
output signal is current
4. Transresistance amplifier
input signal is current;
output signal is voltage
EECS40, Fall 2003
Lecture 25, Slide 2
+
vin
−
iout
amplifier
iin
amplifier
+
vout
−
Prof. King
1
Two-Port Amplifier Model
for a transconductance amplifier
iout
+
vin
gmvin
Rin
Rout
−
EECS40, Fall 2003
Lecture 25, Slide 3
Prof. King
Effect of Source and Load Resistances
Rs
iout
+
vs
+
–
vin
Rin
gmvin
Rout
RL
−
• Overall transconductance is degraded by the
source resistance Rs and load resistance RL
iout  Rin   Rout
gm 
=
vs  Rin + Rs   RL + Rout
EECS40, Fall 2003
Lecture 25, Slide 4



Prof. King
2
NMOSFET Summary: Current Flow
NMOSFET Circuit Symbol
NMOSFET Structure
iG
iS
n+ poly-Si
n+
n+
vG
S
iD
−
S
p-type Si
iB
Gate current iG = 0
Body current iB = 0
Æ iS = −iD
EECS40, Fall 2003
+ G
− vDS +
D
If VGS ≤ VT, iD = 0
If VGS > VT, iD > 0
Current is limited by either
• the resistance of the
inversion-charge layer, or
• velocity saturation
Lecture 25, Slide 5
Prof. King
NMOSFET Summary: Modes of Operation
• When VGS ≤ VT, an n-type channel is not formed.
Æ No electrons flow from SOURCE to DRAIN
“CUTOFF mode”
• When VGS > VT, an n-type channel (“inversion” layer of
electrons at the surface of the semiconductor) is formed.
Æ Electrons may flow from SOURCE to DRAIN (iD > 0)
If VDS < VGS–VT, the inversion layer exists across the
entire channel length, and current iD increases with VDS
“LINEAR mode” or “TRIODE mode”
If VDS ≥ VGS–VT, the inversion layer is pinched off at the
drain end, and current iD does not increase with VDS
“SATURATION mode”
EECS40, Fall 2003
Lecture 25, Slide 6
Prof. King
3
NMOSFET Summary: I-V Characteristics
iD
n+
n+
p
“LINEAR”
or
“TRIODE”
n+
p
n+
“SATURATION”
vGS = VG3 > VG2
vDS = vGS–VT ≡ VDSAT
n+
p
vGS = VG2 > VG1
n+
0
vGS = VG1 > VT
vDS
“CUTOFF”
( vGS ≤ VT )
EECS40, Fall 2003
n+
p
n+
Lecture 25, Slide 7
Prof. King
NMOSFET Summary: I-V Equations
“LINEAR” or “TRIODE”
I D = k n′
W
L
“SATURATION”
VDS 

V
V
VDS
−
−
T
 GS
2 

iD
I DSAT =
k n′ W
(VGS − VT )2
2 L
vDS = vGS–VT ≡ VDSAT
vGS > VT
vDS
0
EECS40, Fall 2003
Lecture 25, Slide 8
Prof. King
4
PMOSFET I-V Equations
iD
0 v
DS
|vGS| > |VTp|
vDS = vGS–VT ≡ VDSAT
“LINEAR” or “TRIODE”
“SATURATION”
I DSAT = −
k ′p W
(VGS − VTp )2
2 L
EECS40, Fall 2003
I D = −k ′p
W
L
VDS 

VGS − VTp − 2 VDS


Lecture 25, Slide 9
Prof. King
NMOSFET Summary: Non-Ideal Behavior
Channel-length modulation:
•
The length of the pinch-off region, ∆L, increases with
increasing VDS above VGS–VT. It reduces the length of
the inversion layer and hence the resistance of this layer.
cross-sectional
view of channel:
inversion layer
→ iD increases noticeably with VDS, if L is small
λ is the slope
(channel-length
modulation parameter)
iD
0
EECS40, Fall 2003
VDSAT
Lecture 25, Slide 10
vDS
Prof. King
5
(continued)
Velocity Saturation:
•
In a very-short-channel MOSFET, iD saturates because
the carrier velocity is limited to ~107 cm/sec
Æ iD reaches a limit before pinch-off occurs
V


I DSAT = WCox VGS − VT − DSAT  vsat
2 

L
where VDSAT =
vsat < VGS–VT
µn
EECS40, Fall 2003
Lecture 25, Slide 11
Prof. King
(continued)
Subthreshold Leakage:
• For VGS ≤ VT, iD is exponentially dependent on VGS:
log iDS
1/S is the slope
leakage current, IOFF
0
VT
vGS
• The leakage current specification sets the lower limit for
the threshold voltage VT
EECS40, Fall 2003
Lecture 25, Slide 12
Prof. King
6
NMOSFET Summary: Circuit Models
• For analog circuit applications (where we are concerned
only with changes in current and voltage signals, rather
than their total values), the small-signal model is used:
G
id
+
gmvgs
vgs
1/go
−
S
D
S
transconductance
output conductance
W
kn′ (VGS − VT )
L
go ≅ λI D where VGS & ID are the
gm ≅
DC bias (Q point) values
EECS40, Fall 2003
Lecture 25, Slide 13
Prof. King
NMOSFET Summary: Circuit Models
• For digital circuit applications, the MOSFET is modeled
as a resistive switch:
Req
iD
charges,
As the load capacitor dis
V
0
to
ses
VDS decrea
e≅
slop
0
V DD
/ I DS A T
VDD/2
Req ≅
3 VDD  5

1 − λnVDD 
4 I DSATn  6

I DSATn =
kn′ W
(VDD − VTn )2
2 L
MOSFET is turned on
(VGS = VDD) when VDS = VDD
VDD
vDS
slope ≅ VDD / 2 IDSAT
EECS40, Fall 2003
Lecture 25, Slide 14
Prof. King
7