Ultra Shallow Junction Formation Technology and Trends
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Front End Products Group Equipment Supplier’s Perspective on the Evolution of Si Technology Development Gregg S. Higashi, Ph.D. CTO & Co-Director of the Applications Development Center Front End Products Group May 2005 Applied Materials External Use Front End Products Group 2 1998: Unit Process Physical Results RTP’98 Applied Materials External Use Front End Products Group 3 2003: Transistor Electrical Results Low-energy Nitrogen Plasmas for 65-nm node Oxynitride Gate Dielectrics: A Correlation of Plasma Characteristics and Device Parameters P.A. Kraus1, K. Ahmed1, T.C. Chua1, M. Ershov2, H. Karbasi2, C.S. Olsen1, F. Nouri1, J. Holland1, R. Zhao1, G. Miner1 and A. Lepert1 1 Applied Materials, Inc., Santa Clara, CA, U.S.A. 2 PDF Solutions, Inc., San Jose, CA, U.S.A. Phone 408-563-6363, Fax 408-563-4884, E-mail philip_kraus@amat.com Abstract Norm. Electron Density (a.u.) Ultra-thin oxynitride gate dielectrics (EOT 1.1 to 1.2 nm) have been prepared using quasi-remote inductively coupled nitrogen plasmas. A correlation has been established, for the first time, between device characteristics and measurements of the nitrogen plasma characteristics. It is found that reducing the density of high-energy electrons in the plasma results in 5% improved electron and hole low-field mobilities and 100% improved NBTI reliability. These improvements in plasma nitridation technology enable the extension of oxynitride gate dielectrics to the 65-nm technology node specifications. (Keywords: plasma nitridation, oxynitride gate dielectric, 1.0 electron temperature, effective carrier mobility, NBTI) 1750 5 mT 0.8 pRF CW 1700 Vg= -1.6V dIdsat (%) nMOS Gmax*Tinv (a.u.) 10 Introduction It is likely that0.6fundamental and integration difficulties will prevent high-κ dielectrics from becoming adopted for 65-nm nodeT=105C CMOS manufacturing [1]. It is therefore 1650 necessary to extend plasma nitridation to the 65-nm node, as has been recently reported [2-5]. Gate leakage and EOT specifications will require superior N profile pRF 1600 0.4 control in the gate dielectric because effective carrier mobility and NBTI lifetime can be degraded with increasing N concentrations or proximity of N to the channel [2Vg= -1.2V 20 mT 1550 6]. Minimizing these degradations is then a requirement for advanced gate oxide nitridation processes. 0.2 + Fig. 1 is a simulation of N2 ion implantation into 1 nm of SiO2 on Si at ionpRF energies of 10, 20, and 30 eV; both N profile1and the amount of N implanted into the Si 1500 CW channel are dependent on the ion energy. While this simulation does CW not take into account chemistry or diffusion, it illustrates the importance of the ion 0.0 1450 0 200 400formation. 600 800 kinetic energy in gate dielectric An ion striking the surface of the wafer has kinetic energy proportional to the electron temperature (kTe), which describes 10 12 14 16 Effective Power (W) the Maxwellian distribution of electron energies in the plasma [7]. A reduction in kTe will cause a reduction in the mean energy of the nitrogen ions (Eion) striking the Nitrogen Concentration (at. %) Stress time (a.u.) wafer surface. Simulations pulsed (turning the source power on Nitrogen and off at kHz content frequencies) Ar plasmas have been shown to have reduced condition time-averaged kT Plasma impact Plasmaofelectron impact e relative to continuous wave (non-pulsed) plasmas [8]. Here, we report for the first time the use of pulsed nitrogen plasmas for an abrupt N profile and hence improved n- and on device NBTI energy vs. Power on channel mobility pMOS device performance and reliability, and the characterization of these plasmas. VLSI’03 Measurements show Pulsed RF Plasma reduces electron temperature. Improved device performance and NBTI Applied Materials External Use Front End Products Group 4 IBM says, “Classical CMOS Scaling is Dead” 1000 Scaled Device Voltage, V / α WIRING T ox (C ) 100 tox/α W/α GATE n+ source n+ drain 10 classic scaling L/α p substrate, doping α*NA Vdd (V) xd/α 1 RESULTS: SCALING: Higher Density: Scaling factor: α Higher Speed: Voltage: V/α Oxide: tox /α Power/ckt: Power Density: Wire width: W/α Gate width: L/α Diffusion: xd /α Substrate: α * NA ~α2 ~α ~1/α2 ~Constant 0.1 0.01 Vt (V) 0.1 1 Gate Length, Lgate (um) Why deviate from "ideal" scaling? • unacceptable gate leakage/reliability • additional performance at higher voltages B. Meyerson, IBM, Semico Conf., January 2004, Taiwan. What‘s the consequence of this deviation? • a dramatic rise in power density Applied Materials External Use Front End Products Group 5 IBM says, “There’s a Power Crisis in CMOS” 1E+03 Active Power Density 1E+02 Power (W/cm2) Leff and Vdd trends result in: • Active Power Density growth ~1.3X/generation • Passive Power Density growth ~3X/generation • Gate Leakage Power Density >4X/generation` 1E+01 1E+00 1E-01 1E-02 1E-03 1E-04 1E-05 0.01 Standby Power Density 0.1 Gate Length (µm) The CMOS Power Crisis: Simple scaling is no longer an option, as we have hit a “power cliff” B. Meyerson, IBM, Semico Conf., January 2004, Taiwan. Applied Materials External Use 1 Front End Products Group 6 Implications of Power Crisis New materials will be introduced – Plasma Nitrided Gate Dielectric – High-k Gate Dielectric – Metal Gate New processes will be introduced – Co-implantation of species to suppress diffusion – Diffusion free annealing processes – High-tilt high current implantation Processed induced strained silicon will be adopted – SiN overlayers – Recessed SiGe source/drain extensions Applied Materials External Use Front End Products Group 7 Gate Stack Opportunities Applied Materials External Use Front End Products Group 8 More Detailed Look at Gate Stack Gate Stack Bias Causes: Inversion layer to form in Si under the gate oxide. Small depletion layer to form in poly-Si electrode Gate EOT CET or Tox Inversion Well Capacitance Equivalent Thickness (CET): Capacitance in inversion is the true metric governing device performance. Q = CV This inversion capacitance translated into equivalent oxide thickness as CET or Tox inversion. CET/Tox Inversion Governs Transistor Drive Current Applied Materials External Use Front End Products Group 9 Gate Capacitor Considerations C = kε0A/t k = dielectric constant ε0 = permittivity of free space A = capacitor area t = thickness of capacitor 1/Cinversion = 1/Cdielectric + 1/Cinversion layer + 1/Cpoly depletion Assuming equal k’s: CET = EOT + tinversion layer + tpoly depletion CET Jg-reduction tdielectric EOT tinv. layer tpoly depl. Technology 20Å 1x 12Å 12Å 4Å 4Å Oxide/Poly 20Å 10x 12Å 12Å 4Å 4Å Oxinitride/Poly 20Å 10,000x 30Å 12Å 4Å 4Å Hi-k/Poly 16Å 10,000x 30Å 12Å 4Å 0Å Hi-k/Metal Gate Industry driving toward high-k and metal gates Applied Materials External Use Front End Products Group 10 Plasma Nitrided Gate Stack: Scaling to 65nm 1,000 Jg atVg=1v (A/cm2) 65nm HP Req 100 High Performance 10 SiO2 1 65nm LOP Req RTNO Low Operating Power 0 0.1xSiO2 0 10 12 14 16 18 EOT (Å) DPN gate nitridation meets 65nm HP and LOP device requirements. Applied Materials External Use Front End Products Group 11 Gate Dielectric Leakage Reduction with High-k/Metal Gate ITRS Roadmap 45nm EOT (Å) 8 Poly depletion + QM (Å) 4 Gate Leakage (A/cm2) 2,000 Gate Leakage Reduction 1e+5 1e+4 Device Cross-Section SiO2 1e+3 Jg(Vg=Vfb-1) (A/cm2) Poly D HfSiOx (40Å) 1e+2 1e+1 1e+0 1e-1 1e-2 1e-3 1e-4 Process B Process A 1e-5 Si 1e-6 Gate: Ta/TaN 1e-7 5 6 7 8 9 Applied Materials External Use 10 11 EOT 12 13 14 15 Front End Products Group 12 45nm Gate Stack Technology Landscape Substrate Gate Stack Structure Surface Channel Bulk PD-SOI Dielec. WF Requirement Materials P+: W, Ru, IrO2, TiAlN N+: Ta/Si/N, Al SiON or HiK Band Edge Dual metal ~ N+ & P+ Buried Channel Alloy:Ti/N, Ta/N, TaSiN Silicide: NiSi, CoSi SOI FD-SOI SiON or HiK FinFET TriGate Applied Materials External Use MidGap Dual metal ~ mid gap Front End Products Group 13 Ultra-Shallow Junction Applied Materials External Use Front End Products Group 14 Device Scaling and Doping Drivers Key Parameters for Transistor Improvement • Speed: Ion/Idsat : Increase Resistance : Rs : Decrease Higher Doses Higher Anneal Temp. • Leakage: Ioff : Reduce Junction Depth: Xj : Decrease Lower Implant Energies Shorter Anneal Time Gate Length: Requirement = smaller Physical gate length. Typically, Lg is smaller than design rule (technology node). Lg Contact/Extension/Channel Resistance: Requirement = lower Reducing resistance in Contact/Extension/Channel path Increases conductance and raises switching speed Gate Source Ext Ext Xj EOT Drain Lch Channel Length: Requirement = smaller Effective gate length, which is smaller than Lg. Junction Depth: Requirement = shallower As channel length decreases, electric field interaction results in leakage from Drain to Source when transistor is Off (Short Channel Effect – SCE). Shallower Xj reduces SCE leakage Scaling Challenges Implant and Anneal Systems Applied Materials External Use Front End Products Group 15 Technology Curve for Current PTORs and Process Boron TED is a 10000 limiting factor to USJ formation of B in Si and fast diffusion of B must be overcome Shallow and Abrupt implant profiles required Productivity is challenge for USJ doping - lower energies - higher doses - additional implants Sheet Resistance (ohms/sq) Solid solubility limit Low Energy Implant and Spike Anneal 1000 65nm 90nm 130nm Need to push to lower Xj/Rs to meet requirements 100 0 100 200 300 400 500 Junction Depth (A) Current Generation tools and typical low energy implant/spike anneal process do not meet ITRS requirements Applied Materials External Use 600 Front End Products Group 16 Technology Curves for Shallow Junctions Key Metrics/trend 10000 Challenges Implant Productivity Minimizing diffusion during activation step Sheet Resistance (ohms/sq) Xj Rs Abruptness Quantum/Radiance 1000 65nm 90nm Quantum III and Radiance Plus with LE Ge PAI and F 130nm Overlap formation without diffusion Channel Strain Tailoring 100 0 100 200 300 400 500 Junction Depth (A) Process and hardware improvements extend Quantum and Radiance to 90nm Applied Materials External Use 600 Front End Products Group 17 65nm USJ: Carbon Co-Implant + Spike Anneal Partnership with IMEC SIMS B 0.5KeV 7E14 cm-2 1E+21 D03: Ge+F+B D12: Ge+C+B D04: Si+F+B D14: Si+C+B Concentration (cm-3) D09: C+B 1E+20 D05: In+B 1E+19 In Si+C Ge+C C Ge+F Si+F 1E+18 0 5 10 15 20 25 30 35 40 45 50 Depth (nm) Junction depth and abruptness improved with C co-implant Quantum X + RadiancePlus extend to meet customers’ 65nm requirements. Applied Materials External Use Front End Products Group 18 Millisecond Anneal Capability for 65nm USJ 10000 1E+22 Millisec Anneal 500 Ω/sq. Rs (Ω/sq) Radiance Spike Anneal Millisec Anneal 1E+21 [B] Higher Activation -3 (cm ) 1E+20 1000 ITRS 45nm ITRS ITRS 65nm 90nm 1E+19 1E+18 Reduced Diffusion As Implanted Ge 5keV, 1E15/cm2 B 0.5keV, 1E15/cm2 0 100 100 Radiance 1050°C Spike 380 Ω/sq. 200 300 400 Depth (Å) 50 150 250 350 450 550 Xj @ 1E18 /cm3 (Å) Tech. Node 90nm Rs <660Ω/sq Xj <250Å Abruptness 4.1nm/dec Technology Spike spike 65nm 45nm 30nm <760Ω/sq <170Å 2.8nm/dec 830Ω/sq <100Å 2.0nm/dec 940Ω/sq <70Å 1.4nm/dec transition Advanced Advanced Advanced Annealing Potential: Preserves as-implanted profile with <25Å diffusion High activation due to peak temp ~1200°C High throughput (>40 wph/chamber) Lower total power required than Radiance Activation without Diffusion will extend USJ to the 45nm node Applied Materials External Use Front End Products Group 19 Technology Curves for Shallow Junctions Key Metrics/trend 10000 Challenges Implant Productivity Minimizing diffusion during activation step Sheet Resistance (ohms/sq) XJ Rs Abruptness Quantum/Radiance Quantum X and Advanced Anneal 1000 65nm 90nm Overlap formation without diffusion Channel Strain Tailoring Quantum III and Radiance Plus with F co-implant 130nm Quantum X and Radiance Plus with C co-implant 100 0 100 200 300 400 500 Junction Depth (A) Process and hardware improvements extend Quantum and Radiance to 90nm New technology development enables Xj/Rs scaling to continue Applied Materials External Use 600 Front End Products Group 20 Strained Silicon Applied Materials External Use Front End Products Group 21 Applied Materials Suite of Stress Inducing Films Spacer Offsets/Oxide/ Nitride PMD 3 3 Stress Inducing Nitride 4 4 Ni Silicide Ni Silicide Si1-x Gexx 1-x Strained Si Channel MDD MDD // Halo Halo & & Retrograde Well Retrograde Well Heavily Heavily Doped Doped Substrate Substrate 1. 2. 3. 4. 5. PMD 1&2 Source Source 5 5 Stress Inducing Nitride Gate Unlanded Contact Shallow Trench Isolation Pre-Metal Dielectric (PMD) Tensile Silicon Nitride (NMOS) Compressive Silicon Nitride (PMOS) Tensile - HARP PMD Tensile - HARP STI Selective Epitaxial Silicon Germanium APPLIED MATERIALS CONFIDENTIAL/INTERNAL USE ONLY Applied Materials External Use Ni Silicide Drain Drain Si1-x Gexx 1-x Front End Products Group 22 High Stress Nitride for NMOS/PMOS Ion-Ioff (IBM, 2003) Low tensile stress NMOS High tensile stress Low tensile stress PMOS 90nm 90nm MOSFET, MOSFET, Tensile Tensile stress stress 1.4GPa 1.4GPa in in etch etch stop stop (Conventional (Conventional <0.7Gpa) <0.7Gpa) High Stress SiN High tensile stress Better Better NMOS NMOS performance performance (8%) (8%) and and no no PMOS PMOS degradation. degradation. Optimized Optimized strain strain engineering engineering enabling enabling high high performance performance NMOS NMOS with with no no impact impact on on PMOS PMOS performance performance with with minimum minimum manufacturing manufacturing complexity. complexity. Ref.: V. Chan et al, “High speed 45nm Gate Length CMOSFETs Integrated Into a 90nm Bulk Technology Incorporating Strain Engineering,” IBM Microelectronics (SRDC), IEDM 2003, Washington DC. Applied Materials External Use Front End Products Group 23 Strain Engineering for High Performance Logic NMOS PMOS TEM of PMOS device where SiGe in the source/drain areas are used to induce compressive stress in the Si channel (25% improvement in Idsat) Ref.: T. Ghani et al, “A 90 nm High Volume Manufacturing Logic Technology Featuring Novel TEM of 45 nm gate length device using SiN in tensile stress to improve NMOS drive current (10% improvement in Idsat)) 45nm Gate Length Strained Silicon CMOS Transistors,” Intel Corp., IEDM 2003, Washington, D. C. Intel uses both SiN overlayer and SiGe recessed S/D for strained Si Applied Materials External Use Front End Products Group 24 Modeling Localized Strain 1.8 GPa compressive stress in SiGe S/D Compressive stress in channel 1.2 GPa tensile stress in cap layer Tensile stress in channel 800 MPa tensile stress in silicide Compressive stress in channel Simulations courtesy of Synopsys JDP with Synopsys provides understanding for process optimization Applied Materials External Use Front End Products Group 25 10 -5 10 10 10 10 e r -6 S/D Elevation = e/r -7 A 0 elev B 40nm elev C 60nm elev Ref -8 -9 150 250 350 450 550 On-state current [µA/µm] Applied/IMEC/Synopsys Collaboration Channel Stress Change (%) Off-state current [A/µm] Elevation improves device performance 50 40 30 20 10 0 0 25 50 75 100 S/D Elevation (%) S/D elevation improves drive current but the effect saturates at ~40nm Applied Materials External Use Front End Products Group 26 Recent Recessed SiGe IMEC Transistor Data Off-state Current [A/µm] 1.E-03 1.E-04 30% Ion Improvement ~60% Ion improvement at 40nA SiGe SiGe 1.E-05 1.E-06 60% Ion Improvement 1.E-07 Ref Depth V2 1.E-08 SiGe SiGe 1.E-09 100 200 300 400 500 600 700 On-state Current [uA/µm] Applied/IMEC/Synopsys Collaboration 60% drive current improvement demonstrated with 120nm recessed etch. Applied Materials External Use Front End Products Group 27 AMAT/IMEC/Synopsys Strained Si IEDM 2004 Paper Leading Development on Recessed S/D Strained SiGe Applied Materials External Use Front End Products Group 28 nMOS and pMOS stress contours pMOS Geometry nMOS Geometry Includes stress from tesile STI and tensile ESL Includes stress form tensile STI, SiGe and compressive ESL Courtesy of Synopsys Applied Materials External Use
