How far can we push Si CMOS?
What lies beyond?
Prof. Krishna Saraswat
Department of Electrical Engineering
Stanford University
Stanford, CA 94305
saraswat@stanford.edu
araswat
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tanford University
Saraswat - EE311/Future Devices
Physical Limits in Scaling Si MOSFET
Gate stack
• Tunneling current ⇒ ⇑ Ioff
• Gate depletion ⇒ ⇑ EOT
Source/Drain
• Parasitic resistance
• Doping level, abruptness
Gate
Source
Drain
Power ⇑
• CV2f ⇑
• S/D leakage current ⇑
• Gate leakage current ⇑
Substrat
e
Channel/Drain
•
•
•
•
•
Surface scattering - mobility ⇓
High E-field - mobility ⇓
DIBL ⇒ drain to source leakage ⇑ Ioff
Subthreshold slope ≥ kT/q ⇒ ⇑ Ioff
VG - VT decrease ⇒ ⇓ ION
Net result: Bulk-Si CMOS device performance increase commensurate with
size scaling is unlikely beyond the 65 nm node
araswat
tanford University
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Bulk-Si Performance Trends
10
Relative Performance
10
MOSFET in Bulk Si
Conventional Bulk CMOS
1.0
Predictions
(Bulk)
ITRS
1
IEDM Benchmark
Technologies
Novel
Device
Structures
0.1
1985
1990
Technology Node
0.1
1985
1990
1995
2000
1995
Physical Gate Length

2005
2010
2015
2000
130nm
2005
80nm
2010
45nm
2015
22nm
90nm
32nm
18nm
9nm
Maintaining historical CMOS performance trend requires new
semiconductor material and structures by 2008-2010…
 Earlier
araswat
if current bulk-Si data do not improve significantly
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Nanotechnology Eras
0.1
100
65 nm
Generation
45 nm
32 nm
LGATE
22 nm
16 nm
11 nm
micron 0.01
Evolutionary
CMOS
0.001
2000
Revolutionary
Exotic
CMOS
2010
Reasonably
Familiar
Nanotubes
Nanowires
1
2020
Really
Different
Source: Mark Bohr, Intel
araswat
tanford University
10 nm
8 nm
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Extending CMOS
• Novel transistor structures and materials
integration can extend commensurate CMOS
scaling beyond planar bulk-Si solutions:
– Improved Electrostatics and Contacts
• Double-gate or surround-gate
• Schottky source/drain
– Improved Materials Properties
• High mobility materials (e.g. strained Si/SiGe/Ge, etc.)
• Extended CMOS functionality via new
Integration Technologies
• 3-D Integration (Billions of transistors on a chip)
• Exploration of new frontier devices
– Alternatives compatible with silicon
araswat
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tanford University
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New Structures and Materials for
Nanoscale MOSFETs
CURRENT BULK MOSFET
4
5
3
4
Problem 1: Poor Electrostatics ⇒ increased Ioff
Solution: Double Gate
- Retain gate control over channel
- Minimize OFF-state drain-source leakage
Problem 2: Poor Channel Transport ⇒ decreased Ion
2
1
Solution - High Mobility Channel
- High mobility/injection velocity
- High drive current and low intrinsic delay
Problem 3: S/D Parasitic resistance ⇒ decreased Ion
High ION
Low IOFF
FUTURE MOSFET
Top Gate
Schottky
Source
High µ
channel
Schottky
Drain
Bottom Gate
High-K
dielectric
Solution - Metal Schottky S/D
- Reduced extrinsic resistance
Problem 4. Gate leakage increased
Solution - High-K dielectrics
- Reduced gate leakage
Problem 5. Gate depletion ⇒ increased EOT
Solution - Metal gate
- High drive current
araswat
tanford University
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Evolution of MOSFET Structures
Partially Depleted SOI
Bulk
G
G
S
D
D
S
• Device design translates well between
bulk and PD SOI
• e.g. short channel effect control by
doping/halo (same as bulk)
• Reduced junction capacitances
• Dynamic floating body effect - parasitic
bipolar
Ref: Philip Wong, IEDM Short Course, 1999
araswat
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tanford University
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Evolution of MOSFET Structures
Partially Depleted SOI
Ultra-Thin Body Single Gate SOI
Gate
Source
SOI
SiO2
Drain
Si
TBOX
Silicon Substrate
Advantages of Ultra-Thin Body SOI
• Depleted channel ⇒ no conduction
path is far from the gate
• Short channel effects controlled by
geometry
• Steeper subthreshold slope
• Lower or no channel doping
- Higher mobility
- Reduced dopant fluctuation
araswat
tanford University
Ultra-Thin Body Double
Gate SOI
Source
Tox
Gate 1
Vg
SOI
Drain
Si
Gate 2
Ref: Philip Wong, IEDM Short Course, 1999
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Fully Depleted SOI FET
J. Chen et al., Symp. VLSI Tech., 1999.
araswat
tanford University
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Ultra-Thin Body Single vs. Double Gate SOI
• Can be used as a second gate
• Not the ideal structure for double gate
H.-S. P. Wong, et al., p. 407, IEDM 1998.
• In DG MOS better electrostatic control of the channel
⇒ Reduced short channel effects
Wong, et al. IEDM 1998
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tanford University
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Double-Gate FET
• ~2X current drive for the same device width
• Very thin (5 nm) undoped channel ⇒ better electrostatic control
Steeper subthreshold slope - approaching 60 mV/dec
Short-channel effect control feasible down to 20 nm
May tolerate a thicker gate oxide for the same channel length
• Gate workfunction tuning needed for Vt control (for undoped channel)
• Steep lateral source/drain doping profile is required
• Parasitic source resistance
Source/drain fan-out and contact - an integral part of the device
structure
Depletion regions
G
S
D
OFF
G
Channels at the surface
G
D
S
ON
G
Channel length (nm)
araswat
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Effect of Extrinsic Resistance on Double Gate FETs
R
R
s
d
Id = K⋅
K⋅(Vg–Vth–IdRs)α
• Ultrathin body ⇒ higher series resistance
• More severe effect in Double-Gate FET
– Twice Id flows through same Rs ⇒ higher series drop
• Degradation in ION
• Need to reduce parasitic resistance
araswat
tanford University
Shenoy and Saraswat, IEEE Trans. Nanotechnology, Dec. 2003
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Effect of Extrinsic Resistance on Double Gate MOSFETs
SCE
Series Resistance
1.E+21
GATE
Net Doping (cm-3)
1.E+20
1.E+19
1.E+18
1.E+17
Doping
gradient
1.E+16
5nm/dec
4nm/dec
3nm/dec
2nm/dec
1nm/dec
0.5nm/dec
1.E+15
1.E+14
1.E+13
40
45
50
55
60
65
x (nm)
• Extrinsic resistance reduces gate overdrive ⇒ performance limiter in ballistic FETs
• Doping profile too gradual: ⇒ dopants spill into channel ⇒ worse SCE
• Doping profile too abrupt: ⇒ large series resistance in extension tip
• Extrinsic (S/D) resistance may limit performance in future ultrathin body DGFETs
araswat
Shenoy and Saraswat, IEEE Trans. Nanotechnology, Dec. 2003
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Non Planar MOSFETs
Vertical FET
Tri Gate FET
Double Gate FinFET
Gate
Channel
Drain
Source
SiO 2
Gate
Source
Stanford, AT&T
UC Berkeley
Drain
Intel
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tanford University
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Why Germanium MOS Transistors?
Electronic Properties:
• More symmetric and higher
carrier mobilities (low-field)
⇒ More efficient source
injection
Ge
(due to lighter m*)
⇒ ↓ CMOS gate delay
• Smaller energy bandgap
Si
⇒ Survives VDD scaling
⇒ ↓ R with ↓ barrier height
• Lower temperature
processing
(Sze, Phys. of Semicond. Devs. 2nd Ed., p.46,
1981)
⇒ 3-D compatible
araswat
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CMOS Performance Boost with Ge
Drive Current & Gate Delay:
I ON =
MOSFET Channel Energy Band:
W
! Qinv ! vinj
Lgate
T
1
1-T
Lgate ! VDD
C LOADVDD
=
(VDD " VT )! vinj
ID
kBT/q
D
S
Ballistic Ratio Comparisons:
(from Monte Carlo simulations)
l
Si
Ge
Ge
<100> <100> <111>
n-MOS
0.68
0.78
0.76
p-MOS
0.48
0.70
0.56
(Lundstrom et al., 2001, Purdue)
araswat
tanford University
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Problems With Ge
Problems #1: Ge Surface Passivation
 The native oxide passivation on Ge surface is not stable
enough either during fabrication or in the end-product
Solution:
 High-κ
High-κ dielectrics are deposited on Si, why not on Ge?
Problem #2: Ge Wafers as a Substrate?
 Ge substrate not easy to handle and not easily available
 Si will continue to be the main substrate due to its overall
excellent properties
Solution:
 Heterogeneous integration of Ge on Si.
araswat
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Heteroepitaxial Growth of Ge on Si
Ge as deposited
Si
AFM
Ge after H2 anneal
H2
Rrms :2.5nm
Z = 50nm/div,
X= 2µm/div
Rrms : 25 nm
As Grown at 400°C No H2 Anneal
TEM
400°C Growth + 825°C H2 Anneal
Ge
Crystalline Ge
Defects
Si
Si
With H2 anneal dislocations are confined to the Si/Ge
interface leaving defect free top Ge layers.
araswat
tanford University
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HfO2
GeOxNy
Ge
4 nm
Gate Leakage
Effective Mobility (cm2/V-s)
HR-XTEM
Gate Current@ VFB+1V (A/cm2)
High Mobility Ge FETs with High-k
Mobility
400
25 µm Ge hi-! pFET
30 µm Ge hi-! pFET
100 µm Ge hi-! pFET
300
200
Si Universal
Mobility
100
Si hi-! pFET
0
0.2
0.3
0.4
0.5
0.6
Effective Field (MV/cm)
Equivalent SiO2 Thickness (nm)
Key Results
• Passivation of Ge with GeOxNy, ZrO2 and HfO2
• n and p dopant incorporation
• 1st demo of Ge MOSFETs with metal gate and hi-κ
• p-MOSFET with 3× mobility vs. Hi-k Si
• n-MOSFET demonstrated but mobility low
araswat
Chui, Kim, McIntyre and Saraswat, IEDM 2003
tanford University
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Ge nanowires synthesized by low temperature CVD
Au nano
particle
Cold-Wall NW Growth Reactor
nanowire
Substrate
• Vapor-Liquid Solid (VLS) mechanism
uses super saturated liquid eutectic
to locally deposit Si.
Nanowire
• Growth mechanism: wires grow as
the catalytic end moves
Au
GeH4 = Ge + 2H2
SiH4 = Si + 2H2
• Size of the wire is decides by the
size of the nano particle
Nanowire
• 10-20 nm single crystal Ge wires
Au
• CVD temperature: 275 - 400°C
araswat
tanford University
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Ge Nanowire Growth
SEM
TEM
 No control over the overall growth direction
 Individual wires are single crystal and grow along <110> direction
Courtesy: Hongjie Dai
araswat
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Ge Nanowire FET with High K gate dielectric
Ge NW MOSFET
Top view SEM
Channel
dielectric ~20nm
metal
semiconductor
SiO2
Source
~10nm
Drain
source
gate
drain
ALD HfO2 Coating of Ge NW
• 10-20 nm single crystal Ge wires
• CVD temperature: 275 °C
• Initial fabricated transistor shows
great promise µp ~ 500
• 3D integrable technology
Key Challenge: Controlled growth
Ref: Wang, Wang, Javey, Tu, Dai, Kim, McIntyre, Krishnamohan, and Saraswat, Appl Phys. Lett, 22 Sept. 2003
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tanford University
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Center Channel Double/Surround Gate FET
Conventional DG
Schred: 1-D Poisson-Schrodinger simulations
Depletion-Mode DG
Depletion regions
G
E-field
G
S
D
OFF
S
G
Zero E-field
D
G
Channels at the surface
Channel in the center
G
G
D
S
ON
S
Charge
density
D
G
G
Transport:
Electrostatics:
• Zero E-field by symmetry of DG
structure
• Reduced scattering due to perpendicular
E-field
• Natural fan-out (lower R parasitic )
High performance devices:
• Excellent control of short channel effects
due to DG structure
• Excellent sub-threshold slope
• Very low DIBL and Vth roll-off
• High mobility channels leading to very
high drive currents
• Very high switching speeds
• Very high cut-off frequencies
• Lower power dissipation
Technology integration:
• Easier integration with high-k materials
• Fully utilizes excellent transport
properties of materials like Ge, SiGe,
strained Si etc.
araswat
Krishnamohan and Saraswat, IEDM 2003
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Epitaxial Growth of Vertical Nanowires
(111) surface
Ge
SiContaining
containing
vapor
Vapor
<111> oriented Si NWs on (111) Si
Au
Nanoparticle
Si Ge
Nanowire
nanowire
[111]
Yiying Wu et al., Chem. Eur. J., 2002, 8, 1261
Si nanowires grow epitaxially on a (111) Si plane
araswat
tanford University
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o
i
t
a
r
Mobility Enhancements in Strained-Si MOSFETs
Strained Si channel
with high mobility
n+ poly
gate oxide
LTO
spacer
Strained Si
n+
NMOS
V
DS
Relaxed Si1-xGex
= 10 mV
n+
Si1-xGex Graded layer
300 K
Si Substrate
1.6
y
t 1.4
i
l
i 1.2
b
o 1.0
M
Measured, J. Welser, et al.,
IEDM 1994.
Mobility Enhancement Factor
Mobility Enhancement Factor
t
n
e
m
e
c
n
a 2.0
h
n 1.8
e
Calculated for strained Si
MOS inversion layer
S. Takagi, et al., J. Appl. Phys. 80, 1996.
0.80
0.0
0.10
0.20
0.30
0.40
Substrate Ge fraction, x
For substrate Gefraction x < 30%
• NMOS Idsat enhanced ~ 1.5X and
• PMOS Idsat enhanced only ~ 1.15X
Mobility Enhancement Factor
araswat
Gibbons Group, Stanford
PMOS
2.6
Calculation by
Oberhuber et al.
Rim, et al.
2.4
2.2
Currie and
Leitz, et al.
2.0
1.8
1.6
1.4
1.2
1.0
0
10
25
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20
30
40
50
Substrate Ge Content (%)
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Enhanced Hole mobility for Uniaxial Strained-Si
(Si3N4)
Si
Hole mobility for uniaxial strained-Si
introduced by Si1-xGex in the source/drain.
araswat
tanford University
Simplified hole valance band structure for longitudinal
in-plane direction. (a) Unstrained and (b) strained-Si.
S. Thompson, et al. IEEE EDL, April 2004
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Center Channel Double Gate Heterostructure FET
Krishnamohan and Saraswat
Elwomis: Full-Band Monte-Carlo Simulations
PMOS
Depletion-Mode DG
Depletion regions
G
OFF
S
D
G
Hole ψ
Channel in the center
ON
S
NMOS
Electron ψ
G
D
G
Higher drive current
araswat
Higher cut-off frequency
• Carriers in the center of an un-doped strained-Si or SixGe1-x channel
• high mobility also due to zero E field, strain, low surface scattering
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Two kinds of transistors
Schottky S/D MOSFET
Junction S/D MOSFET
Possible advantages of Schottky S/D MOSFET
• Better utilization of the metal/semiconductor interface
Possible option to overcome the higher parasitic resistance
• Modulation of the source barrier by the gate
High Vg ⇒ barrier thin ⇒ tunneling current ⇑ ⇒ ION ⇑
Low Vg ⇒ barrier thick ⇒ tunneling current ⇓ ⇒ IOFF ⇓
• Better immunity from short channel effects
Possible Disadvantage
• ION reduction due to the Schottky barrier
araswat
tanford University
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PN Junction vs. Schottky S/D Si DGFET Simulations
PN Junction S/D
ION vs. IOFF
Schottky S/D
Low barrier height metal/semiconductor contacts
required to achieve high ION and low IOFF
R. Shenoy, PhD Thesis, 2004
araswat
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Schottky Barrier MOSFET
Band diagrams (Schottky barrier FET)
Bias
0.5
source
Off-state
Vds=1.5V
Vgs=0V
Silicide
Si
BOX
Energy (eV)
0
-0.5
-1
-1.5
drain
-2
On-state
-2.5
Vds=1.5V
Vgs=1.5V
-3
0
0.005
0.01
0.015
0.02
0.025
0.03
x (microns)
Possible advantages
• Better utilization of the metal/semiconductor interface
Possible option to overcome the higher parasitic resistance
• Modulation of the source barrier by the gate
High Vg ⇒ barrier thin ⇒ tunneling current ⇑ ⇒ ION ⇑
Low Vg ⇒ barrier thick ⇒ tunneling current ⇓ ⇒ IOFF ⇓
• Better immunity from short channel effects
•Disadvantage
• Tradeoff between short channel effect vs. ION reduction due to the Schottky barrier
araswat
tanford University
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Optimal φB Schottky Barrier MOSFET
Lg~20 nm FETs with Complementary
Silicides PtSi PMOS, ErSi NMOS
Schottky Barrier
Silicide
Source
ErSi2
Si
BOX
Tilted
Lg + Spacers =27nm
Gate
N + poly, ErSi2
W=25nm
PtSi PMOS
20 nm
4 nm
1.2 V
270 uA/um
100 mV/dec
5E5
-0.7 V
ErSi NMOS
15 nm
4 nm
1.2 V
190 uA/um
150 mV/dec
1E4
-0.1 V
1E-3
1E-5
• Metal S/D reduce extrinsic resistance
• Need ultrathin channel, double gate
• Need low barrier technology to ensure high Ion
araswat
tanford University
|Vsd| f rom 0.2V to 1.4V
in steps of 0.4V
1E-4
|Id| (A/ µm)
Lg
Tox
Vg-Vt
Ion
Swing
Ion/Ioff
Vt
1E-6
1E-7
1E-8
PMOS
T ox = 4nm
1E-9
L g = 20nm
1E-10
-1.5
-1.0
NMOS
T ox = 4nm
L g = 15nm
-0.5
J. Boker et al.- UCB
0.0
0.5
1.0
1.5
Vg (V)
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Variation of the Schottky barrier S factor
S=
1
1+ 0.1("# $1) 2
S
!
ε∞
Yeo, King, and Hu, J. Appl. Phys., 15 Dec. 2002
Ref: Robertson, MRS March 2005
 High K’s are less ‘Schottky-like’ than SiO2. Barrier heights change less
than metal workfunction.
 Strong pinning for semiconductors
araswat
tanford University
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Combining New Device Structures
with New Materials
We will be here with
these innovations
We are
here today
•With better injection and transport we may be able to reach closer to the ballistic Ion
•With better electrostatics we may be able to minimize Ioff
araswat
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Seemingly Useful Devices
Limited Current Drive
Cryogenic operation
Limited Fan-Out
Critical dimension control
Challenging fabrication
and process integration
B
+
=
~ 2 nm
Spintronics
Need high spin injection
and long spin coherence time
araswat
tanford University
Limited thermal stability
New architectures needed
34
Carbon
Nanotubes
Controlled growth
Saraswat - EE311/Future Devices
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Motivation for Organic FETs
25 µ m
Low-Cost, Flexible Electronics
Philips
Plastic Logic
Penn State / Sarnoff
30 µm
Siemens
araswat
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Organic Semiconductors
Applications
LSI
(864 Transistors)
• identification tags
• low-end data storage
B. Crone, A. Dodabalapur et al.
Nature 403, 521 (2000)
• smart cards
• emissive displays
• electronic paper
All-Printed
Polymer Circuit
• distributed computing
Z. Bao / Bell Labs
• toys, clothes, ...
low-cost, lightweight, rugged, flexible electronics
No competition to Si,
Going where Si can‘t follow !!
araswat
tanford University
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Next Step : ‘Molecular Electronics
Nanotube Devices / Circuits
(Stanford, IBM, ...)
Molecular Switches
(HP, Cal Tech, Stanford ...)
araswat
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tanford University
Nano-Patterning
Saraswat - EE311/Future Devices
Self-Assembly
Molecular Materials
Molecular Electronics
Molecular-Scale Three-Terminal Devices ?
araswat
tanford University
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Organic Insulator / Semiconductor Monolayer
(σ − π SAM)
J. Collet et al., APL 76, 1339 (2000).
araswat
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Self-Assembled Monolayer Molecular FET
Molecular Relays
Molecular FETs
•Molecular Length Defines Channel
araswat
tanford University
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Molecular Electronics Interfaced with Silicon
Technology
Demultiplexers
Order (n) wires
(large pitch)
Molecular Switch
To gain element
or logic circuit
MS
multiplexer
Crosspoint
molecular electronic
memory: 2n bits
(20 – 30 nm pitch)
• Molecular mechanical complexes as solid-state switch elements
• Non-traditional patterning techniques to achieve a memory bit (cross-point) density of >1011/cm2.
• Non-linear, voltage response of molecular switches to latch (amplify) and clock signals by
coupling a large molecular circuit with very few CMOS-type amplifiers.
Source: Nicholas Melosh and J. Heath
araswat
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Graphene band structure
y
E
x
“left-handed”
“right-handed”
conduction
EF
K1
K2
valence
k||
Two cones in unit cell
Symmetry K1 = -K2
k!
araswat
tanford University
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Diversity of SWNTs
(10,10) Arm-chair
Metal
(18,0) Zig-zag
Small gap
Quasi-metal
Chiral angle: M, S, or Quasi-M
Diameter: band gap ~ 1/d
(0.6 eV for d=1.4 nm)
(0.84 eV for d=1 nm)
(7,12)
Chiral
Semiconductor
araswat
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E
E
Nanotube Band Structure
semiconducting
small bandgap
semiconducting
1.0
0.15
0
-10
0
Vgate (V)
10
large bandgap
semiconducting
G (e2/h)
0.15
G (e2/h)
G (e2/h)
k!
metal
0
Eg ≈ 0.8/d (nm) eV)
k||
k||
k!
Egap
0
0
-4
0
4
Vgate (V)
0
-10
0
Vgate (V)
10
Due to curvature, strain, etc.
araswat
tanford University
McEuen et al., IEEE Tr ans. Nanotech., 1 , 78, 2002.
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Band Gap vs. Diameter
(3)
(3)
m-n ≠ 3 · integer
semiconductor
Eg ~ 1/R
C. Kane, G. Mele, Phys. Rev. Lett. 78 1932 (1997)
araswat
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Ballistic Nanotube Transistors
Growth
MOS Transistor
Nanotube
Gate
HfO2
D
S
10 nm SiO2
CnHm
p++ Si
10
-5
10
-6
10
-7
10
-8
10
-9
-IDS (A)
Dai (Stanford)
McIntyre (Stanford)
Gordon (Harvard)
Lundstrom (Purdue)
IDS (µA)
Catalyst Support
0.2 V
IDS (µ A)
Fe
-0.1 V
-10
L ~ 50 nm
-15
-
VDS = -0.1,-0.2,-0.3 V
-20
-0.4 V
-0.7 V
-1.0 V
L ~ 50 nm
-1.3 V
-1.5 -1.0 -0.5 0.0
VG (V)
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-5
IDS (µA)
CnHm
0.5
-25
-0.4 -0.3 -0.2 -0.1 0.0
VDS (V)
Key Challenge: Low thermal budget controlled growth
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Ids (A)
High Performance CNT-6
10
N-MOSFETs
10
D
G
10
-8
Vds=0.5 V
S~70
mV/dec
S~80
mV/dec
-10
d~1.6 nm
S
G
HfO2
Pd
n+
i
-1
K+
n+
Pd
500 nm SiO2
p+ Si
10
8
0
Vgs (V)
p-FET
1
n-FET
Moderate
S/D doping
Ids (µ A)
K+
CNT
6
4
2
Dai/Gordon/Guo Groups
0
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-0.4 -0.2 0.0 0.2 0.4
Vds (V)
Saraswat - EE311/Future Devices
Ambipolar Schottky S/D Nanotube FETs
araswat
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Conventional MOS Like Nanotube FETs
SB
MOS
Dai group, Stanford
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tanford University
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Theoretical Limits to Scaling



Thermodynamic limit:
Eb ≥ kB.T.ln2
Quantum mechanics
∆x . ∆p ≥ h  xmin (Integration density)
∆E . ∆t ≥ h  τ (witiching speed)
Eb
xmin
Ultimate limit:
•
•
•
•

Emin
xmin ~ 1.5 nm  5.103 transistors/cm3
Switching speed tmin ~ 0.04 ps  25 Tbits/sec
Switching energy Ebit = 17 meV
Power = 55 nW/bit
For densely packed, 100% duty cycle devices
• Total power density = 4.106 W/cm2

With duty cycle ~1 %, Active transistors ~1 %
P=
n max E bit
t min
• Total power density = 370 W/cm2
Source: George Bourianoff, Intel
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!
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Spin Based Switch
Jim Harris et al. (Stanford)
Charge
ΔEb(e-) ~1.7x10-2 eV
Spin
ΔE(spin) ~8.6x10-8 eV
B
a
Eb
+ =
a
Eb
w
w
ΔE(spin) << ΔE(e-)
Single spin state can be detected by
measuring if there is any tunneling current.
After Mark Bohr, (Intel)
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New materials
Ge
SiGe
Semiconductors
Ta2O5
HfO2
High-k
dielectrics
ZrO2
Si3N 4
Al
Al
Poly Si
Air
WSi2
HSQ
CoSi2
Polymer
Pt
TiN
IrO2
TiSi2
Silicides
SiO2
SiO2
MoSi2
TaN
Si
Si
TaSi2
Cu
1950
1970
ZrSixOy
PtSi2
1980
Low-k
dielectrics
Electrode
materials
Y1
Metals
PZT
Ferroelectrics
BST
W
1990
RuO2
2000
2010
(S. Sze, Based on invited talk at Stanford Univ., Aug. 1999)
Moore’s Law increasingly relies on material innovations
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Nanotechnology
Conclusion: Technology Progression
(After P. Wong)
Bulk CMOS
Wafer bonding
Crystallization
Nanowires
FD SOI CMOS
3D ICs
Strained Si
Cu interconnect
Si
(tensile)
Low-k ILD
Optical interconnect
Si0.8Ge0.2
Si1-xGex
Si
High k gate dielectric
Metal gate
Double-Gate CMOS
Gate
Source
Detectors, lasers,
modulators, waveguides
Single e
transistor
Drain
Ge/Si Heterostrcture
Nanowire
Ge on Si hetroepitaxy
Nanotube
Selfassembly
Ge on Insulator
Interconnects
and contacts
for nanodevices
100 nm
Feature Size (Time)
Molecular device
B
+ =
Spin device
2 nm
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