SEMATECH Symposium Taiwan
September 7, 2010
Accelerating the next technology revolution
Advanced CMOS Scaling
Raj Jammy
VP Materials and Emerging
Technologies
SEMATECH
Copyright ©2010
SEMATECH, Inc. SEMATECH, and the SEMATECH logo are registered servicemarks of SEMATECH, Inc. International SEMATECH Manufacturing Initiative, ISMI, Advanced Materials Research Center
and AMRC are servicemarks of SEMATECH, Inc. All other servicemarks and trademarks are the property of their respective owners.
Outline
• CMOS scaling roadmap
• Critical modules/considerations for CMOS scaling
–
–
–
–
Gate stacks
Junctions and contacts
Non-planar devices
High mobility channels
• Alternate devices and summary
2
CMOS scaling for performance/power
@ cost
Lower
Power
Higher
Performanc
e
Power (a.u.)
Scaling provided cost benefit and performance simultaneously
3
Device scaling: detailed look at power
I dsat
A o W

(Vg  Vt ) 2
Tox ,inv 2 L
Ion
Id
Gate
Gate
leakage
Source drain
current
Junction leakage
(including GIDL)
Ig (gate
leakage
)
Drain
Ij (junction
leakage)
Substrate
Power [ACTIVE] = a.f.C.Vdd2
a: Active ratio
f:frequency
C: Load capacitance
Vdd: Supply voltage
Ioff
Vg=0
Vg=Vdd
Power [Standby] = Ioff.Vdd
Ioff = subthreshold leakage + GIDL + Gate Leakage
4
Generic MOSFET scaling trends
Novel materials and architectures
New Mat’l/Structure
III-V Device
High-K
MG
45nm
2007
12 nm + (2015+)
planar
32nm
2009
Si-Ge Device
16nm (?)
2013+
22nm
2011+
Intel,
IEDM 2007,9
T-FET
(Production))
Intel IEDM 2007
(Production))
Intel IEDM 2009
6nm Length
B. Doris IEDM 2002
IBM, IEDM 2009
Non-planar
Intel Tri-Gate,
VLSI 2006
NXP FINFET, VLSI 2007
Nano-wire (LETI IEDM’08)
5
Planar CMOS scaling: critical modules
Contact Resistance:
Junction Extensions:
• USJ with low Rs
-Adv Doping: Plasma, MLD, …
- Adv Anneal: Flash, Laser, …
- compatibility with transistors
Gate
 Tuning Schottky Barrier of Silicides
 Doped Ni Silicide and Dual work function silicides
 Alternative approached (DDM…)
 Schottky FETs
Electrode
Source
Substrate: Si
High-k
Silicide
Drain
Gate Stack:
 CET Scaling with low leakage
-Highk for EOT
- Metal Gates for poly depletion control
 Target Vt : Metal Gates with correct workfunction
6
6
Gate stack module: requirements for
high-k/metal stack
High-k simultaneously delivering:
a) Mobility
>80% SiO2
(1 MV/cm)
b) VT
c) VT reliability
d) Morphology
VT < 20 mV
Match VT
SiON/n-PolySi 1000s CVS @ 125C
Amorphous
≥ 1070C
P. Kirsch IEDM 2006
e) Scaling
<0.9 nm EOT
<1.3 nm Tinv
Maximize
I dsat
Poly-Si
A o W

(Vg  Vt ) 2
Tox ,inv 2 L
Minimize
Metal
BE, Stable
+ + Hi-k
x
x
e-
• Optimizing drive current depends on many dielectric issues
7
Demonstrated gate stack (EOT) scaling
100
Mobility (cm2/V-s)
Mobility (cm2/V-s)
350
300
250
50
0
200
150
100
Red: SiON#
1.04 nm EOT
SiON
1.20 nm EOT
1.08 nm EOT SiO
2
1.25 nm EOT
0.5
pMOS
0.5
1.0
1.5
Field (V/cm)
2.0
nMOS
1.0
1.5
2.0
Field (MV/cm)
•
•
Achieved SiON like Mobility for low EOT ~ 1nm
Scaling further ongoing challenge [Higher-k … Zero Interface].
8
High(er) K and zero-interface-layer (ZIL)
Continuous improvement/challenge
2
Mobility@1MV/cm (cm /V-s)
Continuous Improvement
(Scaling 250
CET w/o Mobility Loss)
225
IL~0nm
Metal gate
200
KHfO2=20 (40)
Metal gate
150
EOTHi-k=
0.39 (1.9)nm
EOTIL= 0.3 nm
125
Si
175
0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3
EOT (nm)
High-k
2nm
J. Huang, et.al, IEDM 2008
SEMATECH identified several ternary and quaternary high-k dielectric
systems in medium-k range (30<k<50)
• SEMATECH identified process routes for ZIL with EOT ~0.6nm
•
9
SEMATECH lead the ground work
for metal gates materials screening
•
SEMATECH has researched on 350 different material systems
– EWF, physical characteristics, electronic properties, band structure, stress,
thermal budget, interface, chemical composition, diffusivity, wet/dry etch
selectivity, reactive ion etching, chemical mechanical polishing, ion implantation
(conventional, monolayer doping, plasma), epitaxial growth, atomic layer
deposition, CVD and PVD
10
SEMATECH demonstrated feasibility for
HKMG CMOS with advanced materials
PMOS
Metal
50 nm
Dual metal gate on
single high-k, VLSI 05
Dual metal gate on
dual high-k, VLSI 06
SiGe
Si
Dual Channel
VLSI 07
nMOS with thin metal
pMOS with
thick metal
pMOS
Non-Planar FinFET, ESSDERC 07
m
Hard
• SEMATECH Demonstrated:
– Well controlled integration of
dissimilar devices with good isolation
– Nano structures fabrication –
precisely and reproducibly across
200/300 mm wafers
– High volume manufacturing-ready
processes of multi-component
systems with high yield
1st
as k
Single metal gate on
single high-k, VLSI 09
Hybrid CMOS
ECS 07
Gate First
1st metal
metal
STI
2nd metal
STI
High-k
A. High-k/1st metal/hard mask deposition
B. Hard mask/1st metal/hard mask etch
STI
High-k
C. 2nd metal deposition
High-k
D. Poly-Si deposition
E. Gate etch
Gate Last
Poly
High-k
Metal
High-k
Fabricate poly-Si/SiON CMOS
and CMP to expose gate
Remove poly-Si/SiON
Deposit high-k and metal gate
11
Planar CMOS scaling: critical modules
Contact Resistance:
Junction Extensions:
• USJ with low Rs
-Adv Doping: Plasma, MLD, …
- Adv Anneal: Flash, Laser, …
- compatibility with transistors
Gate
 Tuning Schottky Barrier of Silicides
 Doped Ni Silicide and Dual work function silicides
 Alternative approached (DDM…)
 Schottky FETs
Electrode
Source
Substrate: Si
High-k
Silicide
Drain
Gate Stack:
 CET Scaling with low leakage
-Highk for EOT
- Metal Gates for poly depletion control
 Target Vt : Metal Gates with correct workfunction
12
12
USJ: advanced doping and/or
advanced anneal
8000
8000
Flash
7000
7000
Low energy, Plasma doping
high dose
5000
5000
USJ
Clustered
molecules
Laser
4000
4000
Infusion +
multistep
FLASH
3000
3000
Annealing
Flash
S
R
ce
(csq.)
S heet
R esistan

S hh eet
eet
R esistan
esistan
ce
 (sq .)
6000
6000
Doping
In-situ epi
~ Spike Anneal Xj Limit
(w co-implant)
Spike
Can achieve low Rs, Xj with std I/I
and FLASH (SEMATECH)
Spike
2000
2000
Old Data
1000
1000
TARGET
00
10 15
15 20
20 25
25 30
30 35
35 40
40 45
45 50
50 55
55 60
60 65
65 70
70 75
00 55 10
32 nm target
JunctionDepth
Depth(nm)
(nm)
Junction
SEMATECH is actively evaluating advanced doping and annealing techniques
SEMATECH demonstrated USJ’s meeting 22nm and below specifications
13
Source
Substrate
Drain
4000
3000
Spike
2000
1000
Flash
0
0
2
Gate
5000
Effective Mobility (cm /V-s)
Flash or Spike
anneal
Sheet Resistance (/sq.)
Demonstrated compatibility of flash
anneal with High-k/metal gate stack
10
20
30
40
50
-3
Junction Depth, X j @ 5E18 cm (nm)
300
200
Universal
Spike (w/ Rsd correction)
100
Flash (w/ Rsd correction)
0
0.0
5
5.0x10
6
1.0x10
6
1.5x10
6
2.0x10
Effective field (V/cm)
Degraded Mobility and NBTI is observed
for flash-annealed gate stacks.
14
Developing defect-free junctions
Mono-layer doping (MLD)
• Demonstrated USJ’s (as low as 5nm) with
monolayer doping of n and p dopants in Si.
A.Javey, et.al, UCB-SEMATECH, Nanoletters, 2008
15
Planar CMOS scaling: critical modules
Contact Resistance:
Junction Extensions:
• USJ with low Rs
-Adv Doping: Plasma, MLD, …
- Adv Anneal: Flash, Laser, …
- compatibility with transistors
Gate
 Tuning Schottky Barrier of Silicides
 Doped Ni Silicide and Dual work function silicides
 Alternative approached (DDM…)
 Schottky FETs
Electrode
Source
Substrate: Si
High-k
Silicide
Drain
Gate Stack:
 CET Scaling with low leakage
-Highk for EOT
- Metal Gates for poly depletion control
 Target Vt : Metal Gates with correct workfunction
16
16
Review of resistance components
K. Kuhn, IEDM SC, 2008
• Evolutionary Racc improvement through Xj scaling (anneal/implant) until the end of the
planar roadmap (thereafter Tsi/Wsi limited)
• Repi / Rspreading improvement from raised source/drain (RSD)
• Limited Rsilicide improvement (NiSi has the lowest known resistivity)
• Significant possibility for Rinterface improvement, particularly through SBH
optimization (Rinterface).
• Rcontact improvement from high conductivity metals (copper?)
17
Material screening for low
resistance contacts
Near Band Edge for PMOS
P.Majhi , et.al, SEMATECH, ECS 2007
Near Band Edge for NMOS
Experimental Demonstration of Achievable Schottky Barrier Height for Various
Material Options
18
Demonstration of Silicide/ Si
interface engineering
W. Loh. et. al.,
SEMATECH, VLSI 2009
 2  m* 
s
B
 c  exp 
contact resistivity,


N





• Significant barrier height modulation with nitrogen
• Significant to Logic (HP, LOP, LSTP), analog and memory
19
Developed novel scheme for tuning
Schottky barrier height
Coss. et. al., SEMATECH, VLSI 2009
• Demonstrated significant SBH ~0.6eV
using the dipole mediated scheme.
• Flexible scheme to accommodate
contacts to alternative substrates (nonalloyed contacts)
20
Common challenges for CMOS scaling
options and SEMATECH efforts
Bulk FET
finFET/Trigate
SOI=>ETSOI
Common Challenges for
All Options
-Resistance
-Capacitance
-Mobility
Nanowire
• Resistance [Rco< 5e-9 ohm.cm2] compatible with strain
technology
• Mobility [>>strained Si for mobility and Vinj]
• Address major issues with Cpara [for e.g, nanowires]
21
Non-planar devices
Similar module challenges and improved SCE
R.
R. Harris
Harris (SEMATECH),
(SEMATECH),
Stanford
workshop
Stanford workshop on
on MUGFETs,
MUGFETs, 2007;SEMICON
2007;SEMICON 2008
2008
Gate Etch
Epi S/D
Doping
10000
1000
100
10
1
Id (m A /  m )
0.1
0.01
Lg<30nm
Vd=50mV
Vd=1V
Wfin=20nm
SS = 71 mV/Dec
DIBL = 28mV/V
IOn = ~1 mA/m
1E-3
1E-4
1E-5
@Vg-Vt=0.8V
and Vdd=1V
1E-6
1E-7
Spacer
Fin Formation
1E-8
1E-9
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
Vg
22
Demonstrated series resistance
improvement in finFETs
FinFET Series Resistance
Si
Eg=1.12eV
Increase ΦB
NiPtSi (Al)
Decrease ΦB
PFET
NFET
Si
Eg=1.12eV
SBH Modulation Model
•
Demonstrated SBH modulation (Diode) with Al implant
•
Demonstrated reduced Rext in finFETs for NFETs
•
This is a compatible to current NiSix process and scalable approach
23
Demonstrated SiGe in scalable finFETs
{100}
HK
MG
{110}
SiGe (110)
and (100)
SiGe
20 nm
{100}
SiGe
Si
{100}
Si (110) and (100)
20 nm
BOX
C.S. Smith, SEMATECH, IEDM 2009;
Img: 'E2092 080625015 6081002 22 2ndTry Fins SiGe 45deg s dm3'
MAG: 115kX
SiGe channel shows significant improvement over Si (no
intentional strain in these devices)
24
Evaluating value of nanowires
HK TiN
Simulation and experiments
a-Si
[4 x]
Si
[2 x]
BOX
50 nm
W = Lg = 40 nm
# of Gates
PFET
NFET
ID (A)
• Simulations show improved performance at
significantly scaled geometries
• Experiments show well controlled short channel
effects
• SEMATECH activities focused on addressing scaling
pathway of non-planar devices
|VD| = 1 V
|VD| = 50 mV
VGS (V)
25
Generic MOSFET scaling trends
Novel materials and architectures
New Mat’l/Structure
III-V Device
High-K
MG
45nm
2007
12 nm + (2015+)
planar
32nm
2009
Si-Ge Device
16nm (?)
2013+
22nm
2011+
Intel,
IEDM 2007,9
T-FET
(Production))
Intel IEDM 2007
(Production))
Intel IEDM 2009
6nm Length
B. Doris IEDM 2002
IBM, IEDM 2009
Non-planar
Intel Tri-Gate,
VLSI 2006
NXP FINFET, VLSI 2007
Nano-wire (LETI IEDM’08)
26
Process induced strain
Key enabler for HP,LP, & LSTP?
High Mobility
I dsat  
High-k
A o W
(Vg  Vt ) 2
Tox ,inv 2 L
• Strained-Si significant technology
enabler for all markets
• However, we NEED performance
beyond strained-Si for high
performance at low power in scaled
FETs.
27
SEMATECH evaluating promising
high mobility materials
I dsat 
Property/
Material

A o W
2

(Vdd Vt )
Tox ,inv 2 L
Si
Ge
GaAs
In0.53Ga0.47As
InAs
Graphene
1.1
0.66
1.4
0.75
0.35
0*
n (cm2/v-sec)
1,350
3,900
4,600
>8,000
40,000
>100,000
p (cm2/v-sec)
480
1,900
500
350
<500
>100,000
0.165
0.12
0.067
0.041
0.024
<0.01
0
4%
4%
8%
12%
n.A
Eg (eV)
m*/mo
Lattice mismatch
to Si
pMOSFET
nMOSFET
* Tunable but at cost
of degradation
28
SEMATECH focused on key challenges
Group consensus at SEMATECH hosted workshops “New Channel
Materials for Future MOSFET Technology” [2006-2010]
Challenges with Ge devices
Challenges with III-V devices
1. Short Lg demonstration
1.
- BTBT due to low Eg?
- Compete with strained Si
III-V on Si
2. PMOS
2. CMOS ?
- NMOS: practical or
fundamental barrier?
3. Scalability
3. Gate Stacks
- scalability
- reliability
4. Heterogeneous integration on Si
- selective epi ?
4. Enhancement mode
5. Gate Stacks
Several Other Challenges w.r.t Metrology, Process Challenges…
29
High Ion/Ioff with Si-Ge based MOSFETs
P. Majhi et.al, S. Lee et.al, SEMATECH,
EDL 2007-2008
Nicholas et.al., IMEC, TED 2007
Hutinet.al., LETI, VLSI-TSA 2010
• SEMATECH lead the demonstration of High Ion/Ioff ratio for short Lg devices
30
Performance of Si/SiGe/Si QW
pFETs
~3xSi
S.Lee, W.Tsai, P.Majhi et.al EDL 2008
• SEMATECH lead the demonstration of performance @ power advantage of SiGe
based QW MOSFETs
31
SEMATECH leading continuous improvement
of surface channel III-V MOSFETs
N. Goel et.al., SEMATECH, IEDM 2008
Huang et.al., SEMATECH, IEDM 2009
HEMTs, Intel, IEDM 2007 [no High-k]
10000
14
CB
VB
conventional
surface channel
MOSFETs
12
-2
Dit (10 eV-1cm )
10
13
P-sub.
200K
12
ZrO2
10
10
300K
N-sub.
1nm Al2O3/ZrO2
10
150K
1nm LaAlO3/ZrO2
11
0.0

Degradation
w/ HKMG
Modified surface
channel MOSFETs
0.2
0.4
0.6
Energy in bandgap(eV)
• SEMATECH Addressing Key Question:
Can the HighK/III-V interface be improved
enough compared to buried channel ? …
Intrinsic Issue ?
32
SEMATECH leading module and process
development for III-V on Si for VLSI
Example of junctions
Target for ~1215 nm node
• SEMATECH demonstrates defect-free process for state-of-art junctions
on III-V meeting 12nm node (and below) specifications
33
SEMATECH leading to process
development issues with III-V on Si
Pitch ~55nm
Reducing parasitic
series S/D
resistance (Low c,
CMOS Metals)
Acceptable control
of short channel
effects (CET, Dit,
Vth)
Isolation strategy; mesa; STI ?
Thin spacer [ALD?] and etch
CO etch (stop on S/D) +
ohmic metallization
Wide-bandgap/dielectric barrier
STI
Wide-bandgap/dielectric barrier
Hetero buffer
Hetero buffer
For pFET
For nFET
Minimize offset for CMOS
Si substrate
Very shallow and low Rs
S/D extension (tip) for SCE
Low defect density; Acceptable DOS with
tolerable Ileak.sub (Eg, E, ), “on Si for VLSI”
- Cleans to remove
surface oxides
- ALD Gate stack
(clustered tool ?)
ALD Gate Stack
Epi growth
High - µn channel
In situ doped
Epi for S/D
Shallow Junction
underlap/overlap?
Delta doped ?
Wide-bandgap/dielectric barrier
STI
Hetero buffer
Wide-bandgap/dielectric barrier
Hetero buffer
Si substrate
Buffer strategy for CMOS; Low
defects [Tolerable leakage]
Epi growth High - µp channel
(III-V or Ge pFET)
34
Summary: SEMATECH evaluating critical issues
with new materials/ architectures for future
technologies
VLSI, 2009
VLSI, 2009
Nanoletters,
2008
VLSI, 2009
VLSI-TSA, 2009
IEDM, 2008
VLSI, 2009
35
Summary: CMOS scaling enabled only
by new materials/ architectures
VLSI, 2009
VLSI, 2009
CMOS Scaling Driven by Increasing Need for Higher
Nanoletters,
Performance at Lower Power and Cost
2008
VLSI, 2009
CMOS Scaling Enabled by New Materials and/or New
Device Architectures
VLSI-TSA, 2009
SEMATECH Programs focused on evaluating critical
modules/materials/devices in inter-disciplinary fashion to
VLSI, 2009
continue CMOS scaling for higher
functionality/cost.
IEDM, 2008
36