Making individual ICs

2007 ELEKTRONIKOS ĮTAISAI

Making individual ICs

The thin wafer is like a piece of glass. The hundreds of individual chips are separated by scoring a crosshatch of lines with a fine diamond cutter and then putting the wafer under stress to cause each chip to separate. Those ICs that failed the electrical test are discarded. Inspection under a microscope reveals other ICs that were damaged by the separation process, and these are also discarded.

The good ICs are individually bonded into their mounting package and the thin wire leads are connected by either ultrasonic bonding or thermocompression.

The mounting package is marked with identifying part numbers and other information.

The completed integrated circuits are sealed in anti-static plastic bags to be stored or shipped to the end user.

VGTU Elektronikos fakultetas http://www.answers.com/topic/integrated-circuit stanislovas.staras@el.vtu.lt

ELEKTRONIKOS ĮTAISAI 2007

VGTU Elektronikos fakultetas stanislovas.staras@el.vtu.lt


When all the processes required to realize all the components and their interconnections are performed, an electrical test of each die is performed.

A wafer prober with sharp probes is used to connect and electrically test each circuit in turn. Circuits that fail are automatically marked.


ELEKTRONIKOS ĮTAISAI

Test of circuits. Prober

2007 http://technology.niagarac.on.ca/courses/tech1271/mosfet%20w2002.JPG



After that each wafer is cut into chips. A thin saw impregnated with diamond particles may be used for cutting grooves along the circuits edges. The wafer is then cleaned and stressed, so that it cracks along the grooves into separate dies each with a single circuit on it.



Semiconductor-die cutting

In the manufacturing of micro-electronic devices, die cutting or dicing is a process of reducing a wafer containing multiple identical integrated circuits to dice each containing one of those circuits.

During this process, a wafer with up to thousands of circuits is cut into individual pieces, each called a die. In between the functional parts of the circuits, a thin non-functional spacing is foreseen where a saw can safely cut the wafer without damaging the circuit. This spacing is called the scribe . The width of the scribe is very small, typically around 100 µm . A very thin and accurate saw is therefore needed to cut the wafer into pieces. Usually the dicing is performed with a water-cooled circular saw with diamond-tipped teeth.

http://en.wikipedia.org/wiki/Die_preparation



Wafer mounting

Wafer mounting is a step that is performed during the die preparation of a wafer as part of the process of semiconductor fabrication . During this step, the wafer is mounted on a plastic tape that is attached to a ring. Wafer mounting is performed right before the wafer is cut into separate dice . The adhesive tape on which the wafer is mounted ensures that the individual dice remain firmly in place during 'dicing', as the process of cutting the wafer is called.

The picture below shows a 200 mm wafer after it was mounted and diced. The blue plastic is the adhesive tape. The wafer is the round disc in the middle. In this case, a large number of dice were already removed.

VGTU Elektronikos fakultetas

Wafer glued on blue tape and cut into pieces stanislovas.staras@el.vtu.lt


Bonding

The chips are placed into the packages in which they will be used.

Thin gold or aluminium wires are bonded between the circuit bonding pads and the package pins.

Thermocompression bonding (heat, pressure and inert atmosphere) is used to bond gold wires to aluminium pads.

Supersonic bonding (supersonic vibrating jig) may be used to bond Al wire to Al pads.


2007


Bonding

2007



Bonding

2007

25µm gold wire ball/wedge bonding of IC to ceramic package



Bonding

2007

25µm gold wire ball/wedge bonds as produced by a fully automatic production machine, bonding speeds approx. 5 wires/second



Back or flip-chip bonding is used for the automation of the bonding process.

Bonding

Chip Raised pad

Tape chip carrier

VGTU Elektronikos fakultetas

2007 stanislovas.staras@el.vtu.lt


Bonding

2007

View with also the returned die (not mounted)



Trends of microelectronics

Complexity of ICs

2007

The complexity of integrated circuits is described by the number of parts that form the circuits: small scale integration (SSI) – medium scale integration (MSI) – large scale integration (LSI) – very large scale integration (VLSI) – ultra large scale integration (ULSI) –

2 1 -2 6 (2-64) elements,

2 6 -2 11 (64-2048) elements,

2 11 -2 16 (2048-65536) elements,

2 16 -2 21 (65536-2x106) elements,

2 ⋅ 10 6 -10 9 elements.

K = lg M

IC, containing 50000 elements, correspond to 5th scale integration.



Complexity of ICs. Moor’s law

2007 http://download.intel.com/research/silicon/moorespaper.pdf



Complexity of ICs. Moor’s law

2007

The most common description of the evolution of CMOS technology is known as Moore's law. It is important to understand the key principles underlying Moore's law, since these allow us to gain insight into the future. The observation made by Gordon Moore in 1965 was that the number of components on the most complex integrated circuit chip would double each year for the next 10 years. This doubling was based on a 50-60-component chip produced in 1965 compared with those produced in preceding years, starting with the single planar transistor in

1959. In 1975 Moore noted with amazement that his previous prediction had come true. He predicted, however, that in the future the number of components per chip would require nearly two years rather than one year to double. He believed that this change in slope would occur in

1980, but it happened earlier, in 1975. In the last 20 years this prediction has been remarkably realized and has gained the status of a

“law.” The term Moore's law has come to refer to the continued exponential improvement in the cost per function that can be achieved on an integrated circuit.



Moor's law - to continue this trend we need new materials and technologies.

http://images.google.lt/imgres?imgurl=http://info.fuw.edu.pl/~kkorona/przedszkoleO/P1-

02Majewski.jpg&imgrefurl=http://info.fuw.edu.pl/~kkorona/przedszk.htm&h=1536&w=2048&sz=759&hl=lt&start=2&tbnid=v6dF3Iy-

K0JehM:&tbnh=113&tbnw=150&prev=/images%3Fq%3DMoor%2527s%2Blaw%26svnum%3D10%26hl%3Dlt%26sa%3DN



Trends of microelectronics

• Increase of complexity.

• Increase of chip dimensions and decrease of dimensions of elements.

• Nanoelectronics.

• Quantum effects.

• Application of new materials.

• Increase of power.

• Increase of operation speed.

• Development of functional electronics (optical, acoustic, magnetic (spin), molecular, etc.) electronics.


2007



Multiple interconnect layers

IBM photomicrograph (Si has been removed!)

Metal 2

M1/M2 via

Metal 1

Polysilicon

Diffusion

6.004 – Fall 2001

Mosfet (under polysilicon gate)

9/13/0

1

L03 - CMOS Technology

20

Making individual ICs - VGTU Elektronikos fakultetas

Test of circuits. Prober

Trends of microelectronics

Trends of microelectronics

Multiple interconnect layers

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Making individual ICs - VGTU Elektronikos fakultetas