Multi-gate pHEMT Modeling for Switch Applications
Ce-Jun. Wei, Hong Yin, Olesky Klimashov, Yu Zhu, and Dylan Bartle
Skyworks Solutions, Inc., 20 Sylvan Road, Woburn, USA
Abstract --- Multi-gate pHEMTs are extensively used in
pHEMT switch circuits for wireless communication
applications due to their size advantage. The intuitive
modeling approach which considers a multiple-gate pHEMT
to be a stack of single-gate FETs is far from adequate.
Crucial factors in multi-gate pHEMT modeling include
accurate leakage, CV below pinch-off, surface traps effects,
and distribution features for large size switch FETs. In this
paper we will address certain techniques to model both
intrinsic FETs and extrinsic parasitic components. Our
multi-gate pHEMT model was verified by comparisons of a
variety of performances between modeled and measured
data, including leakages, floating voltages, and CV curves on
device level. In a switch application, comparisons of
harmonics as a function of frequency at high driving power
for both GSM and DCS bands show excellent agreement
between model prediction and measured data as well.
I. INTRODUCTION
Switches in front-end modules are key components in
modern wireless communications, specifically in 3G and
4G products. Multi-gate devices, such as triple or dual
gate pHEMTs are frequently used to squeeze out more
performance from a limited area. In certain designs, five,
seven, and even 11 gate pHEMTs are also found. The
advantages of multi-gate pHEMTs include less chip area
occupancy and lower insertion loss compared to the single
gate switch with the same gate number. With feed-forward
capacitances, harmonics and distortion at high driving
power can be much reduced even with a low control
voltage. However, modeling a multi-gate FET switch is a
challenging task. Distortion, such as harmonics under high
input power, is very hard to predict. [1, 2] The modeling
process involves several crucial issues. First, the internal
channel nodes between neighboring gates are floating and
their potentials cannot be determined unless all leakages
and their partition are precisely modeled. Second, the
nonlinearity source below pinchoff which generates
distortion in off-state is a capacitance as a function of
voltages and dispersion parameters. Furthermore, there are
other issues regarding extrinsic channel resistances. The
analysis, characterization methods, and modeling
approach include leakages, dispersion, and external
parasitic, and hence appear complicated. We have reported
switch-related modeling work mostly on single-gate
devices. [2,3,4] For a multi-gate pHEMT model, although
we employ the core model of single gate device for each
individual gates of a multi-gate device, more attention is
paid on leakages and CV dependence below and near
pinch-off.[2,4-6] Factors taken into account for multi-gate
devices are listed as follows:
• Leakages of gate to drain/source and leakage between
drain to source and their partition;
• Gate capacitances verse voltages and dispersion effect;
•Separately characterize and model individual gate
leakage and CV characteristics. The leakages and gate
CV characteristics may be different for the gate junction
on the source/drain’s side from that on the channel’s
side.
•Distributed models for parasitic resistances. Essentially
the switch FET is a 3D device due to its large size. This
is quite important for on-state device modeling.
• Maximum current limitation of channel resistances.
Unlike MOS devices, pHEMTs have access resistances
with limited carrier supply capacity. We have to model
the channel resistances that have maximum current
limit. This turns out to be important during modeling of
power collapse in on-state pHEMTs.
• Dispersion effect brought by extrinsic currents flowing
through channel resistances.
We have developed the Skyworks’ pHEMT model for
switch applications [2]. The model has many features
including a comprehensive and distributed extrinsic
model. The core model has been reported previously. [5]
In this paper, we’ll address several modeling issues on
multi-gate FET modeling. Our new model meets all
challenges listed above, and has been incorporated into
company PDK for ADS and Cadence.
II. COMPROHENSIVE MULTI-GATE PHEMT MODEL
An equivalent circuit of a triple gate pHEMT including
intrinsic FETs and extrinsic parasitic is shown in Figure 1.
In the figure, TG1 and TG3 are FETs formed by edge-gate
junction, while TG2 is a FET formed by the center gate.
Two equations-based linear SDD-based access elements,
SP_Rd_Ld and SP_Rs_Ls are distributed elements that
model access resistances, Rs/Rd and metal inductances
Ld/Ls. Nonlinear equation-based SDD element Rgg1 and
Rgg2 account for the gate-to-gate channel resistances that
has a limit set for maximum channel current. Other
parasitic capacitances are: Cds_ext as the electrode drain
to source capacitance, Cdsi1/Cdsi2/Cdsi3 as intrinsic DS
capacitance via channel of individual gates, Cgg1 and
Cgg2 as the coupling gate-to-gate capacitances via air
coupling, and Cds_ext/Cgg1 / Cgg2/Ls/Ld as other access
elements which are generated by EM simulation or quasiphysical modeling. Cg1, Cg2 and Cg3 are parasitic gateto-ground capacitances outside the mesa area that can be
calculated using equations based on quasi-physics.
Drain
Vgse=_Cc(Vgso)*Vgso+(1-_Cc(Vgso))*Vgs
where Vgso is the DC component of Vgs. Effectively
reducing the Vgs swing, _Cc is a bias-dependent
parameter.
SP_Rd_Ld
Cg1
Rg
Cg2
TG1
Cgg1W=W
Nf=Nf
Cgs (F)
Cdsi1
Gate
SDD_Rgg1
Cds_ext
Cdsi2
Gate2
Rg2
Cgg2
Cg3
TG2
W=W
Nf=Nf
SDD_Rgg2
Cdsi3
Gate1
Rg1
TG3
W=W
Nf=Nf
SP_RsLs
Source
Figure 1. Equivalent circuit of a triple-gate pHEMT
III. SPECIAL CONSIDERATION IN INTRINSIC PHEMT MODEL
Intrinsic pHEMT Model has been reported in [4] and
will not be addressed here. Nonetheless, we will focus on
certain important effects that are correlated with multigate modeling.
A: Intrinsic CV dependence and its dispersion
Cgs (Vgs) and Cgd (Vgd) below pinch-off are the sole
distortion sources and should be taken into account
carefully. For multi-gate pHEMT, the gate facing onto the
channel has different and lower Cg than the side gates
facing toward Ohmic contacts have. Typical gate
capacitance characteristics for different kinds of gates are
shown in Figure 2.
The CV dependence can be modeled by using fitting
equations or simply look-up tables with proper
extrapolation beyond measurement region [1, 5, 6]. The
CV functions may be bias-dependent due to dispersion
effect.
Normally, the more negative biases, the flatter CV and
the more positive pinch-off voltage. The detailed
characterization requires de-embedment from pulsed Sparameters [6]. The dispersion can also be roughly
modeled by introducing more parameters to specify the
dependence in flatness of CV and Vp. The effective Vg
would be:
(1)
5.0E-13
4.5E-13
4.0E-13
Cgd red:TG-all gate connected
symbol:drain side gate to drain
3.5E-13
blue:cent gate
Brown: source gate to channel
3.0E-13
2.5E-13
2.0E-13
1.5E-13
1.0E-13
5.0E-14
0.0
-10 -9 -8 -7 -6 -5 -4
Vg (V)
-3
-2
-1
0
Figure 2. Gate CV dependence below pinch-off for different
gates. Red: drain-side-gate, G-to-D; Dot: Source-side-gate, G-toS; Blue: center gate, G-to-channel; Brown: Source-side-gate, Gto-channel
B.Leakages
Both leakages between gate to channels and between
neighboring gates must correctly be characterized and
modeled. The floating voltage is determined by equating
leakage across a gate to the leakage from channel to the
gate. The gate-to-channel leakages can be extracted from
single gate pHEMT with drain and source connected. The
channel-to-channel leakage between neighboring gates can
be extracted by fitting floating drain voltage as a function
of Vgs to measured data of a drain-open testing structure.
The GD, or GS leakage, is expressed as three components
that respectively dominate at lower, medium and high
negative Vg regions.
igs_lk =i gs_lkl i gs_lkm /( i gs_lkl + i gs_lkm )+ i gs_lkh
(2)
where i gs_lkl is the gate channel leakage above pinch-off , i
gs_lkm is the gate edge leakage below pinch-off, and i gs_lkh
is the soft gate breakdown current. All of them can be
modeled by diode equations.
Drain-Source leakage near pinch-off is a 2-D function
of vd and vg. The fitted gate leakage and floating gate-todrain voltage at drain open condition is shown in figure 3.
The leakage characteristics are gate-dependent and are
different between side gates and center gates. During our
research, we employ a new testing structure in order to
better model this effect. While characterizing one gate, we
short and bond the other two gates to their nearest drain or
source to avoid impact from floating gates on the channel
potentials. Figure 4 shows the difference in gate leakage.
The center gate leakage has smaller slope as Vg becomes
more negative than leakage of side gates has.
Measured (sym bol) vs modeled (line) floating Vg
0.5
Measured(symbol) vs m odeled(line) gate leak
0.0
0.0
-5.0E-8
-1.0
Ig_lk (A)
Vgd_float (V)
-0.5
-1.5
where nf is the gate finger number. Here Rs, Rmetal
calculated based on device physical parameters.
The impedance of one finger is:
Z_1finger= Zo / tanh(β*UW)
where
β=sqrt( (j ωL+Rmetal)/Rs)
Zo= sqrt( (j ωL+Rmetal)*Rs)
are
(3)
(4)
(5)
-1.0E-7
-0.15
-1.5E-7
-2.0
-0.20
-2.5
-3.0
-6
-5
-4
-3
-2
-1
0
-2.5E-7
-6
Vg1
-5
-4
-3
-2
-1
0
Vg1
Figure 3. Modeled (line) verse measured(symbol) gate leakage
and floating voltage for a PCM pHEMT device.
Insertion Loss (dB)
-2.0E-7
-0.25
-0.30
-0.35
-0.40
-0.45
-0.50
-0.55
0
2
4
6
8
10
12
14
16
18
freq, GHz
Figure 6. Simulated (line) versus measured (symbol) insertion
loss for series 1mm SG-FET, DG-FET and TG-FET. The gate
fingers numbers are all 8 and gate resistors are all 7.5 kOhm
B. Parasitic gate impedance
Figure 4. Gate leakages for different gates. brown: center-gate,
red and broken lines: Source-side-gate, and drain-side-gate
III. SPECIAL CONSIDERATION IN EXTRINSIC R MODEL
A. Distributed model of access elements
Important at higher frequency, distributed impedance is
taken into account by considering resistances of electrodes
and channel access regions Rs or Rd. The model of
distributed impedance is shown in Figure 5.
I1
L=Lmetal
R=Rmetal
L=Lmetal
R=Rmetal
R=Rs
L=Lmetal
R=Rmetal
R=Rs
V(0)
L=Lmetal
R=Rmetal
R=Rs
V
C=Cds
R=Rch
C=Cds
R=Rmetal
L=Lmetal
C=Cds
R=Rs
R=Rs
L=Lmetal
R=Rch
R=Rmetal
L=Lmetal
R=Rch
R=Rs
R=Rmetal
L=Lmetal
R=Rmetal
I2
Figure 5. Distributed effects of metal and channel resistances
For the case of multiple fingers in parallel, the total
impedance becomes:
Z= Z_1finger /nf
Any parasitic seen from the gate has great impact on the
second harmonics in switch circuits. Assuming induced
signals at all gate fingers have the same phase, these
parasitic elements include the connections outside the
mesa of active area and connection lines with gate-bias
resistors. The equivalent parasitic impedance of those
lines must be considered and calculated.
C. Nonlinearity and Dispersion in Channel resistances
Surface charges and their trapping effects in GaAs based
pHEMTs play an important role in dispersion and
transient performances. When the gate is biased below
pinchoff, electrons diffuse to the surface vicinity of gate
periphery and get trapped. These negative trapped surface
charges result in a depletion region beneath the surface
and hence reduce the channel carrier concentration.
Consequently, when the gate bias suddenly changes from
V(W)
negative to positive, the extra negative surface charge
cannot be discharge immediately, and these negative
charges will not follow the voltage change on the gate.
Figure 7 shows the schematic of our dispersion model.
The access resistances, Rs and Rd, are controlled by
voltage, Vsurface, which is determined by the capacitance,
C_surface. This capacitor is charged up by gate voltage
through R_surface. Meanwhile, the Rdtrap-Cdtrap circuit
is used to model drain/source bulk trapping effects.
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-46
-48
-50
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-54
-56
-58
-60
1.70E9 1.75E9 1.80E9 1.85E9 1.90E9 1.95E9 2.00E9
Modeled vs measured H3 for D5-HB
M odeled (s olid) vs m easured H3 (dBm )
M odeled (s olid) vs m eas ured H2 (dBm )
Modeled vs m easured H2 for D5-HB
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-40
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-44
-46
-48
-50
-52
-54
-56
-58
-60
1.70E9 1.75E9 1.80E9 1.85E9 1.90E9 1.95E9 2.00E9
RFf req
HB_meas..f
RFf req
HB_meas..f
Figure 7. Equivalent circuit of access resistance controlled by
surface charge
The equation for current flowing through the resistance
can be modeled as follows:
I_r=Imax*tanh(vds/(Imax*Ro))
Imax=W*(Q_doped+Qledge-Qs-Qsm)*vs
(6)
(7)
where Vs=1e7 cm/s is the electron saturation velocity; W
is the gate width; and Ro is the access low-field resistance.
Therefore, the movable charge Qsm is:
Qsm=Vsurface*C_surface
(8)
and the time constant is Ts=R_surface*C_surface.
IV. MODELED HARMONICS AT SWITCH CONDITION
We validate our multi-gate device model in a real
switch circuit. The circuit used for validation is a GSM
SP4T switch with triple-gate pHEMTs in the enable arm
and TX arms of low and high bands. The model is verified
in terms of harmonics as a function of frequency at both
low GSM band and DCS high band, as shown in Figure 8
and 9.
Modeled vs measured H3 for D5
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-46
-48
-50
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-54
-56
-58
-60
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-46
-48
-50
VII. CONCLUSION
Several key issues in multi-gate pHEMT modeling for
switch applications are addressed, such as CV below
pinchoff, leakages, distributed, and dispersive parasitic.
Their importance in accurate modeling and the
corresponding modeling approaches are discussed. Some
of these issues are associated with floating voltages of
internal channel nodes. Although some hold the opinion
that floating nodes in a channel should be avoided by
setting contacts in internal channels, the effectiveness is in
doubt due to the high channel resistance along the width
direction. Moreover, floating nodes in a channel are
favorable during high power application with capacitance
feed-forward configuration because these floating nodes
can be negatively biased to a greater extent as a result of
self-biasing effect. The model was validated by
comparison of modeled and measured data over a variety
of performances both in device and circuit levels,
particularly in terms of harmonics at low and high bands.
The modeled and measured data show excellent
agreement.
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-56
-58
-60
9.2E8
9.1E8
9.0E8
8.9E8
8.8E8
8.7E8
8.6E8
8.5E8
8.4E8
8.3E8
8.2E8
9.2E8
9.1E8
9.0E8
8.9E8
8.8E8
8.7E8
8.6E8
8.5E8
8.4E8
8.3E8
8.2E8
RFf req
LB_meas..f
Modeled (solid) vs measured H3 (dBm)
Modeled (solid) vs measured H2 (dBm)
Modeled vs measured H2 for D5
-40
Figure 9. Simulated (solid lines) verses measured (dashed) 2nd
harmonics (left) and 3rd harmonics (right) as function of
frequency at low DCS band. Pin=33dBm.
RFf req
LB_meas..f
Figure 8. Simulated (solid lines) verses measured (broken
lines) 2nd harmonics (left) and 3rd harmonics (right) as function
of frequency at low GSM band. Pin=35dBm.
All simulated harmonics agree with measured data
within a range of 2dB. The model is also validated from
other perspectives, including insertion loss, and isolation.
The variation of harmonics vs frequency is due to the
frequency dependence of external impedances of test
circuit, even though their deviations from 50 Ohm are
small but it significantly affects the harmonics.
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