IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 51, NO. 4, APRIL 2004
569
Two-Dimensional Analytical Modeling of Fully
Depleted DMG SOI MOSFET and Evidence for
Diminished SCEs
M. Jagadesh Kumar, Senior Member, IEEE, and Anurag Chaudhry
Abstract—A two–dimensional (2-D) analytical model for the
surface potential variation along the channel in fully depleted
dual-material gate silicon-on-insulator MOSFETs is developed to
investigate the short-channel effects (SCEs). Our model includes
the effects of the source/drain and body doping concentrations,
the lengths of the gate metals and their work functions, applied
drain and substrate biases, the thickness of the gate and buried
oxide and also the silicon thin film. We demonstrate that the
surface potential in the channel region exhibits a step function
that ensures the screening of the drain potential variation by
the gate near the drain resulting in suppressed SCEs like the
hot-carrier effect and drain-induced barrier-lowering (DIBL).
The model is extended to find an expression for the threshold
voltage in the submicrometer regime, which predicts a desirable
“rollup” in the threshold voltage with decreasing channel lengths.
The accuracy of the results obtained using our analytical model is
verified using 2-D numerical simulations.
Index Terms—Device scaling, insulated gate field effect transistors, short-channel effects (SCEs), silicon-on-insulator (SOI)
MOSFET, threshold voltage, two-dimensional (2-D) modeling.
I. INTRODUCTION
I
N KEEPING with the progress in process technology,
CMOS devices have been scaled down, continuously
pushing the MOS technology into the deep-submicrometer
era. However, when the channel length shrinks, the absolute
value of threshold voltage becomes smaller due to the reduced
controllability of the gate over depletion region by the increased
charge-sharing from the source/drain. Therefore, the study of
short-channel effects (SCEs) has assumed a significant role
because both the threshold voltage rolloff at decreasing gate
length as well as drain-induced barrier lowering (DIBL) at
increasing drain voltage pose a serious challenge to the efforts
for down-scaling the CMOS technology.
Thin-film, fully depleted silicon-on-insulator (SOI) MOSFETs offer superior electrical characteristics over bulk MOS
devices, such as reduced junction capacitances, increased
channel mobility, excellent latchup immunity and reduced
SCEs [1]. As a consequence, deep-submicrometer SOI circuit
design and simulation are increasingly becoming important in
very large-scale technology (VLSI) technology research. In
contrast to the bulk device, the front gate of the SOI device
Manuscript received June 23, 2003; revised November 18, 2003. The review
of this paper was arranged by Editor R. Shrivastava.
The authors are with the Department of Electrical Engineering, Indian Institute of Technology, Delhi, 110 016 India (e-mail: mamidala@ieee.org).
Digital Object Identifier 10.1109/TED.2004.823803
has better control over its active device region in the thin film
and hence charge-sharing effects from source/drain regions
are substantially reduced. However, the thin-film thickness has
to reduce to the order of 10 nm to significantly improve the
device performance, which becomes prohibitively difficult to
manufacture and causes large device external resistance due to
shallow source/drain extension (SDE) depths
Long et al. [2] recently demonstrated that the application of
dual-material gate (DMG) in bulk MOSFET leads to a simultaneous transconductance enhancement and suppression of SCEs
due to the introduction of a step function in the channel potential. In a DMG MOSFET, the work function of metal gate
1 (M1) is greater than metal gate 2 (M2) i.e.,
for an
n-channel MOSFET and vice-versa for a p-channel MOSFET.
However, the effects of the DMG structure have not been studied
so far in the case of SOI MOSFETs, which play an important
role in the present day CMOS design. The aim of this paper is,
therefore, to study for the first time the potential benefits offered by the DMG gate in suppressing the SCEs in SOI MOSFETs using two-dimensional (2–D) modeling. In this paper, an
analytical short-channel model for a fully depleted DMG SOI
MOSFET is presented by solving the 2-D Poisson equation. The
model is used to calculate the surface potential distribution in
the SOI thin film under the two metal gates and to explain the
unique attributes of the DMG structure in suppressing the SCEs
“rollup”
like hot-carrier effect, DIBL and threshold voltage
in SOI MOSFETs. This model thus provides an efficient tool for
design and characterization of the novel DMG SOI MOSFET.
The effects of varying device parameters can easily be investigated using the simple models presented in this paper. The
model results are verified by comparing them with the 2-D simulated results from MEDICI [3].
II. TWO-DIMENSIONAL MODEL FOR SURFACE POTENTIAL
A schematic cross-sectional view of a fully depleted SOI
MOSFET is shown in Fig. 1 with gate metals M1 and M2 of
and
, respectively. Assuming that the impurity
lengths
density in the channel region is uniform, and the influence of
charge carriers and fixed oxide charges on the electrostatics of
the channel can be neglected, the potential distribution in the
silicon thin film, before the onset of strong inversion can be
written as [4]
0018-9383/04$20.00 © 2004 IEEE
for
(1)
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 51, NO. 4, APRIL 2004
1) Electric flux at the gate/front-oxide interface is continuous for both the metal gates
for M1
(5)
for M2
(6)
is the dielectric constant of the oxide,
where
gate oxide thickness, and
is the
and
where
Fig. 1. Cross-sectional view of an n-channel fully depleted DMG SOI
MOSFET.
is the gate-to-source bias voltage,
and
are the front-channel flatband voltages of M1 and
M2, respectively.
2) Electric flux at the interface of buried oxide and the backchannel is continuous for both the metal gates.
where
is the film doping concentration,
is the dielectric
is the film thickness and is the deconstant of silicon,
vice channel length. The potential profile in the vertical direccan be approximated by
tion, i.e., the -dependence of
a simple parabolic function as proposed by Young [4] for fully
depleted SOI MOSFETs
(2)
where
is the surface potential and the arbitrary coeffiand
are functions of only.
cients
In a conventional SOI MOSFET, the gate is made of only
one material, but in the DMG structure, we have two different
materials with different work functions, which are amalgamated
together laterally. Therefore, the flatband voltage for the two
and
, the
gates would be different, as it depends upon
metal work functions of M1 and M2, respectively, which are
given as
for M1
(7)
for M2
(8)
where is the buried oxide thickness,
is the potential function along the backside oxide–silicon interface,
, where
is the substrate
and
bias, and
is the back-channel flatband voltage.
3) Surface potential at the interface of the two dissimilar
metals is continuous
(9)
4) Electric flux at the interface of the two dissimilar metals
is continuous
and
(10)
The semiconductor work function can be written as
5) The potential at the source end is
(11)
where
is the Fermi potential,
is the
is the electron affinity,
is the thermal
silicon bandgap,
voltage, and is the intrinsic carrier concentration.
In the DMG structure, since the gate is divided into two parts,
the potential under gate regions M1 and M2 can be written as
for
for
(3)
6) The potential at the drain end is
(12)
where
is the built-in
potential across the body–source junction. The constants
,
,
, and
in (3) and (4) can be
deduced from the boundary conditions (5)–(8). Substituting their values in (3) and (4) and then in (1) we obtain
(4)
The Poisson’s equation is solved separately under the two gate
regions using the following boundary conditions.
and
(13)
KUMAR AND CHAUDHRY: 2-D ANALYTICAL MODELING OF FULLY DEPLETED DMG SOI MOSFET
where
571
The DIBL effect can be demonstrated by plotting the surface
, as a function of the position along
potential minima
the channel for different drain bias conditions.
The electric field pattern along the channel determines the
electron transport velocity through the channel. The electric
field component in the -direction, under the metal gates M1
and M2 is given as
(18)
and
(19)
The above two equations are useful in examining how the drain
side electric field is modified by the DMG structure.
where
,
and
.
The above equations are simple second-order nonhomogenous differential equations with constant coefficients, which
have a solution of the form
(14)
(15)
and
. Now using boundary condiwhere
tions (9)–(12) to solve for , , and , we obtain the equation shown at the bottom of the page, where
and
. The above expression for surface potential can
be reduced to the form presented in [4] for a single material
, and
gate (SMG) structure upon substituting
in (14).
The minimum potential of the front-channel can be calculated
from (14) as
(16)
The minima occurs at
(17)
and
III. TWO-DIMENSIONAL THRESHOLD VOLTAGE MODEL FOR
DMG FD SOI MOSFET
is that value of the gate voltage
The threshold voltage
at which a conducting channel is induced at the surface of SOI
MOSFET. In a fully depleted thin film SOI, it is desirable that
the front channel turns on before the back channel. Therefore,
the threshold voltage is taken to be that value of gate source
, where
is the difference
voltage for which
between the extrinsic Fermi level in the bulk region and the intrinsic Fermi level. In the case of DMG structure, due to the coexistence of metal gates M1 and M2, with different work functions, the surface potential minima is solely determined by the
metal gate with higher work function. So the threshold voltage
at which the minimum surface pois defined as the value of
equals
. Hence, we can determine the value
tential
by solving (16).
of threshold voltage as the value of
and
, we can approximate
and
as
When
and
and upon solving for
, we obtain an expression of the form
for the threshold voltage
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 51, NO. 4, APRIL 2004
where
(a)
and
A significant result of this formulation is the ability to tune the
surface potential by “gate-material engineering.” The dependence of surface potential and hence, threshold voltage on the
difference between the gate material work functions of the two
gate metals can offer another degree of freedom for the SOI transistor design. This has also been observed for the DMG structure
on bulk MOSFETs [5].
IV. RESULTS AND DISCUSSION
To verify the proposed analytical model, the 2-D device simulator MEDICI [3] was used to simulate the surface potential
distribution within the silicon thin film. A fully depleted (FD)
n-channel DMG SOI structure is implemented in MEDICI
having uniformly doped source/drain and body regions. Typical
values of the workfunction of gate metals M1 and M2 are
chosen as 4.77 and 4.1 eV, respectively, for a DMG SOI, and
4.77 eV for the SMG SOI gate workfunction. All the device
parameters of DMG and SMG are equivalent unless otherwise
stated and are given in the figure captions.
In Fig. 2, the calculated and simulated values of surface
potential are plotted against the horizontal distance in the
channel for channel lengths of 0.1 m and 0.2 m at different
drain voltages. It can be seen from the figure that due to the
presence of the DMG, there is no significant change in the
potential under the gate M1 as the drain bias is increased even
for channel lengths up to 100 nm. Hence, the channel region
under M1 is “screened” from the changes in the drain potential,
i.e., the drain voltage is not absorbed under M1, but is under
has only a very small influence
M2. As a consequence,
on drain current after saturation and the drain conductance
is reduced. It is evident from the figure that the shift in the
point of the minimum potential is almost zero irrespective of
the applied drain bias. This is a clear indication that the DIBL
effect is considerably reduced for the DMG SOI MOSFET. The
model predictions correlate well with the simulation results
proving the accuracy of our proposed analytical model.
In Fig. 3, the electric distribution along the channel near
the drain is shown for SMG and DMG SOI MOSFETs with a
m. It is evident from the figure that
channel length
(b)
Fig. 2. (a) Surface channel potential profiles of a fully depleted DMG
SOI MOSFET obtained from the analytical model and MEDICI simulation
for different drain biases with a channel length L = 0:1 m. (b) Surface
channel potential profiles of a fully depleted DMG SOI MOSFET obtained
from the analytical model and MEDICI simulation for different drain biases
with a channel length L = 0:2 m. The screening effect is distinctly visible.
The parameters used are t = 5 nm, t = 450 nm, t = 150 nm, and
V
= 0 V.
Fig. 3. Longitudinal electric field along the channel toward the drain end
obtained from the analytical model and MEDICI simulation in DMG SOI
and SMG-SOI MOSFETs with a channel length L = 0:4 m and a drain
bias V
= 1:75 V. The parameters used are V
= 0:15 V, t = 5 nm,
t = 400 nm, t = 100 nm, V
= 0 V, and N = 6 10 cm .
2
the presence of a lower function gate at the drain side reduces
the peak electric field considerably. This reduction of the
electric field experienced by the carriers in the channel can be
interpreted as the reduction of the hot-carrier effect at the drain
KUMAR AND CHAUDHRY: 2-D ANALYTICAL MODELING OF FULLY DEPLETED DMG SOI MOSFET
573
Fig. 4. Variation of surface potential with position in channel for different
L ) constant.
combination of gate lengths L and L , keeping the sum (L
+
(a)
Fig. 5. Variation of the front-channel minimum potential with channel length
L ( L L ) for fully depleted DMG SOI MOSFETs for different silicon
thin-film thickness, and with L constant at 0.1 m. The parameters used are
V
: V, t
nm, and V
nm, t
V.
= +
= 0 15
=5
= 400
=0
end. As shown in the figure, the results from the analytical
model are in close proximity with the simulation results.
Fig. 4 shows the variation of surface potential with the
normalized channel position for different combinations of gate
and
of M1 and M2, respectively, keeping the
lengths
sum of total gate length, (
), to be constant. It is seen
from the figure that the position of minimum surface potential,
lying under M1 is shifting toward the source as the length of
gate M1 is reduced. This causes the peak electric field in the
channel to shift more toward the source end and thus there is
a more uniform electric field profile in the channel. Moreover,
it is observed that the channel potential minima for the three
increases, a
cases are not the same. This happens because as
portion of the channel controlled by the gate metal with larger
workfunction [6] is increased.
The variation of the front-channel minimum potential as a
) for fully depleted
function of channel length (
DMG SOI with silicon thin-film thickness
and 50 nm
is shown in Fig. 5. In the case of DMG SOI MOSFETs, the dependence of minimum channel potential on the thin-film thickas comness can be more effectively reduced by decreasing
pared to the SMG SOI MOSFETs. This is due to the existence of
a workfunction difference in the case of DMG SOI MOSFETs.
The validity of model for the minimum surface potential under
and
of
and
the gate for different combinations of
(b)
Fig. 6. (a) Threshold voltage versus channel length for channel lengths up to
mV. (b) Threshold voltage versus channel length for
100 nm with V
mV. The parameters used are t
nm, t
nm, t
V
nm, and V
V.
50
= 50
= 50
=0
=5
= 450
=
is verified by the close match between the analytical results and
the 2-D simulation results [3].
In Fig. 6, the calculated values of threshold voltage as a function of channel-length are compared with those obtained from
2-D simulation [3] extracted from the commonly used maximum transconductance method for two different values of .
It is seen from Fig. 6(a) that the threshold voltage obtained from
the analytical model tracks the simulation values very well but
with an insignificant negative offset of approximately 90 mV
whereas the offset is nearly 20–50 mV for Fig. 6(b). This small
values is due
discrepancy between analytical and simulated
to the two different definitions of threshold voltage used for
and
. As is often done in litercomparison viz.,
as the threshold
ature, in our model we have used
condition while MEDICI calculates the threshold voltage from
condition. The model results when compared
the maximum
to the simulation data, however, justify the validity of the model
for channel lengths well up to 100 nm and as can be discerned
from the figures, the predictions are in line with MEDICI results.
In Fig. 7, the effect of “gate-workfunction engineering” on
the threshold voltage is shown for a fully depleted DMG SOI
) 0.5 m for two
MOSFET of channel length (
and
. It is evident that with the indifferent ratios of
creasing workfunction difference, threshold voltage increases
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 51, NO. 4, APRIL 2004
method of tilt-angle evaporation (TAE) [2]. With the CMOS
processing technology aggressively pushing forward, fabricating sub-100-nm feature gate lengths should not preclude the
possibility of realizing the substantial performance gains over
conventional SOI and excellent immunity against SCEs that
the DMG SOI MOSFET promises.
REFERENCES
Fig. 7. Threshold voltage variation with gate workfunction difference with
fixed at 4.1 eV for the DMG SOI MOSFET a with channel length L
( L
L ) of 0.5 m. The parameters used are t
nm, t
nm,
cm .
t
nm, V
V, and N
=
+
= 50
=0
= 6 2 10
=5
= 400
but, for the same workfunction difference a higher
ratio
leads to a corresponding increase in threshold voltage. This is
due to the increasing proportion of channel length , under the
larger workfunction gate M1.
[1] T. Ohno, Y. Kado, M. Harada, and T. Tsuchiya, “Experimental
0.25-m-gate fully depleted CMOS/SIMOX process using a new
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vol. 42, pp. 1481–1486, Aug. 1995.
[2] W. Long, H. Ou, J.-M. Kuo, and K. K. Chin, “Dual material gate
(DMG) field effect transistor,” IEEE Trans. Electron Devices, vol. 46,
pp. 865–870, May 1999.
[3] MEDICI 4.0, Technology Modeling Associates, Palo Alto, CA, 1997.
[4] K. K. Young, “Short-channel effect in fully depleted SOI MOSFETs,”
IEEE Trans. Electron Devices, vol. 36, pp. 399–402, Feb. 1989.
[5] X. Zhou, “Exploring the novel characteristics of hetero-material gate
field-effect transistors (HMGFETs) with gate-material engineering,”
IEEE Trans. Electron Devices, vol. 47, pp. 113–120, Jan. 2000.
[6] X. Zhou and W. Long, “A novel hetero-material gate (HMG) MOSFET
for deep-submicrometer ULSI technology,” IEEE Trans. Electron Devices, vol. 45, pp. 2546–2548, Dec. 1998.
V. CONCLUSION
For the first time, we have examined the effectiveness of the
DMG structure in fully depleted SOI MOSFETs to suppress
SCEs by developing a 2-D analytical model for surface potential and threshold voltage and comparing the results with accurate MEDICI [3] simulations. The calculated values of the surface potential in the silicon thin film obtained from the proposed
model agree well with the simulated results. Our results unambiguously establish that the introduction of the DMG structure
in a fully depleted SOI MOSFET leads to subdued SCEs due
to a step-function in the channel potential profile. The shift in
the surface channel potential minima position is negligible with
increasing drain biases. The electric field in the channel at the
drain end is also reduced leading to reduced hot-carrier effect.
Also, the variation of the minimum channel potential with decreasing thin-film thickness can be more effectively reduced in
the DMG structure at shallow thin-film thicknesses. Further, it
is clearly seen that the DMG structure gives rise to the desirable threshold voltage “rollup” with decreasing channel lengths.
Thus, the introduction of the DMG structure opens up a new
avenue to improve the short-channel behavior of the SOI MOSFETs over their single-gate SOI and the bulk counterparts.
One of the difficulties in integrating DMG structure in the
present CMOS technology maybe the increased constraint
on lithography due to its asymmetric gate structure. Zhou
[5] suggested two fabrication procedures requiring only one
additional mask step for realizing the DMG FET in bulk CMOS
technology. Wong et al. demonstrated a DMG HFET using the
M. Jagadesh Kumar (SM’99) was born in Mamidala, Nalgonda district, Andhra Pradesh, India. He received the M.S. and Ph.D. degrees, both in electrical
engineering from the Indian Institute of Technology
(IIT), Madras, India.
From 1991 to 1994, his postdoctoral research was
in modeling and processing of high-speed bipolar
transistors with Prof. D. J. Roulston, Department
of Electrical and Computer Engineering, University
of Waterloo, Waterloo, ON, Canada. During his
stay at Waterloo, he also collaborated with Prof.
S. G. Chamberlain on amorphous silicon TFTs. From 1994 to 1995, he was with
the Department of Electronics and Electrical Communication Engineering, IIT,
Kharagpur, and later moved to the Department of Electrical Engineering, IIT,
Delhi, where he was made an Associate Professor in 1997. More than once, his
teaching has been rated as “outstanding” by the Faculty Appraisal Committee,
IIT Delhi. His research interests are in VLSI device modeling and simulation,
IC technology, and power semiconductor devices.
Dr. Kumar is a Fellow of the Institute of Electronics and Telecommunication
Engineers (IETE), India.
Anurag Chaudhry received the B.E. degree (with
distinction) in electronics and communication
engineering from Birla Institute of Technology,
Mesra, India, in 1999. He is currently pursuing the
M.S. degree at the Indian Institute of Technology,
Delhi, India.
From 1999 to 2001, he worked as a Design Engineer in the FPGA Group, ST Microelectronics, Ltd.,
Noida, India. His work primarily involved proposing
logic block architecture for an FPGA. His research
interests include modeling and simulation of novel
device structures on SOI MOSFETs.