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SOI Industry Consortium | Fully Depleted SOI technology | December 2010 – Horacio Mendez –Executive Director Page 1 /8

Derived from “ Questions and Answers on Fully Depleted SOI Technology for next generation CMOS ”, by X Cauchy (Soitec) and F Andrieu (Leti) www.soiconsortium.org/pdf/fullydepletedsoi/SOIconsortium_FDSOI_QA.pdf
As the power consumption demands on silicon technology increase exponentially, one thing is clear:
The current path has reached its capability to support it.
At 22nm and below, traditional CMOS on Bulk silicon is highly inefficient to meet the demands of Smart Mobile
Devices. This is because current Bulk planar transistors have reached the physical limit in controlling leakage current and lack of ability to reduce the operating voltage or dynamic power without compromising performance, a major source of wasted battery power. T Skotnicki, in this paper, reviews why FD-SOI is a winning option.
Illustration: courtesy ST
FD-SOI solves, with less process complexity, scaling, leakage and variability issues to further shrink CMOS technology.
Planar Fully Depleted Silicon on Insulator (FD-SOI) technology relies on an ultra-thin layer of silicon over a
Buried Oxide (commonly called BOx). CMOS transistors built into this top silicon layer are Ultra-Thin Body devices and have unique, extremely attractive characteristics. Two flavors of buried oxide can be used: standard thickness (typically 145nm thick as classically in volume production high performance digital chips today – which employ Partially-Depleted SOI), or ultra-thin BOx, for example 10 or 25nm (UTBOx, Ultra-Thin Buried Oxide).
From a physical point of view, the very thin silicon layer enables the silicon under the transistor gate (the body of the transistor) to be fully depleted of charges.
SOI Industry Consortium | Fully Depleted SOI technology | December 2010 – Horacio Mendez –Executive Director Page 2 /8

FD-SOI Transistors vs. Bulk and PD-SOI Transistors
FD-SOI Starting Wafer
The physical laws that rule the FD-SOI transistor architecture lead to the following key advantages for this technology:
• The excellent electrostatic control of the transistor, intrinsic to FD-SOI, acts as a performance booster and enables lower VDD (therefore lower power consumption) whilst reaching remarkable performance,
• FD-SOI strongly reduces the random dopant fluctuation, thus drastically cutting transistor threshold (VT) variability. In particular, this enables stable, dense, and high-yielding SRAM, functional at very low VDDmin
(even in near- or sub-threshold mode with a good SNM),
• FD-SOI is intrinsically Low Leakage and regains good control of Short Channel Effects.
One consequence is the ability to aggressively shrink the gate length, making it easier to fit devices into smaller and smaller pitches and therefore increase logic density to continue Moore’s law.
In addition, FD-SOI transistors (which require no halo/pocket implant) natively offer superior analog behavior.
This comes with other classical advantages of SOI like much-improved Soft-Error Rate, etc.
FD-SOI efficiently solves the equation: Cost of Ownership (CoO) of the finished Integrated Circuit vs. power, performance, area and manufacturability requirements at the next technology nodes. Some key aspects of the
FD-SOI technology (e.g. regarding process complexity, SRAM area/yield trade-off, etc.) have a beneficial impact on the CoO. In addition, optimization programs at SOI wafer manufacturers like Soitec are significantly lowering the cost of SOI as a starting material. It is also worth keeping in mind that the contribution of the finished wafer cost to the final CoO of an IC is mitigated by other important die-level aspects like cost of IC packaging, etc.
Specifically, benefits of FD-SOI that have an impact on CoO include:
• Simplicity of the CMOS fabrication process (reduction in number of masks and process steps).
Plus, lower complexity factor leads to faster yield learning and improved time-to-volume for SoC products.
• Favorable area vs. stability and yield trade-off for SRAMs,
• Less design sign-off margins required, owing to reduced variability,
SOI Industry Consortium | Fully Depleted SOI technology | December 2010 – Horacio Mendez –Executive Director Page 3 /8

• Ability to scale gate length aggressively (benefit of low Short Channel Effects) leading to better logic density and/or less difficulties to fit into a target transistor pitch,
• Potentially lower packaging and cooling cost, owing to lower power dissipation needs, etc.
Factoring in these aspects with starting wafer cost and die level costs, the Cost of Ownership of FD-SOI based ICs is expected to be extremely competitive vs. a (virtual) Bulk counterpart while offering a superior power/performance/area/manufacturability trade-off in view of the target applications.
All indications are that FD SOI is scalable through multiple generations on technology. Leading papers (VLSI and
IEDM conferences) have shown FD-SOI to be scalable down to the 10nm node, based on projected requirements in terms of thickness and uniformity of top silicon and BOx for next nodes compared to current quality of FD-SOI wafers.
Integration of Analog and I/O transistors, with different gate oxides, has been demonstrated on FD-SOI with very good performance. Regarding non-transistor devices : most of them can be ported to ultra-thin SOI either directly or with minor adaptations. There is also the option to keep devices on Bulk if wished, by locally etching off the ultra-thin silicon film and ultra-thin buried oxide.
An alternative candidate transistor architecture to solve the significant scaling challenges of CMOS is FinFET, which is a vertical rather than planar structure, where the gate wraps around a tall ‘fin’. Although very interesting,
FinFET technology is much more challenging in terms of fabrication process and more disruptive at manufacturing level and at design level.
There are essentially no specificities to design on FD-SOI. Design will rely on the same flows as Bulk, updated to integrate FD-SOI-capable SPICE compact models. Note that FD-SOI does not exhibit the Floating Body Effect and is free of peculiarities such as history effect (also know as the 1st/2nd switch effect) and kink effect. This makes the porting of designs from bulk to FDSOI very direct.
Overall, developing an FD-SOI design ecosystem for the 22/20nm node is a fairly transparent task, because FD-
SOI and traditional Bulk design flows are essentially identical.
Additionally, all low power techniques currently employed in classical Bulk CMOS technology can be directly ported to FD-SOI. One special case is Body Biasing, which can be very efficiently adapted to FD-SOI in the form of back-plane biasing, using ultra-thin BOx wafers. Besides, VT adjustments are no longer done via doping adjustments as FD-SOI requires no channel doping (which is very advantageous to solve variability concerns).
Olivier Faynot, in this paper, reports on solutions.
ARM
FDSOI Workshops – Tokyo, Sept. 2010 – San Francisco, Dec. 2010
End Products:
FD-SOI brings Low Power and High Performance. Ideal fit with Smart Mobile Applications.
Design and System-on-Chip Architecture:
Continuity of tools and methodologies used on Bulk CMOS.
Technology:
Solves major roadblocks to further shrink CMOS. Non-disruptive planar approach.
Cost of ownership:
Very competitive position on the Consumer IC market.
SOI Industry Consortium | Fully Depleted SOI technology | December 2010 – Horacio Mendez –Executive Director Page 4 /8

.
Three flavors in CMOS technologies appeared in response to the impossibility of having Low dynamic Power
(LP), High Performance (HP) and Low Static Power (LSTP) in one. But the rapidly growing Mobile market pushes us to reconsider this division. The applications such as smart-phones, µ -PC, tablets, etc, actually require all three features at the same time. This is impossible with conventional Bulk technologies, today even more than it was when the three technology flavors were introduced. It is so because today the Bulk MOSFET is running out of steam. As summarized in the figure below, all traditional speed boosters are not productive any more.
Therefore non-classical device structures (such as FDSOI, FinFET or Nanowires) are seriously considered as
Bulk challengers. Why should they offer more than Bulk ? First of all because they present a much improved electrostatic integrity with respect to Bulk. The common understanding has been that better electrostatics leads to reduced leakages and therefore advantages this kind of structures for LSTP applications. This is very much true, but recently it has been shown that reduced DIBL is also the speed booster, especially when speaking of
LP technologies.
FDSOI offers similar improvement in terms of electrostatics as FinFET and Nanowires, but in addition to that it offers a very efficient body biasing. This is a very unique feature of FDSOI that is reinforced in case of thin box.
This kind of FDSOI structures called UTBB (Ultra Thin Body and BOX) are cumulating benefits in terms of speed from both the improved electrostatics and from the forward body biasing. Consequently, if we benchmark the different technologies in the frame of 20nm LP, the winning solution definitely goes to UTBB SOI. This is shown in the figure below. Therefore, we believe that the expansion of the multimedia portable electronics will require
FDSOI technology to suit the needs of this kind of applications and bring to this market the best the technology can offer today.
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Due to the reduction of Random Dopant Fluctuations, the use of undoped devices is a significant advantage for the variability control. Fig.1 reports the benchmarking of the variability recent published data: planar FDSOI exhibits the best performance compared to Bulk technologies. Global variability is also reduced and Fig.2 reports the required SOI film thickness non-uniformity to keep a global variability at 3% of V
DD
as required in the ITRS roadmap. It has to be noted that already existing SOI wafers are already fulfilling these specifications, meaning that SOI wafer uniformity is not an issue for this technology.
Lower variability, characterized by the Avt parameter, offers the capability to operate at lower voltage as shown in Fig. 3, which drives technology scaling and significant reduction in active and leakage power.
Fig.1: Variability benchmarking Fig.2: SOI film thickness uniformity required for various gate length
Fig. 3: Capability to operate at lower voltage due to lower variability (Avt)
Courtesy: ST Microelectronics
SOI Industry Consortium | Fully Depleted SOI technology | December 2010 – Horacio Mendez –Executive Director Page 6 /8

T
With undoped channel devices, new solutions are required to offer multi-V
T
options, since the V
T
tuning has to be ensured without channel doping adjustment. The gate material workfunction becomes the main factor that adjusts the V
T
value. With thick buried oxide wafers, the use of Mid-gap and Quarter gap metals is mandatory to achieve both Standard, High and Low V
T
devices (SVT, HVT and LVT respectively). The use of UTBOX wafers with a Ground-Plane doping (GP) extends dramatically the possible V
T
values and reduces the complexity as it becomes possible to achieve 3 various VT’s with only 2-quarter gap metals. Very good values of the Back bias effect are obtained with UTBOX and it is found that, contrary to Bulk devices, the Back-bias coefficient is not degraded during the gate length downscaling. This is due to the excellent electrostatic performance. This enables the use of the Low Power design techniques. Back bias effect of 80mV/V are obtained with a T
BOX
25nm, allowing the modulation of the OFF-state leakage current (Fig.5).
of
Fig.4: Multiple V
T
options with thick and thin BOX Fig.5: I
OFF
leakage modulation with Back bias for Low Power operation
SOI Industry Consortium | Fully Depleted SOI technology | December 2010 – Horacio Mendez –Executive Director Page 7 /8

At wafer level the starting ultra thin Si thickness (FD SOI) has to be matched to the subsequent FD CMOS processing. Cleans, sacrificial oxidations remove a few Si monolayers of the SOI layer and it has to be taken into account when specifying the initial ultra thin SOI thickness T
Si
. The targeted channel Si thickness is typically between 5nm – 7nm, the starting SOI thickness is typically 10nm – 15nm.
The SOI thickness is coupled to the V
T substrate induced V
T
of the FDSOI device, thus SOI uniformity is a key parameter to avoid
variability. Uniformity requirements include on-wafer uniformity and wafer-to-wafer uniformity. Both of them combined are classified as layer total thickness variation (LTTV) and define the overall manufacturing process window for thickness uniformity. LTTV has to be achieved at the nanometer or subnanometer range for the UTSOI layer for all wafers and all sites in order to meet the FD specifications. The thickness variation of UTSOI has a direct impact on the device characteristics. Published data of measured V
T
as a function of T
Si
, empirically result in 25mV/nm. From circuit and device considerations the maximum T fluctuation that can be tolerated is to-wafer (WtW) T
SI
reproducibility.
± 5Å with-in-wafer (WiW), total wafer range of the T
Si
Si
non uniformity, and wafer-
Typical WiW T
Si
range (7 sigma) for 300mm substrates for a target T
Si
of 12nm is 8-9Å. UTSOI thickness is measured by UV ellipsometry to avoid interference of the underlying substrate. Best values for WiW range being around 6Å. Fig. 1 shows typical total thickness variation values over a large wafer population.
Thin BOX (<50nm) suppresses the lateral electrostatic coupling between source, drain and channel of the transistor through the thick BOX. The BOX thickness reduction to 10nm – 25nm improves the scalability of the
FDSOI device at almost constant channel silicon thickness down to L gate length for node 11nm.
G
=10nm which corresponds to the targeted
Figure 1.
Measured T
Si
total thickness variation for a large wafer population. Target T
Si
(min-max).
=15nm, total range is 1nm
The BOX thickness T
BOX
and silicon thickness T
Si
are independent parameters for the SOI fabrication and can therefore be adjusted without degrading the properties of the top silicon layer. The oxide quality of ultra thin BOX is very similar to the quality of equivalent gate oxides. The density of interface states is typically ≤ 5x10
10 for both BOX interfaces. Intrinsic breakdown for 10nm BOX is typically of 12.5 MV/cm. cm
-2 eV
-1
Continuous improvement of FD SOI substrate capability for SOI thickness allows for a Wafer-to-Wafer (WtW) distribution of maximum ± 5Å. The target for High Volume Manufacturing (HVM) phase in 2012 is ± 2Å.
Main UTSOI substrate development focus is the improvement of the short-range surface roughness. The improvement achieved through the optimization of the splitting process and surface finishing of the Smart Cut technology result in 2 Å RMS roughness measured by AFM in 30x30 µ m ² scans. At the inspection scale of 2x2
µm
2
AFM scans, results show that UTSOI and polished bulk silicon surface both exhibit a RMS close to 1.5 Å.
The volume manufacturing for UTSOI is planed to ramp up in 4Q of 2011. This FD substrate product roadmap meets the timelines of the 20nm technology platform ramp up.
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