Dual Comparator with
Accurate Reference Output
ADCMP395
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
High accuracy reference output voltage: 1 V ± 0.9%
Single-supply voltage operation: 2.3 V to 5.5 V
Rail-to-rail common-mode input voltage range
Low input offset voltage across VCMR: 1 mV typical
Guarantees comparator output logic low from VCC = 0.9 V to
undervoltage lockout (UVLO)
Operating temperature range: −40°C to +125°C
10-lead mini small outline package (MSOP)
VCC
ADCMP395
REF
REF
INA+
OUTA
INA–
INB+
OUTB
APPLICATIONS
GND
Battery management/monitoring
Power supply detection
Window comparators
Threshold detectors/discriminators
Microprocessor systems
12210-001
INB–
Figure 1.
GENERAL DESCRIPTION
The ADCMP395 is a dual, rail-to-rail input, low power comparator
ideal for use in general-purpose applications. The device
operates from a supply voltage of 2.3 V to 5.5 V and draws a
minimal amount of current. The dual ADCMP395 consumes
only 37.2 µA of supply current. The low voltage and low current
operation of the ADCMP395 make it ideal for battery-powered
systems.
state upon power-up. The comparator generates a logic low
output when the supply voltage is less than the UVLO threshold.
The ADCMP395 features a common-mode input voltage range
of 200 mV beyond the rails, an offset voltage of 1 mV typical
across the full common-mode range, and a UVLO monitor. In
addition, the design of the comparator allows a defined output
The ADCMP395 is available in a 10-lead MSOP package, and is
specified to operate over the −40°C to +125°C extended
temperature range.
Rev. 0
The ADCMP395 incorporates a 1 V ± 0.9% buffered reference
voltage. The reference voltage output can directly connect to the
comparator input to serve as the trip value for precise monitoring
and detection of positive voltage. It can also act as an offset
when monitoring the negative voltage.
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ADCMP395
Data Sheet
TABLE OF CONTENT
Features .............................................................................................. 1
Open-Drain Output ................................................................... 10
Applications ....................................................................................... 1
Power-Up Behavior .................................................................... 10
Functional Block Diagram .............................................................. 1
Crossover Bias Point .................................................................. 10
General Description ......................................................................... 1
Comparator Hysteresis .............................................................. 10
Revision History ............................................................................... 2
Typical Applications ....................................................................... 11
Specifications..................................................................................... 3
Adding Hysteresis....................................................................... 11
Absolute Maximum Ratings ............................................................ 4
Window Comparator for Positive Voltage Monitoring ......... 11
Thermal Resistance ...................................................................... 4
Window Comparator for Negative Voltage Monitoring ....... 12
ESD Caution .................................................................................. 4
Programmable Sequencing Control Circuit............................... 12
Pin Configuration and Function Descriptions ............................. 5
Mirrored Voltage Sequencer Example ..................................... 14
Typical Performance Characteristics ............................................. 6
Threshold and Timeout Programmable Voltage Supervisor 15
Theory of Operation ...................................................................... 10
Outline Dimensions ....................................................................... 16
Basic Comparator ....................................................................... 10
Ordering Guide .......................................................................... 16
Rail-to-Rail Input (RRI) ............................................................ 10
REVISION HISTORY
10/14—Revision 0: Initial Version
Rev. 0 | Page 2 of 16
Data Sheet
ADCMP395
SPECIFICATIONS
VCC = 2.3 V to 5.5 V, TA = −40°C to +125°C, VCMR = −200 mV to VCC + 200 mV, unless otherwise noted. Typical values are at TA = 25°C.
Table 1.
Parameter
POWER SUPPLY
Supply Voltage Range
VCC Quiescent Current
Symbol
Min
VCC
2.3
0.9
ICC
Typ
Max
Unit
Test Conditions/Comments 1
37.2
35.9
5.5
UVLORISE
51.9
49.2
V
V
µA
µA
Guarantees comparator output low
All outputs in high-Z state, VOD = 0.1 V
All outputs low, VOD = 0.1 V
UNDERVOLTAGE LOCKOUT
VCC Rising
Hysteresis
REFERENCE OUTPUT
Reference Output Voltage
UVLORISE
UVLOHYS
2.062
5
2.162
25
2.262
50
V
mV
VREF
0.991
0.991
1
1
1.008
1.008
V
V
COMPARATOR INPUT
Common-Mode Input Range
Input Offset Voltage
VCMR
VOS
−200
VCC + 200
2.5
2.5
5
5
10
±30
±80
±10
mV
mV
mV
mV
mV
nA
nA
nA
nA
TA = −40°C to +85°C
VCMR = −50 mV to VCC + 50 mV
IN+ = IN− = 1 V
VCMR = −50 mV to VCC + 50 mV
VCMR = −50 mV to VCC + 50 mV,
TA = −40°C to +85°C
VCM = 1 V
IOS
IBIAS
Input Hysteresis
VHYST
3
6
4
8
mV
mV
VOL
0.1
0.01
0.3
0.15
150
V
V
nA
VCC = 2.3 V, ISINK = 2.5 mA
VCC = 0.9 V, ISINK = 100 µA
VOUT = 0 V to 5.5 V
80
74
132
1.1
0.15
dB
dB
dB
µs
µs
VOUT = 10% to 90% of VCC
VOUT = 90% to 10% of VCC
4.7
4.9
4.9
9.7
µs
µs
µs
µs
VCM = 1 V, VCC = 2.3 V, VOD = 10 mV
VCM = 1 V, VCC = 5 V, VOD = 10 mV
VCM = 1 V, VCC = 2.3 V, VOD = 10 mV
VCM = 1 V, VCC = 5 V, VOD= 10 mV
4.5
9.5
4.7
5
µs
µs
µs
µs
VCM = 1 V, VCC = 2.3 V, VOD = 10 mV
VCM = 1 V, VCC = 5 V, VOD = 10 mV
VCM = 1 V, VCC = 2.3 V, VOD = 10 mV
VCM = 1 V, VCC = 5 V, VOD = 10 mV
Output Leakage Current
COMPARATOR CHARACTERISTICS
Power Supply Rejection Ratio
Common-Mode Rejection Ratio
Voltage Gain
Rise Time 2
Fall Time2
Propagation Delay
Input Rising2
Channel A
ILEAK
PSRR
CMRR
AV
tR
tF
Input Falling2
Channel A
Channel B
60
50
tPROP_R
Channel B
2
IN+ = IN− = 1 V
IN+ = IN− = 1 V, TA = −40°C to +85°C
Input Offset Current
Input Bias Current
COMPARATOR OUTPUT
Output Low Voltage
1
0.5
0.5
1
1
IREF = ±1 mA, TA = −40°C to +85°C
IREF = ±1 mA
tPROP_F
VOD is overdrive voltage.
RPULL-UP = 10 kΩ, and CL = 50 pF.
Rev. 0 | Page 3 of 16
ADCMP395
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 2.
Parameter
VCC Pin
All INx+ and INx− Pins
All OUTx Pins
Reference Load Current, IREF
OUTx Pins Sink Current, ISINK
Storage Temperature Range
Operating Temperature Range
Lead Temperature (10 sec)
Junction Temperature
Rating
−0.3 V to +6 V
−0.3 V to +6 V
−0.3 V to +6 V
±1 mA
10 mA
−65°C to +150°C
−40°C to +125°C
300°C
150°C
Table 3. Thermal Resistance
Package Type
10-Lead MSOP
ESD CAUTION
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. 0 | Page 4 of 16
θJA
130
Unit
°C/W
Data Sheet
ADCMP395
10
OUTB
VCC 2
ADCMP395
9
GND
INA– 3
TOP VIEW
(Not to Scale)
8
INB–
7
INB+
6
REF
OUTA 1
INA+ 4
NC 5
NOTES
1. NC = NO CONNECT.
12210-002
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
Mnemonic
OUTA
VCC
INA−
INA+
NC
REF
INB+
INB−
GND
OUTB
Description
Comparator A Output, Open Drain.
Device Supply Input.
Comparator A Inverting Input.
Comparator A Noninverting Input.
No Connect. Leave floating.
Reference Output. Use this pin to set up comparator threshold.
Comparator B Noninverting Input.
Comparator B Inverting Input.
Device Ground.
Comparator B Output, Open Drain.
Rev. 0 | Page 5 of 16
ADCMP395
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
2.5
2.5
SAMPLE 1
SAMPLE 2
SAMPLE 3
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
COMMON-MODE VOLTAGE (V)
–2.5
2.3
12210-003
–2.5
–0.5
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
SUPPLY VOLTAGE (V)
Figure 3. Input Offset Voltage (VOS) vs. Common-Mode Voltage (VCM),
VCC = 3.3 V
Figure 6. Input Offset Voltage (VOS) vs. Supply Voltage (VCC), VCM = 1 V
for Various Temperatures
2.4
2.5
VCC = 2.3V
VCC = 3.3V
VCC = 5.5V
2.0
IN+ = IN– + 10mV
VCM = IN– = 1V
2.2
2.0
1.5
OUTPUT VOLTAGE (V)
1.0
0.5
0
–0.5
–1.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
–1.5
0.4
–2.0
–10
5
20
35
50
65
80
95
110
125
TEMPERATURE (°C)
Figure 4. Input Offset Voltage (VOS) vs. Temperature for
Various Supply Voltages, VCM = 1 V
51
49
0
53
TA = +25°C
TA = +85°C
TA = +125°C
TA = –40°C
51
49
45
43
41
5.0
5.5
35
2.0
12210-005
SUPPLY VOLTAGE (V)
4.5
1.2
1.4
1.6
1.8
2.0
2.2
Figure 5. Supply Current (ICC) vs. Supply Voltage (VCC) at Output Low Voltage
for Various Temperatures
TA = +25°C
TA = +85°C
TA = +125°C
TA = –40°C
41
37
4.0
1.0
43
37
3.5
0.8
45
39
3.0
0.6
47
39
2.5
0.4
Figure 7. Output Voltage (VOUT) vs. Supply Voltage (VCC), RPULL-UP = 10 kΩ
47
35
2.0
0.2
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (µA)
53
0
12210-004
–25
12210-007
0.2
–2.5
–40
2.5
3.0
3.5
4.0
SUPPLY VOLTAGE (V)
4.5
5.0
5.5
12210-008
INPUT OFFSET VOLTAGE (mV)
1.5
12210-006
–2.0
SUPPLY CURRENT (µA)
TA = +25°C
TA = +85°C
TA = +125°C
TA = –40°C
2.0
INPUT OFFSET VOLTAGE (mV)
INPUT OFFSET VOLTAGE (mV)
2.0
Figure 8. Supply Current (ICC) vs. Supply Voltage (VCC) at Output High Voltage
for Various Temperatures
Rev. 0 | Page 6 of 16
Data Sheet
51
53
2.3V
3.3V
5.5V
SUPPLY CURRENT (µA)
49
47
45
43
41
47
45
43
41
39
39
37
37
–25
0
25
50
75
100
125
TEMPERATURE (°C)
35
–50
12210-009
SUPPLY CURRENT (µA)
49
35
–50
2.3V
3.3V
5.5V
51
Figure 9. Supply Current (ICC) vs. Temperature at Output High Voltage (VOH)
for Various Supply Voltages (VCC)
–25
0
25
50
75
100
125
TEMPERATURE (°C)
12210-012
53
ADCMP395
Figure 12. Supply Current (ICC) vs. Temperature at Output Low Voltage (VOL)
for Various Supply Voltages (VCC)
3.9
3.8
3.7
3.6
VCC = 2.3V
VCC = 3.3V
VCC = 5.5V
3.5
INPUT HYSTERESIS (mV)
3.1
2.9
2.7
2.5
2.3
1.7
2.3
3.1
2.8
2.6
2.4
TA = +25°C
TA = +85°C
TA = +125°C
TA = –40°C
2.7
3.0
2.2
3.5
3.9
4.3
4.7
5.1
5.5
SUPPLY VOLTAGE (V)
2.0
–50
14
VCC = 2.3V
VCC = 3.3V
VCC = 5.5V
PROPAGATION DELAY (µs)
12
6
5
4
3
2
–50
25
50
75
100
125
Figure 13. Input Hysteresis vs. Temperature, VCM = 1 V
for Various Supply Voltages (VCC)
VCC = 2.3V
VCC = 3.3V
VCC = 5.5V
10
8
6
4
2
–25
0
25
50
75
100
125
TEMPERATURE (°C)
12210-011
PROPAGATION DELAY (µs)
7
0
TEMPERATURE (°C)
Figure 10. Input Hysteresis vs. Supply Voltage (VCC), VCM = 1 V
for Various Temperatures
8
–25
12210-010
1.9
3.2
Figure 11. Propagation Delay vs. Temperature, Low to High,
VOD = 10 mV
0
–50
–25
0
25
50
75
100
125
TEMPERATURE (°C)
Figure 14. Propagation Delay vs. Temperature, High to Low,
VOD = 10 mV
Rev. 0 | Page 7 of 16
12210-014
2.1
12210-013
INPUT HYSTERESIS (mV)
3.4
3.3
ADCMP395
6.0
10
RPULL-UP = 10kΩ
CL = 50pF
VCM = 1V
VCC = 2.3V
VCC = 3.3V
VCC = 5.5V
5.5
5.0
4.5
4.0
3.5
3.0
2.5
8
7
6
5
4
3
20
30
40
50
60
70
80
90
100
INPUT OVERDRIVE VOLTAGE (mV)
Figure 15. Propagation Delay vs. Input Overdrive Voltage, Low to High,
Channel A
12
RPULL-UP = 10kΩ
CL = 50pF
VCM = 1V
10
1
10
12210-115
1.5
10
20
30
40
50
60
70
80
90
100
INPUT OVERDRIVE VOLTAGE (mV)
12210-118
2
2.0
Figure 18. Propagation Delay vs. Input Overdrive Voltage, High to Low,
Channel A
5.0
VCC = 2.3V
VCC = 3.3V
VCC = 5.5V
RPULL-UP = 10kΩ
CL = 50pF
VCM = 1V
4.5
VCC = 2.3V
VCC = 3.3V
VCC = 5.5V
4.0
PROPAGATION DELAY (µs)
PROPAGATION DELAY (µs)
RPULL-UP = 10kΩ
CL = 50pF
VCM = 1V
VCC = 2.3V
VCC = 3.3V
VCC = 5.5V
9
PROPAGATION DELAY (µs)
PROPAGATION DELAY (µs)
Data Sheet
8
6
4
3.5
3.0
2.5
2.0
1.5
1.0
2
30
50
70
90
INPUT OVERDRIVE VOLTAGE (mV)
Figure 16. Propagation Delay vs. Input Overdrive Voltage, Low to High,
Channel B
30
50
70
90
INPUT OVERDRIVE VOLTAGE (mV)
Figure 19. Propagation Delay vs. Input Overdrive Voltage, High to Low,
Channel B
200
18
VCC = 3.3V
190 CL = 50pF
VCC = 3.3V
CL = 50pF
OUTPUT VOLTAGE FALL TIME (µs)
16
14
12
10
8
6
4
2
180
170
160
150
140
130
120
110
1
10
PULL-UP RESISTANCE (kΩ)
100
100
12210-016
0
Figure 17. Output Voltage Rise Time (tR) vs. Pull-Up Resistance (RPULL-UP)
1
10
PULL-UP RESISTANCE (kΩ)
100
12210-018
OUTPUT VOLTAGE RISE TIME (µs)
0
10
12210-300
0
10
12210-301
0.5
Figure 20. Output Voltage Fall Time (tF) vs. Pull-Up Resistance (RPULL-UP)
Rev. 0 | Page 8 of 16
ADCMP395
1.008
1.006
1.006
1.004
1.004
1.002
1.002
0.998
0.998
0.996
0.996
0.994
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
ISOURCE (mA)
0.994
0.2
1.010
1.008
1.008
1.006
1.006
1.004
1.004
VREF (V)
1.000
0.998
0.996
0.994
0.994
0.992
0.992
–10
20
5
35
50
65
80
95
110
125
TEMPERATURE (°C)
0.990
2.3
1.4
1.6
1.8
2.0
2.8
3.3
3.8
4.3
4.8
5.3
Figure 25. Reference Voltage (VREF) vs. Supply Voltage (VCC)
16
VCC = 2.3V
VCC = 3.3V
VCC = 5.5V
600
1.2
VCC (V)
Figure 22. Reference Voltage (VREF) vs. Temperature, VCC = 3.3 V
700
1.0
1.002
0.996
–25
0.8
1.000
0.998
0.990
–40
0.6
Figure 24. Reference Voltage (VREF) vs. Sink Current (ISINK) of the REF Pin,
VCC = 3.3 V
1.010
1.002
0.4
ISINK (mA)
12210-102
14
12
VOUT (mV)
500
400
300
10
8
6
200
4
100
2
0
1
2
3
4
5
6
7
8
9
10
ISINK (mA)
Figure 23. Output Voltage (VOUT) Low vs. Sink Current (ISINK) for
Various Supply Voltages
0
12210-103
0
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
ISINK (mA)
12210-105
VREF (V)
Figure 21. Reference Voltage (VREF) vs. Source Current (ISOURCE) of the REF Pin,
VCC = 3.3 V
VOUT (mV)
1.000
12210-104
1.000
12210-100
VREF (V)
1.008
12210-101
VREF (V)
Data Sheet
Figure 26. Output Voltage (VOUT) Low vs. Sink Current (ISINK), VCC = 0.9 V
Rev. 0 | Page 9 of 16
ADCMP395
Data Sheet
THEORY OF OPERATION
BASIC COMPARATOR
POWER-UP BEHAVIOR
In its most basic configuration, a comparator can be used to
convert an analog input signal to a digital output signal (see
Figure 27). The analog signal on INx+ is compared to the voltage
on INx−, and the voltage at OUTx is either high or low,
depending on whether INx+ is at a higher or lower potential
than INx−, respectively.
On power-up, when VCC reaches 0.9 V, the ADCMP395 is
asserts an output low logic. When the voltage on the VCC pin
exceeds UVLO, the comparator inputs take control.
VCC
V+
VREF
INx+
OUTx
INx–
Rail-to-rail inputs of this type of architecture in both op amps
and comparators, have a dual front-end design. PMOS devices
are inactive near the VCC rail, and NMOS devices are inactive near
GND. At some predetermined point in the common-mode range,
a crossover occurs. At this point, normally 0.8 V and VCC − 0.8 V,
the measured offset voltages change.
COMPARATOR HYSTERESIS
VOUT
V+
VREF
t
VIN
12210-019
0V
Figure 27. Basic Comparator and Input and Output Signals
RAIL-TO-RAIL INPUT (RRI)
Using a CMOS nonRRI stage (that is, a single differential pair)
limits the input voltage to approximately one gate-to-source
voltage (VGS) away from one of the supply lines. Because VGS for
normal operation is commonly more than 1 V, a single differential
pair input stage comparator greatly restricts the allowable input
voltage. This restriction can be quite limiting with low voltage
supplies. To resolve this issue, RRI stages allow the input signal
range to extend up to the supply voltage range. In the case of the
ADCMP395, the inputs continue to operate 200 mV beyond the
supply rails.
In noisy environments, or when the differential input amplitudes
are relatively small or slow moving, adding hysteresis (VHYST) to
the comparator is often desirable. The transfer function for a
comparator with hysteresis is shown in Figure 28. As the input
voltage approaches the threshold (0 V in Figure 28) from below
the threshold region in a positive direction, the comparator
switches from low to high when the input crosses +VHYST/2. The
new switch threshold becomes −VHYST/2. The comparator
remains in the high state until the −VHYST/2 threshold is crossed
from below the threshold region in a negative direction. In this
manner, noise or feedback output signals centered on the 0 V
input cannot cause the comparator to switch states unless it
exceeds the region bounded by ±VHYST/2.
OUTPUT
VOH
VOL
OPEN-DRAIN OUTPUT
The ADCMP395 has an open-drain output stage that requires
an external resistor to pull up to the logic high voltage level when
the output transistor is switched off. The pull-up resistor must
be large enough to avoid excessive power dissipation, but small
enough to switch logic levels reasonably quickly when the
comparator output is connected to other digital circuitry. The
rise time of the open-drain output depends on the pull-up
resistor (RPULL-UP) and load capacitor (CL) used.
The rise time can be calculated by
tR = 2.2 RPULL-UP CL
(1)
Rev. 0 | Page 10 of 16
–VHYST
2
0V
INPUT
+VHYST
2
12210-020
VIN
CROSSOVER BIAS POINT
Figure 28. Comparator Hysteresis Transfer Function
Data Sheet
ADCMP395
TYPICAL APPLICATIONS
ADDING HYSTERESIS
To add hysteresis, see Figure 29; two resistors are used to create
different switching thresholds, depending on whether the input
signal is increasing or decreasing in magnitude. When the input
voltage increases, the threshold is above VREF, and when the
input voltage decreases, the threshold is below VREF.
WINDOW COMPARATOR FOR POSITIVE VOLTAGE
MONITORING
When monitoring a positive supply, the desired nominal
operating voltage for monitoring is denoted by VM, IM is the
nominal current through the resistor divider, VOV is the
overvoltage trip point, and VUV is the undervoltage trip point.
VCC = 5V
VM
RX
RPULL-UP
VREF = 2.5V
VIN
VPH
OUTx
INx–
OUTA
INA–
RLOAD
INx+
INA+
R1
RY
REF
INB+
R2
OUTB
INB–
12210-021
VPL
RZ
VOUT
Figure 30. Positive Undervoltage/Overvoltage Monitoring Configuration
VIN_HIGH
12210-030
VIN
VIN_LOW
Figure 30 illustrates the positive voltage monitoring input
connection. Three external resistors, RX, RY, and RZ, divide the
positive voltage for monitoring (VM) into the high-side voltage
(VPH) and the low-side voltage (VPL). The high-side voltage is
connected to the INA+ pin and the low-side voltage is
connected to the INB− pin.
Figure 29. Noninverting Comparator Configuration with Hysteresis
The upper input threshold level is given by
VIN_HIGH =
VREF (R1 + R2)
R2
(2)
To trigger an overvoltage condition, the low-side voltage (in this
case, VPL) must exceed the VREF threshold on the INB+ pin.
Calculate the low-side voltage, VPL, by the following:
Assuming RLOAD >> R2, RPULL-UP.

RZ
VPL = VREF = VOV 
 R X + RY + R Z
The lower input threshold level is given by
VIN _ LOW =
VREF (R1 + R2 + RPULL −UP ) − VCC R1
R2 + RPULL −UP
(3)
VHYS
(4)
(5)
In addition,
RX + RY + RZ = VM/IM
The hysteresis is the difference between these voltages levels.
V (R1) R1(VREF + VCC )
= REF
−
R2
R2 + RPULL −UP




(6)
Therefore, RZ, which sets the desired trip point for the
overvoltage monitor, is calculated as
RZ =
(VREF )(VM )
(VOV )(I M )
(7)
To trigger the undervoltage condition, the high-side voltage,
VPH, must be less than the VREF threshold on the INA− pin. The
high-side voltage, VPH, is calculated by
 RY + R Z
VPH = VREF = VUV 
 R X + RY + R Z




(8)
Because RZ is already known, RY can be expressed as
RY =
(VREF )(VM ) − R
(VUV )(I M ) Z
(9)
When RY and RZ are known, RX can be calculated by
RX = (VM/IM) – RY − RZ
(10)
If VM, IM, VOV, or VUV changes, each step must be recalculated.
Rev. 0 | Page 11 of 16
ADCMP395
Data Sheet
Because RZ is already known, RY can be expressed as follows:
WINDOW COMPARATOR FOR NEGATIVE
VOLTAGE MONITORING
Figure 31 shows the circuit configuration for negative supply
voltage monitoring. To monitor a negative voltage, a reference
voltage is required to connect to the end node of the voltage
divider circuit, in this case, REF.
REF
INB+
INB–
RX 
VM  VREF   R
Y
IM
12210-022
VM
RPULL-UP
R5
SEQ
CL
Figure 31. Negative Undervoltage/Overvoltage Monitoring Configuration
R4

 R X  RY
 GND  VREF  VOV 
 R X  RY  R Z


  VOV


(11)
R2
INB+
R1
Figure 32. Programmable Sequencing Control Circuit
Figure 33 shows a simple block diagram for a programmable
sequencing control circuit. The application delays the enable signal,
EN, of the external regulators (LDO x) in a linear order when
the open-drain signal (SEQ) changes from low to high impedance.
The ADCMP395 has a defined output state during startup, which
prevents any regulator from turning on if VCC is still below the
UVLO threshold.
IN
OUT
LDO 1
EN
VREF /VCC
To trigger an undervoltage condition, the monitored voltage
must be less than the nominal voltage in terms of magnitude,
and the low-side voltage (in this case, VNL) on the INB− pin
must be more positive than ground. Calculate the low-side
voltage, VNL, by the following:
SEQ
GND
t1
t2
t3
t4
OUT
LDO 2
EN
1.8V
GND
IN
OUT
LDO 3
EN
2.5V
GND
IN
OUT
LDO 4
EN
GND
(14)
3.0V
GND
IN
(13)

  VUV


OUT1
INB–
V1
Therefore, RZ, which sets the desired trip point for the
overvoltage monitor, is calculated by
 VREF VM  VREF 
RZ 
I M VOV  VREF 
U2
OUT2
INA–
V2
(12)
IM
OUT3
INA+
3.3V


RX
VNL  GND  VREF  VUV 
R

 X RY  R Z

INB+
R3
In addition,
VM  VREF 
OUT4
INB–
V3
To monitor a negative voltage level, the resistor divider circuit
divides the voltage differential level between VREF and the
negative supply voltage into the high-side voltage, VNH, and the
low-side voltage, VNL. The high-side voltage, VNH, is connected
to INA+, and the low-side voltage, VNL, is connected to INB−.
To trigger an overvoltage condition, the monitored voltage must
exceed the nominal voltage in terms of magnitude, and the
high-side voltage (in this case, VNH) on the INA+ pin must be
more negative than ground. Calculate the high-side voltage,
VNH, by using the following formula:
U1
INA+
INA–
V4
Equation 7, Equation 9, and Equation 10 need some minor
modifications. The reference voltage, VREF, is added to the
overall voltage drop; therefore, it must be subtracted from VM,
VUV, and VOV before using each of them in Equation 7, Equation 9,
and Equation 10.
R X  RY  RZ 
(16)
VREF /VCC
OUTB
RX
VNH
 RZ
The circuit shown in Figure 32 is used to control power supply
sequencing. The delay is set by the combination of the pull-up
resistor (RPULL-UP), the load capacitor (CL), and the resistor
divider network.
OUTA
RY
VNL
When RY and RZ are known, RX is then calculated by
PROGRAMMABLE SEQUENCING CONTROL CIRCUIT
INA+
INA–
(15)
12210-125
VNH
 VREF VM  VREF 
 RZ
I M VUV  VREF 
1.2V
12210-124
RZ
RY 
Figure 33. Simplified Block Diagram of a Programmable
Sequencing Control Circuit
Rev. 0 | Page 12 of 16
Data Sheet
ADCMP395
V2
V1
VC
V3
First, determine the allowable current, IDIV, flowing through the
resistor divider. After the value for IDIV is determined, calculate
R1, R2, R3, R4, and R5 using the following formulas:
V4
L
OUT4
t4
OUT3
t3
t2
R1 =
12210-126
OUT2
OUT1
RDIV =
t1
Figure 34. Programmable Sequencing Control Circuit Timing Diagram
R2 =
When the SEQ signal changes from low to high impedance, the
load capacitor, CL, starts to charge. The time it takes to charge the
load capacitor to the pull-up voltage (in this case, VREF or VCC) is the
maximum delay programmable in the circuit. It is recommended
to have the threshold within 10% to 90% of the pull-up voltage.
Calculate the maximum allowable delay by
tMAX = 2.2RPULL-UPCLOAD
To calculate the voltage thresholds for the comparator, use the
following formulas:

V1 = VREF 1 − e RPULL−UP C L


−t 2

V2 = VREF 1 − e RPULL−UP C L


R4 =
(17)
The delay of each output is changed by changing the threshold
voltage, V1 to V4, when the comparator changes its output state.
−t 1
R3 =








VREF
I DIV
= R1 + R2 + R3 + R4 + R5
V1RDIV
(23)
VREF
V2RDIV
VREF
V3RDIV
VREF
V4RDIV
VREF
− R1
(24)
− R1 − R2
(25)
− R1 − R2 − R3
(26)
R5 = RDIV − R1 − R2 − R3 − R4
−t 4

V4 = VREF 1 − e RPULL−UP C L










(27)
To create a mirrored voltage sequence, add a resistor (RMIRROR)
between the pull-up resistor (RPULL-UP) and the load capacitor
(CL) as shown in Figure 35.
VREF /VCC
(18)
RPULL-UP
R5
SEQ
RMIRROR
CL
(19)
INA+
INA–
V4
R4
U1
OUT4
INB+
INB–
V3
−t 3

V3 = VREF 1 − e RPULL−UP C L


(22)
OUT3
R3
(20)
INA+
INA–
V2
R2
(21)
R1
The threshold voltages can come from a voltage reference or a
voltage divider circuit, as shown in Figure 32.
INB+
INB–
V1
U2
OUT2
OUT1
12210-127
SEQ
Figure 35. Circuit Configuration for a Mirrored Voltage Sequencer
Figure 35 shows the circuit configuration for a mirrored voltage
sequencer. When SEQ changes from low to high impedance, the
response is similar to Figure 34. When SEQ changes from high
to low impedance, the load capacitor (CL) starts to discharge at
a rate set by RMIRROR. The delay of each comparator is dependent
on the threshold voltage previously set for t1 to t4. The result is a
mirrored power-down sequence.
Rev. 0 | Page 13 of 16
ADCMP395
Data Sheet
SEQ
L
V2
V1
V3
V4
V4
OUT4
t4
t5
OUT3
t3
t6
t2
OUT2
OUT1
V3
V1
V2
t7
t1
12210-200
VC
t8
Figure 36. Mirrored Voltage Sequencer Timing Diagram
MIRRORED VOLTAGE SEQUENCER EXAMPLE
The timing diagram for the mirrored voltage sequencer is
shown in Figure 36.
Equation 18 through Equation 21 must account for the additional
resistance, RMIRROR, in the calculations of the voltage thresholds.
To calculate these new thresholds, see Equation 28 through
Equation 31.
−t 1

(
RPULL−UP + R MIRROR )C L

V1 = VREF 1 − e






(28)
−t 2

(R
)C
+R
V2 = VREF 1 − e PULL−UP MIRROR L






(29)
−t 3

V3 = VREF 1 − e (RPULL−UP + R MIRROR )C L






(30)
−t 4

V4 = VREF 1 − e (RPULL−UP + R MIRROR )C L






(31)
RMIRROR provides the mirrored delay by prolonging the discharge
time of the capacitor. The mirrored voltage sequencer uses the
same threshold in Equation 28 to Equation 31 in a decreasing
order. To calculate the exact value of the mirrored delay time,
see Equation 32 through Equation 35.
 V4
t 5 = −R MIRRORC L ln

 VREF




(32)
 V3
t 6 = − R MIRRORC L ln

 VREF




(33)
 V2
t 7 = −R MIRRORC L ln

 VREF




(34)
 V1
t 8 = −R MIRRORC L ln

 VREF




(35)
To illustrate operation of the mirrored voltage sequencer, see
Figure 33 and then consider a system that uses a VREF of 1 V and
requires a delay of 50 ms when SEQ changes from low to high
impedance, and between each regulator when turning on. These
considerations require a rise time of at least 200 ms for the pull-up
resistor (RPULL-UP) and the load capacitor (CL). The sum of the
resistance of RMIRROR and RPULL-UP must be large enough to charge
the capacitor longer than the minimum required delay. For a
symmetrical mirrored power-down sequence, the value of RMIRROR
must be much larger than RPULL-UP. A 10 kΩ RPULL-UP value limits the
pull-down current to 100 µA while giving a reasonable value for
RMIRROR. A typical 1 µF capacitor together with a 150 kΩ RMIRROR
value gives a value of
tMAX = 2.2((160 × 103) × (1 × 10−6)) = 351 ms
(36)
The threshold voltage required by each comparator is set by
Equation 28 to Equation 31. For example,
−50 × 10 −3


160 × 103 × 1 × 10 −6
V1 = VREF 1 − e







where V1 = 268.38 mV.
Therefore, V2 = 464.74 mV, V3 = 608.39 mV, and V4 =
713.5 mV.
Next, consider 10 µA as the maximum current (IDIV) flowing
through the resistor divider network. This current gives the total
resistance of the divider network (RDIV) and the individual
resistor values using Equation 22 to Equation 27, resulting in
the following:
•
•
•
•
•
•
Rev. 0 | Page 14 of 16
RDIV = 100 kΩ
R1 = 26.84 kΩ ≈ 26.7 kΩ
R2 = 19.64 kΩ ≈ 19.6 kΩ
R3 = 14.37 kΩ ≈ 14.3 kΩ
R4 = 10.51 kΩ ≈ 10.5 kΩ
R5 = 28.65 kΩ ≈ 28.7 kΩ
Data Sheet
ADCMP395
Resistor values from the calculation are nonindustry standard,
using industry standard resistor values result in a new RDIV
value of 99.8 kΩ. Due to the discrepancy of the calculated resistor
value to the industry standard value, the threshold of each
comparator also changes. Calculate the new threshold values
by using a simple voltage divider formula:
where V1 =
1 V (26.7 kΩ )
99.8 kΩ
R1
RPULL-UP
OUTA
R2
VIN
Therefore, V2 = 463.93 mV, V3 = 607.21 mV, and V4 = 712.42 mV.
t 1 = −C L (RPULL −UP

where t1 = −1 µF(10 kΩ + 150 kΩ)ln 1 −





(38)
267.54 mV 
 = 49.81 ms.
1

Therefore, t2 = 99.78 ms, t3 = 149.52 ms, and t4 = 199.4 ms.
To calculate t5 through t8, use Equation 32 to Equation 35:
 V4
t 5 = −R MIRRORC L ln

 VREF




RESET
Figure 37. Programmable Threshold and Timeout Circuit
= 267.54 mV.

V1
+ R MIRROR )ln1 −
V
REF

OUTB
12210-129
CT
VREF
(37)
Because the threshold of each comparator has changed, the time
when each comparator changes its output has also changed.
Calculate the new delay values for each comparator by using the
following equation:
VCC
RESET
VTH
tRESET
tRESET
12210-130
V1 = VREFR1/RDIV
VIN
Figure 38. Threshold and Timeout Programmable Voltage Supervisor
Timing Diagram
During startup, the ADCMP395 guarantees a low output state
when VCC is still below the UVLO threshold, preventing the
voltage supervisor from toggling.
When VIN reaches the threshold set by the resistor divider (R1
and R2) and VREF, OUT1 changes from low to high and starts to
charge the timeout capacitor (CT). If VIN is kept above the threshold
voltage and the voltage in CT reaches VREF, OUT2 toggles. If VIN
falls below the threshold voltage while CT is charging, the timeout
capacitor quickly discharges, preventing OUT2 from toggling
while VIN is not stable.
In the condition that VIN is tied to VCC, the circuit operates
when VCC is more than the minimum operating voltage.
 712.42 mV 
 = 50.86 ms.
where t5 = −150 kΩ × 1 µF × ln 

1


The threshold voltage (VTH) is configured by changing the
resistor divider or VREF. Calculate the threshold voltage by
R1 
VTH = VREF 1 +

 R2 
Therefore, t6 = 74.83 ms, t7 = 115.2 ms, and t8 = 197.78 ms.
THRESHOLD AND TIMEOUT PROGRAMMABLE
VOLTAGE SUPERVISOR
Figure 37 shows a circuit configuration for a programmable
threshold and timeout circuit. The timeout, tRESET, defines the
duration that the input voltage (VIN) must be kept above the
threshold voltage to toggle the RESET signal, preventing the
device from operating when VIN is not stable. If VIN falls below
the threshold voltage, the RESET signal toggles quickly.
(39)
Timeout is adjusted by changing the values of the pull-up
resistor or the timeout capacitor. To set the timeout value,
determine the allowable current flowing through RPULL-UP and
IPULL-UP. When IPULL-UP is known, calculate RPULL-UP and CT by the
following formulas:
Rev. 0 | Page 15 of 16
RPULL-UP = VCC/IPULL-UP
CT =
−tRESET
 V
RPULL −UP ln1 − REF
VCC

(40)




(41)
ADCMP395
Data Sheet
OUTLINE DIMENSIONS
3.10
3.00
2.90
10
3.10
3.00
2.90
1
5.15
4.90
4.65
6
5
PIN 1
IDENTIFIER
0.50 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.30
0.15
6°
0°
0.23
0.13
0.70
0.55
0.40
COMPLIANT TO JEDEC STANDARDS MO-187-BA
091709-A
0.15
0.05
COPLANARITY
0.10
Figure 39. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADCMP395ARMZ
ADCMP395ARMZ-RL7
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
Package Description
10-Lead Mini Small Outline Package [MSOP]
10-Lead Mini Small Outline Package [MSOP]
Z = RoHS Compliant Part.
©2014 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12210-0-10/14(0)
Rev. 0 | Page 16 of 16
Package Option
RM-10
RM-10
Branding
LQ4
LQ4