Presented at ASC98, Submitted to IEEE Trans. on Appl. Supercond.
T. Satoh, M. Hidaka and S. Tahara
Fundamental Research Laboratories, NEC Corporation, 34 Miyukigaoka, Tsukuba, Ibaraki 305-8501, Japan
Abstract--A new process is presented for fabricating uniform high-temperature superconducting edge-type Josephson junctions. The junctions were fabricated by an in situ process using loweeee LaSrAlTaO material for both the insulator layer and the substrate. The LaSrAlTaO layer played a role as a mask for in
situ edge fabrication. This process contained no intentional barrier deposition process. These junctions however showed resistively and capacitively shunted junction like current-voltage characteristics and an excellent uniformity. These junctions showed small spreads in the critical current as low as 1 s
= 8% for 100 junctions at 4.2 K.
I. I NTRODUCTION
In the technology of high-temperature superconducting
(HTS) integrated circuits, though a robust fabrication process has been established for metallic low T c
superconducting junctions [1], a reproducible fabrication process for uniform Josephson junctions has not yet been developed. In most HTS junctions that have artificial barriers, these layers are deposited using such materials as PrBaCuO [2],[3] or Co-doped YBaCuO
[4],[5]. A small 1 s
spread in the critical current (I c
) of around
10% for 10 to 20 HTS edge junctions has been achieved using deposited barriers [4-6].
The deposition process is probably not suitable for the formation of uniform and atomically thin barriers for HTS junctions, because film growth at high temperature is not homogeneous. New types of barrier formation processes must be developed for greater uniformity in HTS Josephson junctions. A recently reported process for fabricating interface-engineered junctions (IEJ) [7] did not include barrier deposition. Instead, the barrier was formed on a YBaCuO surface by structural modification using ion bombardment and vacuum annealing.
The IEJ showed resistively shunted junction like currentvoltage (I-V) characteristics that would be suitable for HTS integrated circuits, as well as improved uniformity; the I c was 1 s
= 8% for 10 junctions.
spread
We have previously studied processes for fabricating HTS integrated circuits, such as Josephson sampler circuits [8].
Our sampler circuit consisted of five edge-type Josephson junctions with deposited PrBaCuO barriers. We have developed an in situ edge fabrication process to improve the uni-
Manuscript received September 15, 1998
This work was carried out by the Superconducting Electron Devices Project under the management of the R&D Association for Future Electron Devices (FED) as a part of the Ministry of International Trade and Industry
(MITI) R&D of Industrial Science and Technology Frontier Program supported by New Energy and Industrial Technology Development Organization
(NEDO).
formity and electrical characteristics of the edge junctions
[2],[6]. We have obtained a 1 s spread in I c
as small as 10% for
12 junctions [6]. Successful operation of HTS Josephson sampler circuits using these junctions has been confirmed [8].
Larger integrated circuits require a smaller I c
spread. To achieve this, we believe junctions are needed that have modified interface barriers. As well as the structurally modified interface junctions such as IEJ, it is also possible to fabricate structurally and chemically modified interface junctions. These junctions could have characteristics, including uniformity, superior to those of the structurally modified interface junctions.
Recently, we have been working with (La
0.30
Sr
0.70
)(Al
0.65
Ta
0.35
)O
3
(LaSrAlTaO) [9],[10], in place of strontium titanate, as the substrate and insulator material. This insulator material is matched to YBaCuO in terms of lattice and thermal expansion, is twin free, and has a relatively low dielectric constant. We have discovered that we can use LaSrAlTaO with our in situ etching process to form Josephson junctions without intentional barrier deposition.
Here we describe our new process for improving the uniformity of HTS edge-type Josephson junctions. This process includes no intentional barrier deposition or intentional vacuum annealing. The essence of our process is that LaSrAlTaO is used as both the substrate and the insulator layer. Even though the junctions were fabricated without barrier deposition, they exhibited resistively and capacitively shunted junction (RCSJ) like characteristics and smaller I c
spreads compared to junctions having deposited barriers. For 100 junctions, an I c
spread as low as 1 s
= 8% was achieved. The formation mechanism and the nature of the barrier are not yet entirely clear. This process has potential for becoming a key technology for HTS integrated circuits.
II. F ABRICATION PROCESS
Our process for fabricating our new junctions was based on the in situ edge fabrication process [2], in which the etching mask was not a photoresist but a patterned insulator layer on the base YBaCuO layer, and the fabricated YBaCuO edge surface was not exposed to air before barrier formation.
Schematic illustrations of key parts of our new process are shown in Fig. 1. The superconducting YBaCuO layers,
LaSrAlTaO insulator layer, and Au layer for the contact pads were all deposited by KrF pulsed laser deposition on a
LaSrAlTaO (001) single crystal substrate. The YBaCuO films were grown in 200 mTorr oxygen at about 700°C, while the
LaSrAlTaO films were grown in 100 mTorr oxygen about 20°C

Presented at ASC98, Submitted to IEEE Trans. on Appl. Supercond.
lower.
First, a 300 nm-thick YBaCuO base layer and a 600 nmthick LaSrAlTaO insulating layer were deposited sequentially on the substrate. The epitaxial LaSrAlTaO layer acted not only as an insulating layer, but also as an etching mask.
The LaSrAlTaO layer was patterned using 400 V Ar ion beam etching with a reflowed AZ6112 photoresist mask that had rounded edges. For photoresist reflow, the sample was baked at about 160°C for 20 min. The Ar ion beam had an incident angle of q
1
= 30° to the substrate surface. The substrate was rotated during the etching.
After the photoresist was removed and the surface was cleaned, the sample was mounted on a water-cooled stage in an
in situ etching chamber, which was connected to the deposition chamber. Then, the edge was etched by Ar-ion milling at 200 V, using the LaSrAlTaO mask (Fig. 1 (a),(b)). The angle of incidence of the Ar ion beam was q
2
= 30 to 45° to the substrate surface, and the substrate was rotated. To prevent oxygen depletion from the YBaCuO edge surface, atomic oxygen activated by microwave was directed at the sample during the in
situ etching. An atomic oxygen flux was obtained by flowing oxygen gas through a quartz tube, in which a microwave discharge was generated using an Evenson cavity operating at 2.45
GHz and 120 W. After the etching, the YBaCuO edge surface was cleaned by Ar-ion milling at 50 V in the same activatedoxygen atmosphere. We fabricated four types of edges parallel to the [100] or [010] axis simultaneously. The angle of the edge was about 25° from the substrate surface.
After fabrication of the edge, the sample was transferred to the deposition chamber without being exposed to air. Then it was heated up to about 700°C in a 200 mTorr O
2
atmosphere over a span of about 45 min. No intentional annealing of the edge was done. A 400 nm-thick YBaCuO counter layer was deposited on the sample (Fig. 1 (c),(d)). No intentional barrier deposition was included in this process.
The YBaCuO counter layer was patterned by ion milling to define the junction width. Finally, a layer of Au was deposited and patterned by lift-off for the contact pads.
Each wafer had four 5 mm x 5 mm chips. Half of the chips contained twelve 4 m m-wide Josephson junctions within a 200 m m x 200 m m square near the center of the chip. The other chips contained series arrays of 100 junctions distributed in an area about 500 m m x 500 m m square.
III. R ESULTS AND D ISCUSSION
Even though the junctions had no intentionally deposited barrier, Josephson junctions were formed at almost 100% yield.
These modified interface junctions exhibited RCSJ-like I-V characteristics with small excess current. Fig. 2 shows a typical
I-V characteristic for the modified interface junction. At low temperature, most of the junctions showed hysteretic behavior that disappeared at about 30 to 40 K. Typical ranges for the junction characteristics were I normal state resistance R n c
=
0.3 to 1.5 mA at 4.2 K and
=
1 to 10
W
at 4.2 K. We observed that I c
increased and R n
decreased with increasing substrate temperature for the counter deposition. But the process parameters controlling I c
and R n
are not fully understood. We believe that these junction parameters are controllable. The critical current-normal state resistance product (I c
R n
) for the junctions was determined to be 1.5 to 2.5 mV at 4.2 K and 0.5
to 0.8 mV at 40 K. Periodic I c
modulation in a magnetic field was observed.
The normal state resistance R n
was for the most part independent of temperature in the range from 4.2 to 70 K. This
R n
(T) behavior was clearly different from that of the junctions with relatively thick PrBaCuO barriers [11], in which the junction characteristics were dominated by carrier hopping via localized states in PrBaCuO. At high voltage, the I-V curves of our junctions showed nonlinearity. Conductance of the junc-
YBaCuO
LaSrAlTaO
(a)
(c)
YBaCuO
YBaCuO barrier
(b) ( d)
Fig.1. Schematic illustrations of key parts of our new process. (a) edge fabrication by ion beam etching using a LaSrAlTaO layer as an etching mask, (b) completion of the edge, (c) YBaCuO deposition, (d) completion of the junction.
Fig.2. Typical I-V characteristic at 4.2 K for the modified interface junction.
(The vertical scale is 1.0 mA/div., and the horizontal scale is 2.0 mV/div.).

Presented at ASC98, Submitted to IEEE Trans. on Appl. Supercond.
2.0
at 4.2 K : 1 at 40 K : 1 s
= 7 % s
=10 %
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0 10 20 30 40 50 60 70
Tem perature (K)
1.5
1.0
0.5
0.0
1 2 3 4 5 6 7 8 9 10 11 12
Junction Number
Fig.4. I c
spread for 12 junctions at 4.2 K and at 40 K. The spreads were 1 s
=
7% at 4.2 K and 10% at 40 K.
Fig.3. Typical dependence of I c on temperature.
tions increased with increasing voltage.
The temperature dependence of I c
for the junctions showed no significant difference from that for the junctions with
PrBaCuO barriers. This was a quasi-linear dependence (Fig. 3), which has been commonly observed in most high T c
junctions
[12], except for Co- and Ca-doped YBaCuO barrier junctions.
This behavior of our junction in terms of R n
(T,V) and I c
(T) is similar to that of the HTS grain-boundary junctions [13]. Such behavior may give clues about the nature of the barrier of our junction.
We now describe the advantages of this junction process. Fig.
4 shows an I c
spread for 12 junctions at 4.2 K and at 40 K. The spread was 1 s
= 7% at 4.2 K. This spread was smaller than that for the junctions with deposited PrBaCuO barriers fabricated in our laboratory. The spread at high temperature was larger, for example 1 s
= 10% at 40 K.
Taking advantage of the hysteresis in the I-V curves at low temperature we also estimated the I c
spreads, using series arrays of edge junctions. Fig. 5(a) shows an I-V curve at 4.2 K for an
100-junction array that has smallest I c
spread of the arrays measured. Each individual I c
value is distinguishable. A histogram showing the I c
5(b). The I c
spread for these junctions is shown in Fig.
spread was 1 s
= 8% for 100 junctions. At elevated temperatures, it was impossible to estimate the I c
spread using the junction array, because the hysteresis in I-V curve disappeared. From the results shown in Fig. 4, the 1 s spread in I c
presumably was nearly 10% for 100 junctions at 40 K.
Though this process is still in early stages of investigation, the uniformity of the junctions has already been found superior to that of junctions having intentionally deposited barriers. We believe that it has potential for becoming a key fabrication process for HTS Josephson junctions.
In formulating our new process, we need to understand the formation mechanism and the nature of the barrier. We presume that the barrier is composed of a structurally and chemically modified YBaCuO layer, formed on the edge surface as in the following scenario.
During the in situ edge fabrication by ion beam etching,
YBaCuO on the edge surface was damaged by ion bombardment. Additionally, etched materials such as YBaCuO and
LaSrAlTaO were redeposited on the edge surface. These redeposited materials mixed with YBaCuO surface material due to ion irradiation. Thus, when the edge was completed, its surface was covered with an amorphous YBaCuO layer containing La,
Sr, Al, and Ta. This precursor layer crystallized and became the barrier while the sample was being heated up to the deposition temperature for the YBaCuO counter layer.
When we used SrTiO
3
or Sr(Al,Ta)O
3
material as the mask for the in situ etching, a PrBaCuO barrier deposition about 10 nm thick was required to make good Josephson junctions. In these cases, the YBaCuO-YBaCuO contacts in the edge geometry exhibited flux flow like I-V curves and a critical current density (J c
) of larger than 10
6
A/cm
2
at 4.2 K, though there must have been some redeposition. The reason Josephson junctions were not formed in these cases is unknown.
This mask-material dependence of the interface properties implies that the presence of La, Sr, Al, Ta in the precursor layer is essential for barrier formation. Moreover, La seemed to be a key element in barrier formation, since the Sr(Al,Ta)O
3
material was not an effective etching mask for the modified interface junctions. The importance of La was also implied in [14], where the authors observed higher R n
and lower J c
values for
La-doped YBaCuO base electrodes compared to YBaCuO base electrodes. Unintentionally modified interfaces may have been formed in their edge junctions, in addition to the deposition of the Co-doped YBaCuO barrier.
Ion-beam-damaged amorphous layers on the edge surface have been studied see, for example, in [15]. The present work suggests that the redeposited material, as well as the amorphous
YBaCuO layer on the edge surface, could have significant in-

Presented at ASC98, Submitted to IEEE Trans. on Appl. Supercond.
2.0
X:20 mV/div.
Y:0.2 mA/div.
1 s
= 8 %
1.5
1.0 mA
1.0
at 4.2 K
0.4 m
0.5
0 mV (a)
0.0
0
(b) at 4.2 K
5 10 15 20 25 30
Number of Junctions
Fig.5. (a) I-V characteristic at 4.2 K for an 100-junction array (The vertical scale is 0.2 mA/div., and the horizontal scale is 20 mV/div.).
(b) Histogram showing the I c
spread for the 100 junctions shown in (a). The spread was 1 s
= 8%.
fluence on the junction properties.
We have presented a process for fabricating modified interface junctions in edge geometry that show excellent uniformity.
The junctions were fabricated by the in situ process, using
LaSrAlTaO material for both the substrate and the insulator layer, acted as a mask for the in situ edge fabrication. Even though this fabrication process contained no intentional barrier deposition process, these junctions exhibited RCSJ-like I-
V characteristics and excellent uniformity. These junctions showed small I c
spreads, as low as 1 s
= 8%, for 100 junctions at 4.2 K. The formation mechanism and the nature of the barrier are as yet unclear. We believe that this process has potential for becoming a key technology in the fabrication of HTS integrated circuits.
The authors would like to thank J. Sone and J. S. Tsai for helpful discussions.
A
IV.
CKNOWLEDGMENT
R
S UMMARY
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