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HD3SS3212, HD3SS3212I
ZHCSDQ7 – MAY 2015
HD3SS3212x 双通道差分 2:1/1:2 USB3.1 复用器/解
解复用器
1 特性
•
1
•
•
•
•
•
•
•
•
•
提供面向支持 USB3.1 第 1 代和第 2 代数据传输速
率的 USB Type-C™ 生态系统的复用器/解复用器
解决方案
兼容 MIPI DSI/CSI、FPDLinkIII、LVDS 和 PCIE
的第 II 代和第 III 代
运行速率高达 10Gbps
-3dB 差分带宽宽达 8GHz 以上
出色动态特性（5GHz 时）
– 串扰 = –32dB
– 断开隔离 = –19dB
– 插入损耗 = –1.6dB
– 回波损耗 = –12dB
双向“复用/解复用”差分开关
支持 0 到 2V 共模电压
单电源电压 VCC：3.3V±10%
0°C 至 70°C 的商用温度范围 (HD3SS3212RKS)
-40°C 至 85°C 的工业温度范围
(HD3SS3212IRKS)
3 说明
HD3SS3212 是一款高速双向无源开关，可采用复用或
解复用两种配置，适用于支持 USB3.1 第 1 代和第 2
代数据传输速率的 USB Type-C™ 应用。 该器件可通
过控制引脚 SEL 在两个差分通道（端口 B 到端口 A，
或者端口 C 到端口 A）间切换。
HD3SS3212 是一款通用模拟差分无源开关，可满足任
何高速接口应用对于 0-2V 共模电压范围和差分幅值高
达 1800mVpp 的差分信令的需求。 该器件采用自适应
跟踪，可确保信道在整个共模电压范围内保持不变。
该器件具有出色的动态特性，可在信号眼图衰减最小的
情况下实现高速转换，并且附加抖动极少。 该器件在
工作模式下的功耗 < 2mW，关断模式下的功耗
< 20µW（可通过 OEn 引脚切换模式）。
器件信息(1)
器件型号
HD3SS3212
HD3SS3212I
2 应用
•
•
•
•
•
•
封装
封装尺寸（标称值）
2.50mm × 4.50mm ×
0.5mm 间距
VQFN (20)
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
USB Type-C™ 生态系统
台式机和笔记本个人电脑 (PC)
服务器/储存区网络
PCI EXPress 背板
共享 I/O 端口
FPDLinkII 和 FPDLinkIII 开关
NC
GND
4 简化电路原理图
1
20
18
B0n
A0n
4
17
B1p
GND
5
16
B1n
VCC
6
15
C0p
A1p
7
14
C0n
A1n
8
13
C1p
SEL
9
12
C1n
11
3
GND
19
A0p
10
2
NC
OEn
B0p
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLASE74
HD3SS3212, HD3SS3212I
ZHCSDQ7 – MAY 2015
www.ti.com.cn
目录
1
2
3
4
5
6
7
8
特性 ..........................................................................
应用 ..........................................................................
说明 ..........................................................................
简化电路原理图 ........................................................
修订历史记录 ...........................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
3
4
8.1
8.2
8.3
8.4
8.5
8.6
8.7
4
4
4
4
5
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
High-Speed Performance Parameters ......................
Switching Characteristics ..........................................
10.1
10.2
10.3
10.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
8
8
8
9
11 Application and Implementation........................ 10
11.1 Application Information.......................................... 10
11.2 Typical Applications .............................................. 13
12 Power Supply Recommendations ..................... 17
13 Layout................................................................... 17
13.1 Layout Guidelines ................................................. 17
13.2 Layout Example .................................................... 17
14 器件和文档支持 ..................................................... 18
14.1
14.2
14.3
14.4
14.5
9 Parameter Measurement Information .................. 6
10 Detailed Description ............................................. 8
相关链接................................................................
社区资源................................................................
商标 .......................................................................
静电放电警告.........................................................
术语表 ...................................................................
18
18
18
18
18
15 机械、封装和可订购信息 ....................................... 18
5 修订历史记录
2
日期
修订版本
注释
2015 年 5 月
*
首次发布。
Copyright © 2015, Texas Instruments Incorporated
HD3SS3212, HD3SS3212I
www.ti.com.cn
ZHCSDQ7 – MAY 2015
6 Device Comparison Table
PACKAGE (1) (2)
OPERATING TEMPERATURE (°C)
(1)
(2)
ORDERABLE PART NUMBER
0 to 70
RKS
20 pins
HD3SS3212RKSR
–40 to 85
RKS
20 pins
HD3SS3212IRKSR
For the most current package and ordering information, see 机械、封装和可订购信息.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
7 Pin Configuration and Functions
NC
GND
RKS Package
20-Pin VQFN
Top View
1
20
18
B0n
A0n
4
17
B1p
GND
5
16
B1n
VCC
6
15
C0p
A1p
7
14
C0n
A1n
8
13
C1p
SEL
9
12
C1n
11
3
GND
19
A0p
10
2
NC
OEn
B0p
Pin Functions
PIN
NAME
NO.
TYPE (1)
DESCRIPTION
VCC
6
P
3.3-V power
OEn
2
I
Active-low chip enable
L: Normal operation
H: Shutdown
A0p
3
I/O
Port A, channel 0, high-speed positive signal
A0n
4
I/O
Port A, channel 0, high-speed negative signal
GND
5, 11, 20
G
Ground
A1p
7
I/O
Port A, channel 1, high-speed positive signal
A1n
8
I/O
Port A, channel 1, high-speed negative signal
SEL
9
I
C1n
12
I/O
Port C, channel 1, high-speed negative signal (connector side)
C1p
13
I/O
Port C, channel 1, high-speed positive signal (connector side)
C0n
14
I/O
Port C, channel 0, high-speed negative signal (connector side)
C0p
15
I/O
Port C, channel 0, high-speed positive signal (connector side)
B1n
16
I/O
Port B, channel 1, high-speed negative signal (connector side)
B1p
17
I/O
Port B, channel 1, high-speed positive signal (connector side)
B0n
18
I/O
Port B, channel 0, high-speed negative signal (connector side)
Port select pin. Internally tied to GND via 100-kΩ resistor.
L: Port A to Port B
H: Port A to Port C
B0p
19
I/O
Port B, channel 0, high-speed positive signal (connector side)
NC
1, 10
NC
These are no connect pins but can be tied to VCC or GND
(1)
The high-speed data ports incorporate 20-kΩ pulldown resistors that are switched in when a port is not selected and switched out when
the port is selected.
Copyright © 2015, Texas Instruments Incorporated
3
HD3SS3212, HD3SS3212I
ZHCSDQ7 – MAY 2015
www.ti.com.cn
8 Specifications
8.1 Absolute Maximum Ratings
see
(1)
VCC
Supply voltage
Voltage
Tstg
(1)
MIN
MAX
–0.5
4
UNIT
Differential I/O
–0.5
2.5
Control pins
–0.5
VCC+ 0.5
–65
150
Storage temperature
V
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
8.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VCC
Supply voltage
3
3.6
UNIT
V
Vih
Input high voltage (SEL, OEn pins)
2
VCC
V
Vil
Input low voltage (SEL, OEn pins)
–0.1
0.8
V
Vdiff
High-speed signal pins differential voltage
0
1.8
Vpp
Vcm
High speed signal pins common mode voltage
0
2
TA
Operating free-air/ambient temperature
HD3SS3212RKS
0
70
HD3SS3212IRKS
–40
85
V
°C
8.4 Thermal Information
HD3SS3212
THERMAL METRIC (1)
RKS (VQFN)
UNIT
20 PINS
RθJA
Junction-to-ambient thermal resistance
46.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
41.8
°C/W
RθJB
Junction-to-board thermal resistance
4.4
°C/W
ψJT
Junction-to-top characterization parameter
17.6
°C/W
ψJB
Junction-to-board characterization parameter
1.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
17.6
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
Copyright © 2015, Texas Instruments Incorporated
HD3SS3212, HD3SS3212I
www.ti.com.cn
ZHCSDQ7 – MAY 2015
8.5 Electrical Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.6
0.8
UNIT
mA
5
20
µA
ICC
Device active current
VCC = 3.3 V, OEn = 0
ISTDN
Device shutdown current
VCC = 3.3 V, OEn = VCC
CON
Output ON capacitance
0.6
pF
COFF
Output OFF capacitance
0.8
pF
RON
Output ON resistance
VCC = 3.3 V; VCM = 0 to 2 V; IO = –8
mA
ΔRON
On-resistance match between pairs of the
same channel
RFLAT_ON
On-resistance flatness RON(MAX) –
RON(MAIN)
IIH,CTRL
Input high current, control pins (SEL, OEn)
IIL,CTRL
Input low current, control pins (SEL, OEn)
IIH,HS
Input high current, high-speed pins
[Ax/Bx/Cx][p/n]
VIN = 2 V for selected port, A and B
with SEL = 0, and A and C with SEL
= VCC
IIH,HS
Input high current, high-speed pins
[Ax/Bx/Cx][p/n]
VIN = 2 V for non-selected port, C
with SEL = 0, and B with SEL =
VCC (1)
IIL,HS
Input low current, high-speed pins
[Ax/Bx/Cx][p/n]
(1)
8
Ω
VCC = 3.3 V; –0.35 V ≤ VIN ≤ 2.35 V;
IO = –8 mA
0.5
Ω
VCC = 3.3 V; –0.35 V ≤ VIN ≤ 2.35 V
1
Ω
1
µA
1
µA
1
µA
140
µA
1
µA
5
100
There is a 20-kΩ pull-down in non-selected port.
8.6 High-Speed Performance Parameters
PARAMETER
TEST CONDITION
ƒ = 0.3 MHz
f = 0.625 MHz
IL
BW
RL
OIRR
XTALK
Differential insertion loss
Differential OFF isolation
Differential crosstalk
Copyright © 2015, Texas Instruments Incorporated
TYP
MAX
UNIT
–0.5
-0.55
ƒ = 2.5 GHz
–0.8
ƒ = 4 GHz
–1.4
ƒ = 5 GHz
–1.6
–3-dB bandwidth
Differential return loss
MIN
8
ƒ = 0.3 MHz
–25
ƒ = 2.5 GHz
–13
ƒ = 4 GHz
–13
ƒ = 5 GHz
– 12
ƒ = 0.3 MHz
–75
ƒ = 2.5 GHz
–23
ƒ = 4 GHz
–19
ƒ = 5 GHz
–19
ƒ = 0.3 MHz
–90
ƒ = 2.5 GHz
–35
ƒ = 4 GHz
–32.5
ƒ = 5 GHz
–32
dB
GHz
dB
dB
dB
5
HD3SS3212, HD3SS3212I
ZHCSDQ7 – MAY 2015
www.ti.com.cn
8.7 Switching Characteristics
PARAMETER
MIN
TYP
MAX
UNIT
tPD
Switch propagation delay (see Figure 3)
80
ps
tSW_ON
Switching time SEL-to-Switch ON (see Figure 2)
0.5
µs
tSW_OFF
Switching time SEL-to-Switch OFF (see Figure 2)
0.5
µs
tSK_INTRA
Intra-pair output skew (see Figure 3)
6
ps
tSK_INTER
Inter-pair output skew (see Figure 3)
20
ps
9 Parameter Measurement Information
VCC
RSC = 50 Ÿ
Bxp/Cxp
Axp
RL = 50 Ÿ
RSC = 50 Ÿ
Axn
RL = 50 Ÿ
Bxn/Cxn
SEL
Figure 1. Test Setup
50%
50%
SEL
90%
10%
VOUT
tSW_ON
tSW_OFF
Figure 2. Switch On and Off Timing Diagram
6
Copyright © 2015, Texas Instruments Incorporated
HD3SS3212, HD3SS3212I
www.ti.com.cn
ZHCSDQ7 – MAY 2015
Parameter Measurement Information (continued)
2.6-V Max
50%
VIN
50%
0V
2.6-V Max
50%
VOUT
0V
50%
tPD
VOUTp
50%
VOUTn
TSK_INTRA
B0/C0
VOUT
B1/C1
VOUT
50%
50%
50%
50%
tSK_INTER
Figure 3. Timing Diagrams and Test Setup
Copyright © 2015, Texas Instruments Incorporated
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HD3SS3212, HD3SS3212I
ZHCSDQ7 – MAY 2015
www.ti.com.cn
10 Detailed Description
10.1 Overview
The HD3SS3212 is a generic analog differential passive switch that can work for any high-speed interface
applications requiring a common mode voltage range of 0 to 2 V and differential signaling with differential
amplitude up to 1800 mVpp. It employs adaptive tracking that ensures the channel remains unchanged for the
entire common mode voltage range.
Excellent dynamic characteristics of the device allow high-speed switching with minimum attenuation to the
signal eye diagram with very little added jitter. It consumes <2 mW of power when operational and has a
shutdown mode exercisable by OEn pin resulting <20 µW.
10.2 Functional Block Diagram
10.3 Feature Description
10.3.1 Output Enable and Power Savings
The HD3SS3212 has two power modes, active/normal operating mode and standby/shutdown mode. During
standby mode, the device consumes very-little current to save the maximum power. To enter standby mode, the
OEn control pin is pulled high through a resistor and must remain high. For active/normal operation, the OEn
control pin should be pulled low to GND or dynamically controlled to switch between H or L.
HD3SS3212 consumes <2 mW of power when operational and has a shutdown mode exercisable by the EN pin
resulting <20 µW.
8
Copyright © 2015, Texas Instruments Incorporated
HD3SS3212, HD3SS3212I
www.ti.com.cn
ZHCSDQ7 – MAY 2015
10.4 Device Functional Modes
Table 1. Port Select Control Logic (1)
Port A Channel
(1)
Port B or Port C Channel Connected to Port A Channel
SEL = L
SEL = H
A0p
B0p
C0p
A0n
B0n
C0n
A1p
B1p
C1p
A1n
B1n
C1n
The HD3SS3212 can tolerate polarity inversions for all differential signals on Ports A, B, and C. Take
care to ensure the same polarity is maintained on Port A versus Ports B/C.
Copyright © 2015, Texas Instruments Incorporated
9
HD3SS3212, HD3SS3212I
ZHCSDQ7 – MAY 2015
www.ti.com.cn
11 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
11.1 Application Information
The HD3SS3212 is a generic 2-channel high-speed mux/demux type of switch that can be used for routing highspeed signals between two different locations on a circuit board. The HD3SS3212 supports several high-speed
data protocols with a differential amplitude of <1800 mVpp and a common mode voltage of <2.0 V, as with USB
3.0 and DisplayPort 1.2. The device’s one select input (SEL) pin can easily be controlled by an available GPIO
pin within a system or from a microcontroller.
The HD3SS3212 with its adaptive common mode tracking technology can support applications where the
common mode is different between the RX and TX pair. The two USB3.1 Type C connector applications show
both a host and device side. The cable between the two connectors swivels the pairs to properly route the
signals to the correct pin. The other applications are more generic because different connectors can be used.
Many interfaces require AC coupling between the transmitter and receiver. The 0402 capacitors are the preferred
option to provide AC coupling; 0603 size capacitors also work. Avoid the 0805 size capacitors and C-packs.
When placing AC coupling capacitors, symmetric placement is best. A capacitor value of 0.1 µF is best, and the
value should match for the ±signal pair. The designer should place them along the TX pairs on the system board,
which are usually routed on the top layer of the board.
The AC coupling capacitors have several placement options. Because the switch requires a bias voltage, the
designer must place the capacitors on one side of the switch. If they are placed on both sides of the switch, a
biasing voltage should be provided. Figure 4 shows a few placement options. The coupling capacitors are placed
between the switch and endpoint. In this situation, the switch is biased by the system/host controller.
0.1uF
Connector
Port B
Port C
Device/
Endpoint
TX
0.1uF
Port B
Port C
0.1uF
RX
Connector
RX
HD3SS3212
TX
System/Host
controller
RX
Device/
Endpoint
TX
0.1uF
Figure 4. AC Coupling Capacitors between Switch TX and Endpoint TX
In Figure 5, the coupling capacitors are placed on the host transmit pair and endpoint transmit pair. In this
situation, the switch on top is biased by the endpoint and the lower switch is biased by the host controller.
10
Copyright © 2015, Texas Instruments Incorporated
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www.ti.com.cn
ZHCSDQ7 – MAY 2015
Application Information (continued)
Port B
System/Host
controller
Port C
Device/
Endpoint
TX
0.1uF
Port B
RX
Port C
RX
Connector
HD3SS3212
TX
Connector
RX
0.1uF
Device/
Endpoint
0.1uF
TX
Figure 5. AC Coupling Capacitors on Host TX and Endpoint TX
In the case where the common mode voltage in the system is higher than 2 V, the coupling capacitors are placed
on both sides of the switch (shown in Figure 6). A biasing voltage of <2 V is required in this case.
VBIAS
Port B
VBIAS
RX
Port C
Device/
Endpoint
TX
Port B
Port C
Connector
System/Host
controller
HD3SS3212
TX
Connector
RX
VBIAS can be GND
Capacitor and Resistor values depend upon application
RX
Device/
Endpoint
TX
Figure 6. AC Coupling Capacitors on Both Sides of Switch
The HD3SS3212 can be used with the USB Type C connector to support the connector’s flip ability. Figure 7
provides the generic location for the AC coupling capacitors for this application.
Copyright © 2015, Texas Instruments Incorporated
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HD3SS3212, HD3SS3212I
ZHCSDQ7 – MAY 2015
www.ti.com.cn
Application Information (continued)
Down Facing Port
RX±
RX1±
RX+
TX1+
RX±
0.1 µF
RX1±
TX2+
TX2±
RX2+
0.1 µF
TX1±
0.1 µF
RX2+
RX2±
HD3SS3212
RX
HD3SS3212
RX+
TX1±
RX1+
TX±
System/Host
Controller
RX1+
Type C Connector
TX
TX1+
Type C Connector
TX+
Up Facing Port
RX
Hub
TX+
TX±
TX
TX2+
RX2±
TX2±
0.1 µF
Figure 7. AC Coupling Capacitors for USB Type C
12
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www.ti.com.cn
ZHCSDQ7 – MAY 2015
11.2 Typical Applications
11.2.1 Down Facing Port for USB3.1 Type C
HD3SS3212
B0+
SSTXp
SSTXn
0.1 µF
3
0.1 µF
4
7
SSRXp
8
SSRXn
USB Host
2
Optional
9
Controller
10 NŸ
1
10
B0±
A0+
C0+
A0C0±
A1+
B1+
A1B1±
OEn
C1+
SEL
NC
NC
VCC
VCC
0.01 µF
0.1 µF 10 µF
C1±
GND
GND
GND
19
A2
SSTXp1
GND
SSTXn1
GND
B2
SSTXp2
GND
B3
SSTXn2
GND
B11
SSRXp1
18
A3
15
14
17
16
B10
13
A11
12
5
A10
A5
11
20
B5
A1
B12
A12
B1
SSRXn1
SSRXp2
SSRXn2
CC1
CC2
USB C
6
VCC
CC
Controller
Figure 8. Down Facing Port for USB3.1 Type C Connector
11.2.1.1 Design Requirements
The HD3SS3212 can be designed into many different applications. All the applications have certain requirements
for the system to work properly. The HD3SS3212 requires 3.3-V ±10% VCC rail. The OEn pin must be low for
device to work otherwise it disables the outputs. This pin can be driven by a processor. The expectation is that
one side of the device has AC coupling capacitors. Table 2 provides information on expected values to perform
properly.
Table 2. Design Parameters
DESIGN PARAMETER
VCC
AXp/n, BXp/n, CXp/n CM input voltage
VALUE
3.3 V
0 to 2 V
Control/OEn pin max voltage for low
0.8 V
Control/OEn pin min voltage for high
2.0 V
AC coupling capacitor
RBIAS (Figure 8) when needed
100 nF
1 kΩ
11.2.1.2 Detailed Design Procedure
The HD3SS3212 is a high-speed passive switch device that can behave as a mux or demux. Because this is a
passive switch, signal integrity is important because the device provides no signal conditioning capability. The
device can support 2 to 3 inches of board trace and a connector on either end.
To
•
•
•
•
•
design in the HD3SS3212, the designer needs to understand the following.
Determine the loss profile between circuits that are to be muxed or demuxed.
Provide clean impedance and electrical length matched board traces.
Depending upon the application, determine the best place to put the 100-nF coupling capacitor.
Provide a control signal for the SEL and OEn pins.
The thermal pad must be connected to ground.
Copyright © 2015, Texas Instruments Incorporated
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HD3SS3212, HD3SS3212I
ZHCSDQ7 – MAY 2015
•
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See the application schematics on recommended decouple capacitors from VCC pins to ground
11.2.1.3 Application Curves
Figure 9. 10 Gbps Source Eye Diagram
Figure 10. 10 Gbps Output Eye Diagram
11.2.2 Up Facing Port for USB3.1 Type C
HD3SS3212
SSTXp1
GND
SSTXn1
B12
GND
A12
SSTXp2
GND
SSTXn2
B1
GND
SSRXp1
A2
19
A3
18
B2
15 C0+
A1
SSRXn1
SSRXp2
SSRXn2
CC2
USB C
B11
B10
14
17
16
B0±
A0±
C0±
A1+
B1+
A1±
B1±
OEn
A11
13
A10
12
C1±
5
GND
11
GND
20
GND
A5
B5
A0+
C1+
SEL
3
SSRXp
4
SSRXn
7
0.1 µF
8
0.1 µF
SSTXp
SSTXn
USB Device
2
Optional
9
Controller
NC 1
NC 10
10 NŸ
VCC
VCC
CC1
B3
B0+
10 µF 0.1 µF
6
0.01 µF
VCC
CC
Controller
Figure 11. Up Facing Port for USB3.1 USB Type-C Connector
14
Copyright © 2015, Texas Instruments Incorporated
HD3SS3212, HD3SS3212I
www.ti.com.cn
ZHCSDQ7 – MAY 2015
11.2.3 PCIE/SATA/USB
HD3SS3212
B0+
TXp
TXn
0.1 µF
3
0.1 µF
4
B0±
A0+
B1+
A0±
B1±
7
RXp
17
16
C0+ 15
A1±
2
PCIE/USB/
SATA
Optional
18
TXp1
TXn1
RXp1
RXn1
A1+
8
RXn
19
C0±
OEn
9
C1+
SEL
C1±
Controller
GND
VCC
VCC
VCC
VCC
10 NŸ
GND
GND
14
13
12
Con
TXp2
TXn2
RXp2
RXn2
5
Con
11
20
1 6 10
0.01 µF
0.1 µF 0.1 µF 10 µF
VCC
Figure 12. PCIE Motherboard
11.2.4 PCIE/eSATA
HD3SS3212
B0+
3
TXp
4
TXn
7
RXp
8
RXn
MINI CARD
mSATA Con
2
9
Optional
1
10
Controller
10 NŸ
B0±
A0+
B1+
A0±
A1+
A1±
OEn
SEL
0.01 µF
0.1 µF 10 µF
C0+
C0±
C1+
C1±
NC
NC
GND
VCC
VCC
B1±
GND
GND
19
18
15 0.1 µF
14 0.1 µF
17
16
13 0.1 µF
12 0.1 µF
5
11
PCIE Controller
RXp1
RXn1
TXp1
TXn1
RXp2
RXn2
TXp2
TXn2
eSATA Controller
20
6
VCC
Figure 13. PCIE and eSATA Combo
Copyright © 2015, Texas Instruments Incorporated
15
HD3SS3212, HD3SS3212I
ZHCSDQ7 – MAY 2015
www.ti.com.cn
11.2.5 USB/eSATA
HD3SS3212
B0+
3
TXp
4
TXn
7
RXp
8
RXn
USB/eSATA
Con
2
9
Optional
1
10
Controller
10 NŸ
B0±
A0+
B1+
A0±
A1+
A1±
OEn
SEL
0.01 µF
C0+
C0±
C1+
C1±
NC
NC
18
15 0.1 µF
14 0.1 µF
17
16
13 0.1 µF
12 0.1 µF
5
GND
VCC
VCC
B1±
19
GND
GND
11
USB Controller
RXp1
RXn1
TXp1
TXn1
RXp2
RXn2
TXp2
TXn2
eSATA Controller
20
6
0.1 µF 10 µF
VCC
Figure 14. eSATA and USB 3.0 Combo Connector
11.2.6 MIPI Camera Serial Interface
HD3SS3212
B0+
3
D0p
4
D0n
7
CLKp
8
CLKn
CSI RX
Chipset
Optional
2
9
Controller
1
10
10 NŸ
B0±
A0+
B1+
A0±
B1±
0.1 µF 10 µF
18
15
14
CSI Camera
D0p
D0n
CLKp
CLKn
A1+
A1±
OEn
SEL
C0+
C0±
C1+
C1±
NC
NC
GND
VCC
VCC
0.01 µF
19
GND
GND
17
16
13
12
5
11
D0p
D0n
CLKp
CLKn
CSI Camera
20
6
VCC
Figure 15. CSI Camera Array
16
Copyright © 2015, Texas Instruments Incorporated
HD3SS3212, HD3SS3212I
www.ti.com.cn
ZHCSDQ7 – MAY 2015
12 Power Supply Recommendations
The HD3SS3212 does not require a power supply sequence. However, TI recommends that OEn is asserted low
after device supply VCC is stable and in specification. TI also recommends to place ample decoupling capacitors
at the device VCC near the pin.
13 Layout
13.1 Layout Guidelines
On a high-K board, TI always recommends to solder the PowerPAD™ onto the thermal land. A thermal land is
the area of solder-tinned-copper underneath the PowerPAD package. On a high-K board, the HD3SS3212 can
operate over the full temperature range by soldering the PowerPAD onto the thermal land without vias.
On a low-K board, for the device to operate across the temperature range, the designer must use a 1-oz Cu
trace connecting the GND pins to the thermal land. A general PCB design guide for PowerPAD packages is
provided in PowerPAD Thermally-Enhanced Package, SLMA002.
GND
xxx
xxx
xxx
xxx
xxx
2
A0p
100nF
A0n
100nF
A1n
SEL
Match High Speed traces
length as close as possible to
minimize Skew
GND
VCC
NC
GND
A1p
Match High Speed traces
length as close as possible to
minimize Skew
1
OEn
10kQ
OEn and SEL can be controlled
by the microcontroller. OEn
can also be tied to Vcc with
resistor
NC
VCC
13.2 Layout Example
B0p
B0n
B1p
B1n
C0p
C0n
C1p
C1n
Place VCC decoupling caps as
close to VCC pins as possible
Figure 16. HD3SS3212 Basic Layout Example for Application Shown
in Down Facing Port for USB3.1 Type C
版权 © 2015, Texas Instruments Incorporated
17
HD3SS3212, HD3SS3212I
ZHCSDQ7 – MAY 2015
www.ti.com.cn
14 器件和文档支持
14.1 相关链接
以下表格列出了快速访问链接。 范围包括技术文档、支持与社区资源、工具和软件，并且可以快速访问样片或购买
链接。
表 3. 相关链接
器件
产品文件夹
样片与购买
技术文档
工具与软件
支持与社区
HD3SS3212
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
HD3SS3212I
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
14.2 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
14.3 商标
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
14.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
14.5 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、首字母缩略词和定义。
15 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不
对本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
18
版权 © 2015, Texas Instruments Incorporated
重要声明
德州仪器(TI) 及其下属子公司有权根据 JESD46 最新标准, 对所提供的产品和服务进行更正、修改、增强、改进或其它更改， 并有权根据
JESD48 最新标准中止提供任何产品和服务。客户在下订单前应获取最新的相关信息, 并验证这些信息是否完整且是最新的。所有产品的销售
都遵循在订单确认时所提供的TI 销售条款与条件。
TI 保证其所销售的组件的性能符合产品销售时 TI 半导体产品销售条件与条款的适用规范。仅在 TI 保证的范围内，且 TI 认为 有必要时才会使
用测试或其它质量控制技术。除非适用法律做出了硬性规定，否则没有必要对每种组件的所有参数进行测试。
TI 对应用帮助或客户产品设计不承担任何义务。客户应对其使用 TI 组件的产品和应用自行负责。为尽量减小与客户产品和应 用相关的风险，
客户应提供充分的设计与操作安全措施。
TI 不对任何 TI 专利权、版权、屏蔽作品权或其它与使用了 TI 组件或服务的组合设备、机器或流程相关的 TI 知识产权中授予 的直接或隐含权
限作出任何保证或解释。TI 所发布的与第三方产品或服务有关的信息，不能构成从 TI 获得使用这些产品或服 务的许可、授权、或认可。使用
此类信息可能需要获得第三方的专利权或其它知识产权方面的许可，或是 TI 的专利权或其它 知识产权方面的许可。
对于 TI 的产品手册或数据表中 TI 信息的重要部分，仅在没有对内容进行任何篡改且带有相关授权、条件、限制和声明的情况 下才允许进行
复制。TI 对此类篡改过的文件不承担任何责任或义务。复制第三方的信息可能需要服从额外的限制条件。
在转售 TI 组件或服务时，如果对该组件或服务参数的陈述与 TI 标明的参数相比存在差异或虚假成分，则会失去相关 TI 组件 或服务的所有明
示或暗示授权，且这是不正当的、欺诈性商业行为。TI 对任何此类虚假陈述均不承担任何责任或义务。
客户认可并同意，尽管任何应用相关信息或支持仍可能由 TI 提供，但他们将独力负责满足与其产品及在其应用中使用 TI 产品 相关的所有法
律、法规和安全相关要求。客户声明并同意，他们具备制定与实施安全措施所需的全部专业技术和知识，可预见 故障的危险后果、监测故障
及其后果、降低有可能造成人身伤害的故障的发生机率并采取适当的补救措施。客户将全额赔偿因 在此类安全关键应用中使用任何 TI 组件而
对 TI 及其代理造成的任何损失。
在某些场合中，为了推进安全相关应用有可能对 TI 组件进行特别的促销。TI 的目标是利用此类组件帮助客户设计和创立其特 有的可满足适用
的功能安全性标准和要求的终端产品解决方案。尽管如此，此类组件仍然服从这些条款。
TI 组件未获得用于 FDA Class III（或类似的生命攸关医疗设备）的授权许可，除非各方授权官员已经达成了专门管控此类使 用的特别协议。
只有那些 TI 特别注明属于军用等级或“增强型塑料”的 TI 组件才是设计或专门用于军事/航空应用或环境的。购买者认可并同 意，对并非指定面
向军事或航空航天用途的 TI 组件进行军事或航空航天方面的应用，其风险由客户单独承担，并且由客户独 力负责满足与此类使用相关的所有
法律和法规要求。
TI 已明确指定符合 ISO/TS16949 要求的产品，这些产品主要用于汽车。在任何情况下，因使用非指定产品而无法达到 ISO/TS16949 要
求，TI不承担任何责任。
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应用
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www.dlp.com
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www.ti.com.cn/dsp
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IMPORTANT NOTICE
邮寄地址： 上海市浦东新区世纪大道1568 号，中建大厦32 楼邮政编码： 200122
Copyright © 2015, 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
13-Jul-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
HD3SS3212IRKSR
ACTIVE
VQFN
RKS
20
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
HD3212I
HD3SS3212IRKST
ACTIVE
VQFN
RKS
20
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
HD3212I
HD3SS3212RKSR
ACTIVE
VQFN
RKS
20
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
0 to 70
HDS3212
HD3SS3212RKST
ACTIVE
VQFN
RKS
20
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
0 to 70
HDS3212
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
13-Jul-2016
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
重要声明
德州仪器(TI) 及其下属子公司有权根据 JESD46 最新标准, 对所提供的产品和服务进行更正、修改、增强、改进或其它更改， 并有权根据
JESD48 最新标准中止提供任何产品和服务。客户在下订单前应获取最新的相关信息, 并验证这些信息是否完整且是最新的。所有产品的销售
都遵循在订单确认时所提供的TI 销售条款与条件。
TI 保证其所销售的组件的性能符合产品销售时 TI 半导体产品销售条件与条款的适用规范。仅在 TI 保证的范围内，且 TI 认为 有必要时才会使
用测试或其它质量控制技术。除非适用法律做出了硬性规定，否则没有必要对每种组件的所有参数进行测试。
TI 对应用帮助或客户产品设计不承担任何义务。客户应对其使用 TI 组件的产品和应用自行负责。为尽量减小与客户产品和应 用相关的风险，
客户应提供充分的设计与操作安全措施。
TI 不对任何 TI 专利权、版权、屏蔽作品权或其它与使用了 TI 组件或服务的组合设备、机器或流程相关的 TI 知识产权中授予 的直接或隐含权
限作出任何保证或解释。TI 所发布的与第三方产品或服务有关的信息，不能构成从 TI 获得使用这些产品或服 务的许可、授权、或认可。使用
此类信息可能需要获得第三方的专利权或其它知识产权方面的许可，或是 TI 的专利权或其它 知识产权方面的许可。
对于 TI 的产品手册或数据表中 TI 信息的重要部分，仅在没有对内容进行任何篡改且带有相关授权、条件、限制和声明的情况 下才允许进行
复制。TI 对此类篡改过的文件不承担任何责任或义务。复制第三方的信息可能需要服从额外的限制条件。
在转售 TI 组件或服务时，如果对该组件或服务参数的陈述与 TI 标明的参数相比存在差异或虚假成分，则会失去相关 TI 组件 或服务的所有明
示或暗示授权，且这是不正当的、欺诈性商业行为。TI 对任何此类虚假陈述均不承担任何责任或义务。
客户认可并同意，尽管任何应用相关信息或支持仍可能由 TI 提供，但他们将独力负责满足与其产品及在其应用中使用 TI 产品 相关的所有法
律、法规和安全相关要求。客户声明并同意，他们具备制定与实施安全措施所需的全部专业技术和知识，可预见 故障的危险后果、监测故障
及其后果、降低有可能造成人身伤害的故障的发生机率并采取适当的补救措施。客户将全额赔偿因 在此类安全关键应用中使用任何 TI 组件而
对 TI 及其代理造成的任何损失。
在某些场合中，为了推进安全相关应用有可能对 TI 组件进行特别的促销。TI 的目标是利用此类组件帮助客户设计和创立其特 有的可满足适用
的功能安全性标准和要求的终端产品解决方案。尽管如此，此类组件仍然服从这些条款。
TI 组件未获得用于 FDA Class III（或类似的生命攸关医疗设备）的授权许可，除非各方授权官员已经达成了专门管控此类使 用的特别协议。
只有那些 TI 特别注明属于军用等级或“增强型塑料”的 TI 组件才是设计或专门用于军事/航空应用或环境的。购买者认可并同 意，对并非指定面
向军事或航空航天用途的 TI 组件进行军事或航空航天方面的应用，其风险由客户单独承担，并且由客户独 力负责满足与此类使用相关的所有
法律和法规要求。
TI 已明确指定符合 ISO/TS16949 要求的产品，这些产品主要用于汽车。在任何情况下，因使用非指定产品而无法达到 ISO/TS16949 要
求，TI不承担任何责任。
产品
应用
数字音频
www.ti.com.cn/audio
通信与电信
www.ti.com.cn/telecom
放大器和线性器件
www.ti.com.cn/amplifiers
计算机及周边
www.ti.com.cn/computer
数据转换器
www.ti.com.cn/dataconverters
消费电子
www.ti.com/consumer-apps
DLP® 产品
www.dlp.com
能源
www.ti.com/energy
DSP - 数字信号处理器
www.ti.com.cn/dsp
工业应用
www.ti.com.cn/industrial
时钟和计时器
www.ti.com.cn/clockandtimers
医疗电子
www.ti.com.cn/medical
接口
www.ti.com.cn/interface
安防应用
www.ti.com.cn/security
逻辑
www.ti.com.cn/logic
汽车电子
www.ti.com.cn/automotive
电源管理
www.ti.com.cn/power
视频和影像
www.ti.com.cn/video
微控制器 (MCU)
www.ti.com.cn/microcontrollers
RFID 系统
www.ti.com.cn/rfidsys
OMAP应用处理器
www.ti.com/omap
无线连通性
www.ti.com.cn/wirelessconnectivity
德州仪器在线技术支持社区
www.deyisupport.com
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