Transistor Scaling:
The Age of Innovation
Kaizad Mistry
VP, Technology and Manufacturing Group
Intel Corporation
April 2014
Outline
 Transistor Scaling – The Dennard Era
– Moore’s Law
– Dennard Scaling
 Transistor Scaling: The Age of Innovation
– Strain
– High-k/Metal Gate
– Tri Gate
– Dual/Quad Patterning
 Transistor Evolution: The Future
2
Moore’s Law - 1965
“Reduced cost is one of the
big attractions of integrated
electronics, and the cost
advantage continues to
increase as the technology
evolves toward the
production of larger and
larger circuit functions on a
single semiconductor
substrate.”
Electronics, Volume 38, Number 8,
April 19, 1965
Integrated circuits = Lower cost per function
3
The Cost Reduction Engine
that Drives the Industry
1010
10
As the number
of transistors
goes UP
100
10-1
$
10-2
109
108
107
Price per
transistor goes
DOWN
10-3
10-4
10-5
106
105
10-6
104
10-7
103
’70
’80
’90
’00
Source: WSTS/Dataquest/Intel
4
And Enables Energy Efficiency
As the number
of transistors
goes UP
Energy per transistor
10
100
1010
109
10-1
108
10-2
107
10-3
10-4
Energy per
transistor goes
DOWN
106
105
10-5
10-6
104
10-7
103
’70
’80
’90
’00
Source: WSTS/Dataquest/Intel
~ 1 Million Factor Reduction In Energy/Transistor Over 30+ Years
5
Three Decades of Scaling
Contact
1978
22nm SRAM
Cell 2012
1 mm
2012 22nm SRAM cell is dwarfed by a 1978 SRAM cell
CONTACT
29
6
Moore’s Law: circa 2008
Intel® Atom™ - dual-core
Rice – single grain
47 Millions Transistors
45nm node
Hi-k Metal Gate
193 dry Litho
In 2014, on 14nm technology, the above chip would be 1/8 the size
- Much smaller than the grain of rice!
7
Classical Transistor Scaling
Id = W/L * m * Cox * (Vg-Vt)2
Dennard, Gaenssalen, Yu, Rideout, Bassous, LeBlanc, 1974
Classical Scaling drove transistor performance improvement for decades
8
Dimensional Scaling
 Source Wavelength scaling is slowing
Id = W/L * m * Cox * (Vg-Vt)2
9
Mobility Scaling
 Mobility degrades with transistor scaling
Id = W/L * m * Cox * (Vg-Vt)2
T. Ghani VLSI ‘00
10
Gate Oxide Scaling
 SiO2 scaling running out of atoms
 Does Cox stop scaling?
Id = W/L * m * Cox * (Vg-Vt)2
1000
Poly
SiON
100
Silicon
10
1
0.1
1
Gate Leakage (Rel.)
Electrical (Inv) Tox (nm)
10
0.01
350nm 250nm 180nm 130nm
90nm
65nm
11
Voltage Scaling
 As VDD is scaled down below 1V, drive current reduces
sigignificantly if VT cannot be reduced
– Can VT be reduced?
Id = W/L * m * Cox * (Vg-Vt)2
12
Classical Scaling
Id = W/L * m * Cox * (Vg-Vt)2
Dennard, Gaenssalen, Yu, Rideout, Bassous, LeBlanc, 1974
Classical Scaling drove transistor performance improvement for decades
But is it over?
13
Is the End of Scaling Near?
© 2013 Jupiterimages Corp.
14
Outline
 Transistor Scaling – The Dennard Era
– Moore’s Law
– Dennard Scaling
 Transistor Scaling: The Age of Innovation
– Strain
– High-k/Metal Gate
– Tri Gate
– Dual/Quad Patterning
 Transistor Evolution: The Future
15
The Age of Material & Structure Innovation
2003
90 nm
SiGe
2005
65 nm
2007
45 nm
2009
32 nm
2011
22 nm
Gate-Last
High-k
Metal Gate
2nd Gen.
Gate-Last
High-k
Metal Gate
Tri-Gate
SiGe
SiGe
2nd Gen. SiGe
Strained Silicon Strained Silicon
16
New Materials are key enablers
17
Uniaxial Strain
 Uniaxial strain structure has provided >2X improvement
in carrier inversion mobility
Id = W/L * m * Cox * (Vg-Vt)2
High Stress Film
SiGe
SiGe
18
Biaxial Tensile Strain
Biaxial tensile strain studied extensively in 1990s
–
Much of the seminal work on strain with this structure
–
Large electron mobility gain, but...
Two key problems:
n+
Gate
1. Integration difficulties
–
Dislocations
–
Ge Up-diffusion
–
Fast diffusion of extensions
–
VT Shift
–
Cost
2. Poor hole mobility gain
STI
S
Strained Si
D
Relaxed Si1-xGex
Graded Si1-yGey
Si Substrate
19
Biaxial vs. Uniaxial Strain: Electrons
 Electron mobility enhancement similar
– Both cases result from splitting of 6-fold degenerate valleys
<001>
<010>
<100>
D2
D4
20
Biaxial vs. Uniaxial Strain: Holes
 Uniaxial stress more effective than biaxial for hole
mobility improvement
– Simple calculations using peizoresistance coefficients [C.S. Smith,
Phys. Rev., 1954]
40
<110> channel orientation
(001 surface)
% Hole Dm / m
35
30
Longitudinal compressive
25
20
Tranverse tensile
15
10
Compressive stress <001> ~12.5 % Ge
(Biaxial in plane tension)
5
0
0
200
400
 / Stress MPa
600
21
High-k + Metal Gate
Id = W/L * m * Cox * (Vg-Vt)2
 High-k gate dielectrics
enabled inversion charge
to continue scaling
1.0 nm EOT Hi-K
Dual workfunction metal gate
electrodes
 Requires replacement
metal gate flow so that
metal workfunction
materials come AFTER
high temperature steps
22
Replacement Metal Gate Flow - I
 High temperature steps for S/D and strain formation
completed with dummy polysilicon gate
N+
N+
p-well
STI
SiGe
SiGe
N-well
23
Replacement Metal Gate Flow - II
N+
N+
STI
SiGe
p-well
SiGe
N-well
Dummy Poly removal
24
Replacement Metal Gate Flow - III
N+
N+
STI
SiGe
p-well
SiGe
N-well
PMOS WF Metal
25
Replacement Metal Gate Flow - IV
N+
N+
p-well
STI
SiGe
SiGe
N-well
NMOS WF Metal deposition
26
Replacement Metal Gate Flow - V
Low Resistance Al Fill
NMOS WF
N+
N+
High-k
p-well
PMOS WF
STI
SiGe
SiGe
High-k
N-well
High-k + Metal gate transistor formation complete
27
Serendipity
 Strain formation and Hi-k Metal Gate flow interact NICELY
– 50% INCREASE in strain during dummy poly removal
28
Tri-Gate Transistors
 Tri-Gate transistors provide
improved electrostatics
 Enables voltage scaling
 Higher drive current per unit
footprint
Reduced Threshold
Voltage
Channel
Current
Id = W/L * m * Cox * (Vg-Vt)2
(normalized)
Gate Voltage (V)
Reduced
Operating
Voltage
29
Transistor Features
Gate
 Tri-gate transistors
Source/
Drain
 25 nm gate length
 0.9 nm EOT Hi-K
 strained silicon
 Dual workfunction metal
gate electrodes
NMOS
Gate
Source/
Drain
PMOS
30
Excellent short channel effects
1.E-02
0.80V
0.80V
0.05V
0.05V
IDSAT (A/mm)
1.E-03
1.E-04
1.E-05
PMOS
1.E-06
NMOS
1.E-07
1.E-08
1.E-09
SS ~72mV/dec
DIBL ~50 mV/V
-1.0
-0.6
-0.2
SS ~69mV/dec
DIBL ~46 mV/V
0.2
VGS (V)
0.6
1.0
 Low Subthreshold slope and DIBL
31
Short Channel Effects
0.5
NMOS
0.4
32nm
Vds=0.05V
0.3
Vt (V)
0.2
0.1
22nm
0
-0.1
22nm
-0.2
-0.3
-0.4
32nm
PMOS
-0.5
25
30
35
40
Lgate (nm)
 Excellent VT rolloff
– Enables 100mV reduction in Vt
32
Tri-Gate Self-Aligned Double Patterning
1. Pattern Sacrificial
Layer
2. Deposit &
Etch spacer
3. Sacrificial layer
removal / etch
120nm pitch
sacrificial layer
substrate
Spacer
60nm pitch
substrate
substrate
4. Etch
5. Spacer removal
60nm pitch
substrate
substrate
substrate
substrate
Id = W/L * m * Cox * (Vg-Vt)2
17
33
Self-Aligned Contact (SAC)
1. Std process
Thru gate
polish
2. Recess
Gate
3. Fill/Polish
Etch Stop
Metal Gate
Spacer
4. Etch
Contacts
Etch Stop
Contact
 Allows Contact to land on gate without short
– Scaling of alignment tolerances
34
Self-Aligned Contact (SAC)
Misalignment
% die passing
100
80
SAC
Non-SAC
60
40
20
0
-25 -20 -15 -10 -5 0
5 10 15 20 25
Gate - Contact Shift (nm)
 “Infinite” CTG window demonstrated
35
Transistor
Scaling
Continues
130nm
90nm
65nm
45nm
32nm
22nm
36
The Golden Age of Transistor Innovation
2003
90 nm
SiGe
2005
65 nm
2007
45 nm
2009
32 nm
2011
22 nm
Gate-Last
High-k
Metal Gate
2nd Gen.
Gate-Last
High-k
Metal Gate
Tri-Gate
SiGe
SiGe
2nd Gen. SiGe
Strained Silicon Strained Silicon
Strained Silicon
High-k Metal Gate
Tri-Gate
Can innovation driven scaling continue?
37
Outline
 Transistor Scaling – The Dennard Era
– Moore’s Law
– Dennard Scaling
 Transistor Scaling: The Age of Innovation
– Strain
– High-k/Metal Gate
– Tri Gate
– Dual/Quad Patterning
 Transistor Evolution: The Future
38
Enabling a Steady Technology Cadence
TECHNOLOGY GENERATION
2009
22nm
2011
14nm
2013
MANUFACTURING
10nm
2015
7nm
2017
DEVELOPMENT
5nm
2019
Beyond
2020
RESEARCH
To be defined
2007
32nm
Defined
45nm
What to do now
to enable
these future
generations ?
39
How Far
Can We
Go?
Innovation-Enabled Technology
Pipeline is Full
65nm
2005
45nm
2007
32nm
2009
22nm
2011
14nm
2013
MANUFACTURING
10nm
7nm
2015
Beyond …
2017 2019
DEVELOPMENT
III-V
5nm
RESEARCH
3-D
EUV
Interconnects
2021+
Graphene
Dense
Memory
Photonics
Materials
Synthesis
Nanowires
*projected
Our limit to visibility goes out ~10 years
41
Optimizing Choices for Transistors on Multiple Fronts
Energy Band Diagram
Increasing
MOBILITY
Si d
SEM Micrograph
Gate
n-Ge
Source
Strain
Drain
Ge
III-V
InP
CNT
QW
Graphene
InAlAs Barriers
Increasing
COUPLING
Planar
With High K
UTB SOI
(or QW)
Fins
Wires/Ribbons
42
Production 22nm Tri-Gate Transistors
~400,000 atoms
1.E-02
IDSAT (A/mm)
1.E-03
1.E-04
Lg=26nm
0.80V
0.05V
0.05V
1.E-05
PMOS
1.E-06
NMOS
1.E-07
1.E-08
SS ~72mV/dec
DIBL ~50 mV/V
1.E-09
-1.0
-0.6 -0.2
SS ~69mV/dec
DIBL ~46 mV/V
0.2
VGS (V)
36
43
0.80V
C. Auth, VLSI 2012
0.6
1.0
Research Nanowire Transistors
~40,000 atoms
1.E-03
Ids (A/mm)
1.E-05
1.E-07
SS ~ 61 mV/dec
DIBL ~ 10 mV/V
1.E-09
SS ~ 67 mV/dec
DIBL ~ 23 mV/V
1.E-11
Lg=30nm
1.E-13
-1.5
-1
-0.5
0
0.5
1
1.5
Vgs (V)
K. Kuhn, IEDM 2012
44
III-V Progress Scorecard
 Integration of III-V on Si – Feasibility demonstrated using MBE
Intel paper @ IEDM 2007
 Enhancement-mode operation – Feasibility demonstrated
–
–
MIT papers @ IEDM 2006 and 2007
Intel paper @ IEDM 2007
Research on surface prep, novel materials
 Scalability compared to Si devices unknown – In progress
–
–
n+cap
Work started on self-alignment, alternative geometries
Modeling efforts underway at universities and internal
 Manufacturing tool feasibility
– Research tool selected
Source
HiK
S/D
n+cap
InAlAs
Intel paper @ IEDM 2008
Ge PMOS QW devices may be alternatives
 Gate dielectric on III-V layers of interest – Demonstrated
–
HiK
InP
 III-V hole mobility (P-type) not high enough – Strain demo
–
–
S/D
Gate
–
III-V Barrier
In0.7Ga0.3As QW
InAlAs Barrier
In0.53Ga0.47As cap layer
InP etch stop
In0.52Al0.48As top barrier
Drain
40nm gate length
P-channel III-V
In0.7Ga0.3As QW
Gate
P-channel QW with strain
In0.52Al0.48As bottom barrier
45
Future Visibility: Interconnects
Current Status
 Bottoms-up fill okay to about
14nm, barrier is the limiter
 No “better than Cu” option
 <14nm L/S might exceed
dielectric breakdown limit
14nm
filled trench
Needed Focus
 Thin conformal plateable barrier
… or self forming barrier
 Tall vias might use non-Cu
 Non-SiO2 dielectrics
 Exotic long interconnects:
CNT (10’s um), optical (>mm)
5nm conformal Cu
On-chip optical
interconnect
~15nm Cu nanowire
CNT
46
3-D Chip Stacking & Other ways to integrate
+ High density chip-chip
connections
Top Chip
+ Small form factor
TSV
Bottom Chip
+ Combine dissimilar
technologies
Package
? Added cost
? Degraded power delivery,
heat sinking
CPU
TSV
Memory
Package
? Area impact on lower chip
3-D chip stacking using through-silicon vias
47
Beyond 2020 and possible futures
 Conventional fabrication architectures continue
– Individual steps continue as 2D layers
– More and more layers stacked to give increasing function
High resolution
TEM of graphene
Graphene layers can couple together
and create a quantum condensate
Bilayer graphene structure
Theoretically >10000x less power
Source: M. Gilbert et.al J Comput Electron (2009)
48
Our limit to visibility goes out ~10 years
TECHNOLOGY GENERATION
45nm
2007
32nm
2009
MANUFACTURING
22nm
2011
14nm
2013
10nm
2015
DEVELOPMENT
7nm
2017
Beyond
2020
RESEARCH
Carbon Nanotube
~1nm diameter
Graphene
1 atom thick
QW III-V Device
5nm
Not to scale
Nanowire
10 atoms across
5 nm
 Silicon lattice is ~ 0.5nm, hard to imagine good devices
smaller than 10 lattices across – reached in 2020
49
Is the End of Scaling Near?
© 2013 Jupiterimages Corp.
Rumors of my death are greatly exaggerated
- Mark Twain
50
Discussion
51