International Journal of Research in Computer and ISSN (Online) 2278- 5841
Communication Technology, Vol 3, Issue 5, May- 2014 ISSN (Print) 2320- 5156
Process Variation Induced Mismatch Analysis In Sense
Amplifiers
Parita Patel, Sameena Zafar,and Hemant soni
Abstract— Sense amplifier is a very critical peripheral circuit
in memories as its performance strongly affects both memory
access time, and overall memory power dissipation. As the
device dimensions scale below 100nm, the process variations
are increasing and are impacting the circuit design
significantly. In this paper, effects of process variation induced
transistor mismatch on sense amplifier performance are
studied. A comparative study of the effect of mismatch on delay
for different sense amplifier configurations at 45nm technology
is presented.
Index Terms—Channel length, Delay, Threshold voltage, VSA,
CSA
1. INTRODUCTION
Technology scaling has enabled us to integrate large
memory blocks with logic circuits on a single chip.
However, performance of the on chip memory limits the
speed and performance of the overall system. The key
limiting factor is the increasing bit line capacitance, which
results in increased efficient memory designs, both this time
and signal swing on the bit lines need to be minimized. A
sense amplifier is used to generate full rail output voltage
using minimum bit line differential voltage/current.
As CMOS IC fabrication technology becomes more and
more advanced, the control of process variation and
manufacturing uncertainty becomes more and more critical.
The sense amplifier performance degradation due to process
variations and resulting yield loss is more pronounced than
before. It is important for the designer to be able to
understand mismatch effects, since sensing should be done
as fast as possible, subject to sensitivity constraints imposed
by the parameter variations inherent in fabrication process.
For low power applications it is always desirable to have
low bit line differential voltage. However, the bit line
differential voltage has direct impact on yield of the sense
amplifier.
This paper studies the effect of length mismatch and
threshold voltage mismatch on sense amplifier designs at
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45nm CMOS technology. Variations in sensing delay with
transistor mismatch are compared in voltage mode and
current mode sense amplifier. Section 2 gives a brief
introduction to process variations. Section 3 briefly
describes the sense amplifiers used in this study. Section 4
explains experimental setup for mismatch analysis. Section 5
documents the simulation results and conclusions are
presented in section 6.
2. PROCESS VARIATIONS IN SA
The inter-die and intra-die variation in the process
parameters (channel length (L), width (W), and transistor
threshold voltage (Vt) in nano-scale technologies can
significantly degrade the yield of an SRAM design. If Vt
variation between sense transistors is sufficient to overcome
bit differential voltage developed on the bit lines of the SA,
then SA may latch incorrect signal. Thus the V t variation in
the transistors in the SRAM cell causes in read, write, access
and hold failures in the cell. On the other hand, the statistical
variations in the device parameters also result in significant
variation in the sensing delay (difference between the time
sense-amplifier is turned “ON” and the time sense-amplifier
outputs are available) of the sense amplifiers used in
SRAMs and in the worst case may amplify the input signal
in the wrong direction (functional failure due to incorrect
sensing). Access failure in SRAM is defined as the reading
of wrong data during the access of the memory array. The
access failure in an SRAM array can occur due to random Vt
variation in SRAM cell or sense-amplifier. Hence, analysis
of access failure has to consider the impact of both SRAM
cell and sense-amplifiers.
3. Sense amplifiers
This section briefly illustrates the working of the sense
amplifiers used in this study.
A. Voltage Mode Sense Amplifier (VSA)
Sense amplifier implicates the whole memory and is
required to have high performance and high yield which is
actually determined by its robustness. The performance is
determined primarily by the sensing delay. The robustness is
determined by the minimum voltage difference between two
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International Journal of Research in Computer and ISSN (Online) 2278- 5841
Communication Technology, Vol 3, Issue 5, May- 2014 ISSN (Print) 2320- 5156
bit lines that can be correctly sensed (input offset
voltage).Thus the principal design goal in CMOS sense
amplifier design is to lower the sensing delay and to reduce
the input offset voltage at which the sensing is done.
In Fig. 1, we show the design of a basic voltage mode
charged high. This causes nodes A and B to be predischarged to ground. In the evaluation phase, Ysel is
grounded and the current is immediately transported to the
nodes A and B through the drain of P3 and P4. The
difference in the current flowing through A and B will be
equal to the cell current. The sense amplifier is enabled two
inverter delay after the SAen is pulled high during which
bias current flows through the two legs of the sense
amplifier while PMOS (M) keeps the output equalized.
After this two inverters delay, PMOS (M) is disabled and
the differential current flowing through the sense amplifier
causes a differential voltage to be developed at sa and sa#.
This differential voltage is then amplified to CMOS logic
levels by the high-gain positive feedback cross-coupled
inverters.
The sensing delay is relatively insensitive to bit-line
capacitance, as this technique does not depend on
differential discharging of the large bit-line capacitances.
Fig. 1. Voltage mode sense amplifier [1].
SA, The current flow of the differential input transistors N1
and N2 controls the serially connected latch circuit. A small
difference between the currents through N1 and N2 converts
to a large output voltage. A drawback of a latch type sense
amplifier is that once the decision process has started, the
positive feedback completes the transition and the decision
cannot be recovered without resetting the circuit to a meta
stable point.
B. Current Mode Sense Amplifier (CSA)
The current sense amplifier consists of two parts: current
conveyor circuit with unity-gain current transfer
characteristics and the second is the current sense amplifier
that senses the differential current as shown in Fig. 2. The
current conveyor circuit consists of four equally sized
PMOS transistors (P1 to P4) with positive feedback. The
intermediate nodes are pre-equalized using a PMOS to
prevent latching and to ensure same delay for all read cycles.
The current conveyor circuit output is connected to the
second current sense amplifier. All the nodes of the circuit
has been pre-charged to full VDD or pre-discharged to
ground.
The operation of the circuit is in two phases. In pre-charge
phase, bit-lines and the output nodes of sa and sa# are prewww.ijrcct.org
Fig. 2. Current mode sense amplifier [2].
4. EXPERIMENTAL SET UP
The sense amplifier is said to be perfectly balanced or
symmetric when all the transistor parameters on the lefthand side are equal to parameters on the right-hand side. It
is said to be vertically matched when the W/L's of NMOS
and PMOS have been ratioed so that the sense amplifier has
equal pull-up and pull-down capability. For mismatch
analysis, we consider only the variation in channel length
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International Journal of Research in Computer and ISSN (Online) 2278- 5841
Communication Technology, Vol 3, Issue 5, May- 2014 ISSN (Print) 2320- 5156
and threshold voltage of the transistors. Our analysis
assumes that a particular parameter x (where x is either L, W
or Vth of the device), is varied by decreasing the value of
that parameter for the NMOS transistors in the left hand side
of the sense amplifier by ∆x and increasing it by the same
amount for corresponding right hand side transistors. We
assume perfect matching in PMOS transistors while
performing mismatch analysis of NMOS transistors and
vice-versa. In all sense amplifiers total width of all the
transistors is kept nearly same for fair comparison.
Simulations are carried out for 45nm CMOS technology,
using Predictive Technology Model (PTM).
Fig. 3. Sense amplifier delay Vs NMOS channel length
mismatch.
From Fig. 3, we find that sensing delay increases with the
mismatch. However, the delay decreases when a logic low is
read with the same setup. Exactly reverse phenomenon can
be expected, if the parameters of the NMOS transistors in
the left hand side are increased while those in the right hand
side are decreased.
5. SIMULATION RESULTS
Extensive simulations are carried out to check the effect of
mismatch in Vth and channel length.
A. Mismatch in NMOS parameters
For the circuit shown in Fig. 2, Vth of M1 is decreased
and that of M3 is increased by same amount. For circuits
shown in Fig. 1, the Vth of N1 and N3 is decreased while
that of N2 and N4 is increased. Similar analysis is carried
out to study channel length mismatch in NMOS transistors.
For all the simulations we assume that the SRAM cell
content is logic high, since this gives the worst case results
for the above setup.
The results of delay versus NMOS threshold voltage
mismatch are shown in Fig. 4.
However CSA is relatively more sensitive to mismatch in
NMOS threshold voltage which fails at 2%. Similar trend is
observed with NMOS length mismatch. However, if
minimum length (i.e. 50nm) NMOS transistors are used,
CSA is found to become extremely sensitive to mismatch in
channel length. Simulation results for NMOS length
mismatch are shown in Fig. 3.
Fig. 4. Sense amplifier delay Vs NMOS threshold
voltage mismatch.
B. Mismatch Analysis in PMOS Parameters
Parameter mismatch of PMOS transistors does not
drastically affect performance of the sense amplifier. The
reason being, when the sense amplifier is activated NMOS
transistors immediately start operating in saturation region,
however PMOS transistors operate either in cut-off or
conduct in deep triode region. Mismatch analysis is carried
out by decreasing Vth of P1 and increasing Vth of P2 in
Fig.2. by the same amount. Similar variations in channel
length are imposed to understand the effect of length
mismatch. The readings are taken when the SRAM cell
content is logic low, as this gives worst case results.
Simulation results for length mismatch and threshold
voltage mismatch are shown in Fig. 5 and 6 respectively.
However, the sense amplifier delay decreases when logic
high is read from the memory. Simulation results show that
VSA is less sensitive to variation in PMOS parameters.
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International Journal of Research in Computer and ISSN (Online) 2278- 5841
Communication Technology, Vol 3, Issue 5, May- 2014 ISSN (Print) 2320- 5156
and channel length whereas performance degradation due to
PMOS parameter variations is found to be marginal. Current
sense amplifier is found to give best performance in terms of
speed, although when compared to voltage sense amplifiers
it is marginally more sensitive to parameter variations.
REFERENCES
[1]
Chotaro Masuda et al., “High current efficiency sense amplifier
using body-bias control for ultra-low-voltage SRAM ,” IEEE
2011.
[2] Manoj Sinha, et al, " High-Performance and Low-Voltage Sense
Amplifier techniques for sub-90nm SRAM ," IEEE 2003.
[3] Bernard Wicht, Thomas Nirschl and Doris Schmitt Landsiedel, “A
Yield-Optimized Latch-Type SRAM
Sense Ampli_er”, European
Solid-State Circuits Confer ence (ESSCIRC), 2003, pp. 409-412.
[4] T.N. Blalock and R.C. Jaeger, “A High Speed Clamped Bit-Line
Current-Mode Sense Amplifier”, IEEE Journal of Solid- State Circuits,
Vol. 26, No. 4, 1991, pp. 542-548.
[5] R. Jacob Baker, “CMOS: Circuit Design,Layout, and Simulation”,
2nd Edition, Wiley- IEEE Press, 2004.
Fig. 5. Sense amplifier delay Vs PMOS channel
length mismatch
Fig. 6. Sense amplifier delay Vs PMOS threshold
Voltage mismatch.
6. CONCLUSION
Impact of process variation induced transistor mismatch
on two different sense amplifier configurations is presented.
It is found that as the mismatch increases sensing delay also
increases, eventually leading to failure of the sense
amplifier. Performance of the sense amplifier is worst
affected by mismatch in NMOS transistor threshold voltage
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