Section 12. Parallel Slave Port
HIGHLIGHTS
12
This section of the manual contains the following major topics:
Introduction .................................................................................................................. 12-2
Control Register ........................................................................................................... 12-3
Operation ..................................................................................................................... 12-5
Operation in SLEEP Mode ........................................................................................... 12-6
Effect of a RESET ........................................................................................................ 12-6
PSP Waveforms ........................................................................................................... 12-6
Design Tips .................................................................................................................. 12-8
Related Application Notes............................................................................................ 12-9
Revision History ......................................................................................................... 12-10
 2000 Microchip Technology Inc.
DS39512-page 12-1
Parallel
Slave Port
12.1
12.2
12.3
12.4
12.5
12.6
12.7
12.8
12.9
PIC18C Reference Manual
12.1
Introduction
Some devices have an 8-bit wide Parallel Slave Port (PSP). This port is multiplexed onto one of
the device’s I/O ports. The port operates as an 8-bit wide Parallel Slave Port, or microprocessor
port, when the PSPMODE control bit is set. In this mode, the input buffers are TTL.
In slave mode, the module is asynchronously readable and writable by the external world through
the RD control input pin and the WR control input pin.
It can directly interface to an 8-bit microprocessor data bus. The external microprocessor can
read or write the PORT latch as an 8-bit latch. Setting the PSPMODE bit enables port pins to be
the RD input, the WR input, and the CS (chip select) input.
Note 1: At present the Parallel Slave Port (PSP) is only multiplexed onto PORTD and
PORTE. The microprocessor port becomes enabled when the PSPMODE bit is set.
In this mode, the user must make sure that PORTD and PORTE are configured as
digital I/O. That is, peripheral modules multiplexed onto the PSP functions are disabled (such as the A/D).
When PORTE is configured for digital I/O, PORTD will override the values in the
TRISD register.
2: In this mode the PORTD and PORTE input buffers are TTL. The control bits for the
PSP operation are located in TRISE.
There are actually two 8-bit latches, one for data-out (from the PICmicro) and one for data input.
The user writes 8-bit data to the PORT data latch and reads data from the port pin latch (note
that they have the same address). In this mode, the TRIS register is ignored, since the microprocessor is controlling the direction of data flow.
Register 12-1 shows the block diagram for the PSP module.
Figure 12-1: PORTD and PORTE Block Diagram (Parallel Slave Port)
Data Bus
D
WR LATD
or PORTD
Q
PSP<7:0>
CK
EN
Q
D
TTL
RD PORTD
EN
EN
RD LATD
One bit of PORTD
Set interrupt flag
PSPIF
Read
Chip Select
Write
Note:
DS39512-page 12-2
TTL
RD
TTL
CS
TTL
WR
I/O pins have protection diodes to V DD and V SS.
 2000 Microchip Technology Inc.
Section 12. Parallel Slave Port
12.2
Control Register
Register 12-1 is the PSP control register (PSPCON). The TRISE register (Register 12-2) contains the 4 bits for the PSP module found in some devices (such as PIC18C4X2) for compatibility
with 40-pin midrange devices.
Register 12-1: PSPCON Register
R-0
IBF
bit 7
bit 7
R-0
OBF
R/W-0
IBOV
R/W-0
PSPMODE
U-0
—
U-0
—
U-0
—
U-0
—
bit 0
12
IBF: Input Buffer Full Status bit
bit 6
Parallel
Slave Port
1 = A word has been received and waiting to be read by the CPU
0 = No word has been received
OBF: Output Buffer Full Status bit
1 = The output buffer still holds a previously written word
0 = The output buffer has been read
bit 5
IBOV: Input Buffer Overflow Detect bit (in microprocessor mode)
1 = A write occurred when a previously input word has not been read
(must be cleared in software)
0 = No overflow occurred
bit 4
PSPMODE: Parallel Slave Port Mode Select bit
1 = Parallel slave port mode
0 = General purpose I/O mode
bits 3:0
Unimplemented: Read as '0'
Legend
R = Readable bit
- n = Value at POR reset
 2000 Microchip Technology Inc.
W = Writable bit
’1’ = bit is set
U = Unimplemented bit, read as ‘0’
’0’ = bit is cleared
x = bit is unknown
DS39512-page 12-3
PIC18C Reference Manual
Register 12-2: TRISE Register
R-0
IBF
bit 7
bit 7
R-0
OBF
R/W-0
IBOV
R/W-0
PSPMODE
U-0
—
R/W-1
TRISE2
R/W-1
TRISE1
R/W-1
TRISE0
bit 0
IBF: Input Buffer Full Status bit
1 = A word has been received and waiting to be read by the CPU
0 = No word has been received
bit 6
OBF: Output Buffer Full Status bit
1 = The output buffer still holds a previously written word
0 = The output buffer has been read
bit 5
IBOV: Input Buffer Overflow Detect bit (in microprocessor mode)
1 = A write occurred when a previously input word has not been read
(must be cleared in software)
0 = No overflow occurred
bit 4
PSPMODE: Parallel Slave Port Mode Select bit
1 = Parallel slave port mode
0 = General purpose I/O mode
bit 3
Unimplemented: Read as '0'
bit 2
TRISE2: RE2 Direction Control bit
1 = Input
0 = Output
bit 1
TRISE1: RE1 Direction Control bit
1 = Input
0 = Output
bit 0
TRISE0: RE0 Direction Control bit
1 = Input
0 = Output
Legend
R = Readable bit
- n = Value at POR reset
DS39512-page 12-4
W = Writable bit
’1’ = bit is set
U = Unimplemented bit, read as ‘0’
’0’ = bit is cleared
x = bit is unknown
 2000 Microchip Technology Inc.
Section 12. Parallel Slave Port
12.3
Operation
A write to the PSP from the external system occurs when both the CS and WR lines are first
detected low. When either the CS or WR lines become high (edge triggered), the Input Buffer Full
status flag bit IBF is set on the Q4 clock cycle following the next Q2 cycle. This signals that the
write is complete. The interrupt flag bit, PSPIF, is also set on the same Q4 clock cycle. The IBF
flag bit is inhibited from being cleared for additional TCY cycles (see parameter 66 in the "Electrical Specifications" section). If the IBF flag bit is cleared by reading the PORTD input latch,
then this has to be a read-only instruction (i.e., MOVF) and not a read-modify-write instruction.
The Input Buffer Overflow status flag bit IBOV is set if a second write to the Parallel Slave Port is
attempted when the previous byte has not been read out of the buffer.
Input Buffer Full Status Flag bit, IBF, is set if a received word is waiting to be read by the CPU.
Once the PORT input latch is read, the IBF bit is cleared. The IBF bit is a read only status bit.
Output Buffer Full Status Flag bit, OBF, is set if a word written to the PORT latch is waiting to be
read by the external bus. Once the PORTD output latch is read by the microprocessor, OBF is
cleared. Input Buffer Overflow Status Flag bit, IBOV, is set if a second write to the microprocessor
port is attempted when the previous word has not been read by the CPU (the first word is retained
in the buffer).
When not in Parallel Slave Port mode, the IBF and OBF bits are held clear. However, if the IBOV
bit was previously set, it must be cleared in the software.
An interrupt is generated and latched into flag bit PSPIF when a read or a write operation is completed. Interrupt flag bit PSPIF must be cleared by user software and the interrupt can be disabled by clearing interrupt enable bit PSPIE.
Table 12-1: PORTE Functions
Name
RD
WR
CS
Note:
 2000 Microchip Technology Inc.
Function
Read Control Input in parallel slave port mode:
RD
1 = Not a read operation
0 = Read operation. Reads PORTD register (if chip selected)
Write Control Input in parallel slave port mode:
WR
1 = Not a write operation
0 = Write operation. Writes PORTD register (if chip selected)
Chip Select Control Input in parallel slave port mode:
CS
1 = Device is not selected
0 = Device is selected
The PSP may have other functions multiplexed onto the same pins. For the PSP to
operate, the pins must be configured as digital I/O.
DS39512-page 12-5
12
Parallel
Slave Port
A read of the PSP from the external system occurs when both the CS and RD lines are first
detected low. The Output Buffer Full status flag bit OBF is cleared immediately indicating that the
PORTD latch was read by the external bus. When either the CS or RD pin becomes high (edge
triggered), the interrupt flag bit, PSPIF, is set on the Q4 clock cycle following the next Q2 cycle,
indicating that the read is complete. OBF remains low until data is written to PORTD by the user
firmware.
PIC18C Reference Manual
12.4
Operation in SLEEP Mode
When in SLEEP mode, the microprocessor may still read and write the Parallel Slave Port. These
actions will set the PSPIF bit. If the PSP interrupts are enabled, this will wake the processor from
SLEEP mode so that the PSP data latch may be either read, or written with the next value for the
microprocessor.
12.5
Effect of a RESET
After any RESET, the PSP is disabled and PORTD and PORTE are forced to their default mode.
12.6
PSP Waveforms
Register 12-2 shows the waveform for a write from the microprocessor to the PSP, while
Register 12-3 shows the waveform for a read of the PSP by the microprocessor.
Figure 12-2: Parallel Slave Port Write Waveforms
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
Figure 12-3: Parallel Slave Port Read Waveforms
Q1
Q2
Q3
Q4
Q1
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
DS39512-page 12-6
 2000 Microchip Technology Inc.
Section 12. Parallel Slave Port
Table 12-2: Registers Associated with Parallel Slave Port
Value on
POR, BOR
Value on all
other resets
Port data latch when written; port pins when read
xxxx xxxx
uuuu uuuu
LATD
LATD Data Output Bits
xxxx xxxx
uuuu uuuu
TRISD
PORTD Data Direction Bits
1111 1111
1111 1111
---- -000
---- -000
Name
Bit 7
PORTD
PORTE
(1)
LATE
TRISE
(1)
—
Bit 6
—
Bit 5
—
Bit 4
Bit 3
—
—
Bit 2
RE2
Bit 1
RE1
Bit 0
RE0
—
—
—
—
—
LATE Data Output Bits
---- -xxx
---- -uuu
IBF
OBF
IBOV
PSPMODE
—
PORTE Data Direction Bits
0000 -111
0000 -111
PSPCON
IBF
OBF
IBOV
PSPMODE
—
—
—
—
0000 ----
0000 ----
INTCON
GIE/
GIEH
PEIE/
GIEL
TMR0IF
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x
0000 000u
PSPIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
PSPIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
IPR1
PSPIP
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
0000 0000
0000 0000
ADCON1
ADFM
ADCS2
—
—
PCFG3
PCFG2
PCFG1
PCFG0
--0- -000
--0- -000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'.
Shaded cells are not used by the Parallel Slave Port.
Note 1: On some devices the entire PORTE will be implemented with I/O functions. In these devices, the TRISE register will contain the eight data direction bits and the PSP bits will be located in the PSPCON register.
 2000 Microchip Technology Inc.
DS39512-page 12-7
Parallel
Slave Port
PIR1
PIE1
12
PIC18C Reference Manual
12.7
Design Tips
Question 1:
Migrating from the PIC16C74 to the PIC18CXX2, the operation of the PSP
seems to have changed.
Answer 1:
Yes, a design change was made so the PIC18CXX2 is edge sensitive (while the PIC16C74 was
level sensitive).
DS39512-page 12-8
 2000 Microchip Technology Inc.
Section 12. Parallel Slave Port
12.8
Related Application Notes
This section lists application notes that are related to this section of the manual. These application notes may not be written specifically for the Enhanced MCU family (that is, they may be written for the Base-Line, the Mid-Range or High-End families), but the concepts are pertinent, and
could be used (with modification and possible limitations). The current application notes related
to the Parallel Slave Port are:
Title
Application Note #
Using the 8-bit Parallel Slave Port
AN579
12
Note:
http://www.microchip.com/10/faqs/codeex/
 2000 Microchip Technology Inc.
DS39512-page 12-9
Parallel
Slave Port
Please visit the Microchip Web site for additional software code examples. These
code examples are stand alone examples to assist in the understanding of the
PIC18CXXX. The web address for these examples is:
PIC18C Reference Manual
12.9
Revision History
Revision A
This is the initial released revision of the Parallel Slave Port description.
DS39512-page 12-10
 2000 Microchip Technology Inc.