Mixed-Signal BIST - Auburn University
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A Built-In Self-Test Approach for Analog Circuits in Mixed-Signal Systems Chuck Stroud Dept. of Electrical & Computer Engineering Auburn University Outline of Presentation • Need for Test & Overview of BIST • Mixed-Signal BIST Architecture ¾ ¾ Test Pattern Generator Output Response Analyzer • Fault Detection with BIST • Experimental Results ¾ ¾ Fault Simulation Hardware Prototype • Parameterized VHDL Model • Summary & Conclusions • Demonstration The Need for Test 2000 International Technology Roadmap for Semiconductors (by the Semiconductor Industry Association - SEMATECH) predicts by 2014: • Test machines will cost more than $20M each!!! • It will cost more to test a transistor than to manufacture it!!! • Built-In Self-Test (BIST) is the most likely solution ¾ Analog BIST is needed for mixed-signal systems ¾ Fault diagnosis is needed with BIST ¾ Methods are needed for automatic implementation of BIST Analog Circuit Behavior Frequency response using nominal component values Gain Phase Analog Circuit Behavior Frequency response using component variations Gain Phase What is Built-In Self-Test? • Basic idea: Add circuitry to integrated circuit (chip) or printed circuit board to make it test itself ¾ ¾ Only power and clock needed during BIST sequence System Pass/Fail result reported at end of BIST sequence No need for external test equipment • Necessary components: ¾ ¾ ¾ BIST Start Test Pattern Generator (TPG) Output Response Analyzer (ORA) For system level use: Test controller Input isolation • Penalties: area overhead, performance • Benefits: low testing time & cost Inputs TPG MUX Test Control Circuit Under Test ORA Pass/Fail System Outputs Mixed-Signal BIST Architecture Digital Circuitry Digital System Inputs System Function Mux Analog Circuitry DAC 101011000111011010 BIST Start BIST Complete BIST Results Digital System Outputs Analog System Outputs Analog Cktry TPG Analog System Inputs Test Control Analog Loopback ORA 101011000111011010 System Function ADC Analog Cktry System-Level Use of BIST • Multiple BIST sequences w/ analog loopback MUX ¾ Pass/fail results indicate location of faulty analog circuitry • Location & number of analog loopback MUXs ¾ ¾ Determine analog diagnostic resolution & fault coverage Can trade-off diagnostic resolution and fault coverage with analog area overhead & performance penalties TPG DAC Analog Cktry ORA ADC Analog Cktry Analog Cktry Analog Cktry Test Pattern Generation TPG generates 16 test waveforms: • counter (up, down, & up/down) ¾ Counter/LFSR ramp, sawtooth & triangle waveforms • LFSR (pseudo-random patterns) ¾ Bit Reversal MUX noise-like waveforms • magnitude register ¾ ¾ programmable amplitude DC test impulse & step responses • frequency sweep ¾ varying & constant amplitudes • bit reversal (for most waveforms) ¾ Count Value Holding Reg System Mag Reg Data Output Data MUX noise & random frequencies/amplitudes To DAC Sample Test Waveforms 6.0V 5.0V 4.0V 4.0V Frequency Sweep Varying Amplitude 2.0V 0V 0s 1.0s 2.0s 3.0s 4.0s 5.0s 6.0s 7.0s Frequency Sweep Varying Amplitude Bit Reversal 2.0V 8.0s 0V 0s V(1) 0.5s 1.0s 1.5s 2.0s 2.5s 3.0s 3.5s 4.0s 4.5s V(2) Time Time 5.0V 5.0V Triangular Wave & Bit Reversal 2.5V 0V 0s 100ms V(1) 200ms 300ms V(2) 400ms Pseudo-Random Patterns 2.5V 500ms 0V 0s 40ms 80ms 120ms V(2) Time Time 160ms 200ms 240ms Actual Waveforms from Demo Unit Varying amplitude frequency sweep observed at DAC output Triangle wave observed at DAC output Step function observed at DAC output Saw-tooth observed at DAC output Output Response Analyzer ORA is a double precision accumulator: • Allows range of values to determine From TPG pass/fail status ¾ ¾ ¾ ¾ component tolerances processing variation temperature & voltage variation DAC/ADC noise • Modes of operation: ¾ ¾ ¾ digital test of BIST circuitry analog magnitude test sums ADC output magnitudes analog difference test sums |TPG input - ADC output| From ADC Absolute Value Subtractor MUX Double Precision Accumulator BIST Results Absolute Value Difference • Detects faults causing: ¾ ¾ ¾ Noise Phase shift Overshoot/ringing Input step function Output response Correct signature Fault detection signature Analog Fault Detection with BIST • Acceptable variation distributions ¾ Observation: all variations produce normal distribution of signatures • Detected vs. undetected faults • Potentially detected faults ¾ Pdetect = #detects/#simulations • Fault Coverage = (#detect + ΣPdetect)/#faults Pdetect 0 bad ckt good ckt bad ckt 2N Fault Simulator Results OpAmp1, Sum Vout, 250 runs, 2/16/02, -0.1 to 0.1 V sawtooth input, 250-µ s period Faults: MOS source-drains, resistor, and capacitor opens and shorts. 120 100 Counts 80 Process variations: resistor and capacitor (MOS process variations planned). 60 40 20 No Faults All Faults 0 0 1000 2000 3000 4000 BIST Accumulator Sum 5000 6000 BIST Results with Benchmark Circuits Benchmark Circuit Op Amp 1 CTSV Filter Op Amp 2 Leapfrog filter Differential amp Comparator Single stage amp Elliptical filter Low-pass filter # Comps 11 9 10 17 9 3 6 22 4 # Op Amps 3 6 1 3 1 Hard Soft Faults Faults 22 6 84 36 20 2 154 46 34 18 26 8 16 12 90 62 30 14 Fault Coverage 98.6% 97.8% 100% 100% 95.0% 95.4% 100% 100% 100% General trends: • Frequency sweep waveforms perform best for filters • Count/LFSR test waveforms perform best for amplifiers Noise & Phase Shift Detection Noise and Phase Shift Detection with Difference Summing Mode 100 Fault C o ve rage 100 Diff Summing FC Mag Summing FC Diff Summing FC Mag Summing FC Fault C o ve rage 80 60 40 20% 20 80 60 40 45% 20 0 0 0.5 1 2 4 5 Amplitude of noise as a % of the amplitude of the input signal 1 2 3 4 5 6 7 8 Phase shift as a % of the input waveform period 9 Actual Benchmark Circuit Results Good low pass filter w/count-up DAC output test waveform Resultant good circuit signature distribution in ORA Good low-pass output response Faulty low pass filter w/count-up DAC output test waveform Resultant faulty circuit signature distribution in ORA Fault is always detected Faulty low-pass output response Parameterized VHDL Models • Automated synthesis in any design • Parameterized VHDL includes: ¾ TPG ¾ Supports ADC sizes: 4 to 24-bits User specified accumulator size Reduces aliasing probability Test controller ¾ Supports DAC sizes: 4 to 24-bits ORA ¾ Processor Interface User programmable initialization & BIST sequence lengths Choice of processor interfaces Custom, serial, parallel IEEE 1149 Boundary Scan Test Control ORA TPG Demonstration Unit 1997 • Original demo unit ¾ 3 analog benchmark circuits in discrete parts DAC, OpAmp, & Low Pass Filter Test Pattern Generator 1997 Demonstration Unit 2002 • • PC control & display Benchmark circuit PCB ¾ ¾ low/high/band-pass filter with physical fault injection • DAC-ADC PCB ¾ with analog loopback • Mixed-signal BIST PCB ¾ with MOSIS TinyChips • CPLD-based BIST PCB ¾ ¾ for synthesis of VHDL parameterized 4 to 12 bits ORA TPG BIST Implementation 2002 Test Pattern Generator Output Response Analyzer • Includes test controller Parameterized VHDL Generics Generic Range Bits controlled by generics NDAC 4 ≤ NDAC ≤ 24 # inputs to DAC NADC 4 ≤ NADC ≤ 24 # outputs from ADC NACUM NACUM ≥ max (NADC, NDAC) # bits in 1/2 of double-precision accumulator NPSR NPSR ≥ 1 # bits in freq. sweep shift reg. NICNT NICNT + NBCNT ≤ NACUM # bits in initialization counter NBCNT NLPBK # bits in BIST counter NLPBK ≤ NACUM - 2 # analog loopback control bits Processor Interfaces • Custom Interface ¾ ¾ incorporation with system specific interfaces all data busses & write enables TDI accessible • Parallel Interface ¾ ¾ address decoder & read multiplexer with & without synchronization • Serial Interface ¾ ¾ serial shift register with & without synchronization • Boundary Scan ¾ interface to IEEE 1149 standard Capture/update sync shift register sync address decode TPG read MUX Test ORA Control TDO VHDL Synthesis Results NDAC 4 4 4 8 12 12 8 Area optimize Speed optimize NADC NACUM # Area Freq. # Freq. (MHz) gates (MHz) gates (µm2) 4 12 1044 554961 61.3 1157 94 8 12 1100 581594 62.6 1227 89.2 12 12 1159 624680 64 1305 86.8 4 12 1276 690625 62.6 1441 88.9 4 12 1506 801766 64 1716 84.9 12 12 1534 809328 64 1773 85.7 8 8 1147 599636 91.8 1298 108.7 • AMI 0.5µm CMOS standard cell synthesis results: ¾ 745 µm to 900 µm on a side ¾ 60 MHz to 109 MHz operation VHDL Synthesis • Used Mentor Graphics ¾ ¾ serial processor interface 4, 8, and 12-bit versions • Synthesized & verified ¾ via simulation in: 1.5µm AMI CMOS 0.5µm AMI CMOS ¾ in actual hardware in: Cypress 39K CPLDs Using WARP Xilinx Virtex FPGAs Using ISE VHDL Synthesis Synthesis in Spartan 2s50 FPGA with room to spare Project TPG Architecture BIST FS CVAL Mag Cont 8 8 PISR 4 cont W Ad Data PDO 8 Dat 8 ADEC 2 Mag Cont WEs 8 8 Mag Cont Mag Cval SDAT BIST 8 LCNT BITR 1 0 LCNT 8 5 FFs 8 TCO TOUT BIST FS PSR 8 8 TCO logic ODAT co CO din LFSR/counter 8 PDI PSL PE 8 OTOG FS DSEL 2 CVAL 3 ld Par Register Shift Reg TFF 8 CVAL OTOG PDI PSL PE 2 W Ad Aclo 8 8 8 Data WE3 PISR 8 TDAT ADAT 8 8 PDO Dat 8 Achi Bist Idone DONE OFS LPBK Icnt Bcnt Project ORA Architecture REG ADEC 3 8 8 co Sub 8 5 2 4 WEs Abs 2 2 DSEL 8 LPBK OFS Dat BIST en ICNT co Idone 4 Bist Icnt Idone en BCNT co 4 Bcnt Dat WE2 Dat 4 WE3 TCO Dat WE2 Dat 4 WE3 TCO Dat WE3 Sdat Done CONT DONE Ben WE0 Dat WE1 Dat 8 8 en ACLO co 8 Aclo en ACHI ACUM 8 Achi Summary & Conclusions • Most of BIST circuitry in digital domain ¾ minimizes impact on analog circuitry • TPG produces 16 test waveforms ¾ high fault coverage in wide variety of analog ckts • ORA has multiple summing modes ¾ ¾ accumulator allows range of acceptable values absolute value difference detects noise/phase shifts • Parameterized VHDL for use in any design ¾ implemented & verified in hardware
