課程講義：【電力電子】 DC-DC Converter - Modeling Techniques
交通大學 808-電力電子實驗室 June 4, 2009
台灣新竹‧交通大學‧電機與控制工程研究所‧808實驗室
電力電子系統晶片、數位電源、DSP控制、馬達與伺服控制
Lab-808: Power Electronic Systems & Chips Lab., NCTU, Taiwan
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Right-Half-Plane (RHP) Zero
鄒 應 嶼
國立交通大學
教 授
電機與控制工程研究所
2009年6月4日
Lab808: 電力電子系統與晶片實驗室
Power Electronic Systems & Chips, NCTU, TAIWAN
LAB808
NCTU
台灣新竹•交通大學•電機與控制工程研究所
1/26
Zero in the Boost and Buck/Boost Converters (CCM)
L
D
vi
C
vo
D
vi
C
L




vo
• Boost
o 
v o ( s ) Vi (1  rC Cs)(1  sL ( D'2 R))

s
1
d ( s ) D'2
( )2 
s 1
o
 oQ
Q
• Buck/Boost
o 
vo ( s) Vi (1 rC Cs)(1 sDL ( D'2 R))
 '2
s
1
d ( s) D
( )2 
s 1
o
oQ
Q
D
LC
D
o
1
L
rL C

 rC C
DR D
D
LC
D
o
1
L
rC
r

(
 L )C
(D )2 R D (D )2
Why the RHP zero will occur?
Where is the RHP zero?
What is the effect of the RHP zero?
Can the RHP zero be eliminated?
2/26
台灣新竹‧交通大學‧電機與控制工程研究所‧808實驗室
電源系統與晶片、數位電源、馬達控制驅動晶片、DSP/FPGA控制
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1
課程講義：【電力電子】 DC-DC Converter - Modeling Techniques
交通大學 808-電力電子實驗室 June 4, 2009
Right-Half-Plane (RHP) Zero
Right-Half-Plane Zero (of DC-DC Converters) - A simplified explanation,
Lloyd Dixon, 1984, (slup084)
Understanding the Right-Half-Plane Zero,
May 1, 2009 12:00 PM
CHRISTOPHE BASSO, Director, Product Application Engineering, ON
Semiconductor, Phoenix
Tricks of the Trade - understanding the right-half-plane zero in smallsignal DC-DC converter models,
IEEE Power Electronics Society NEWSLETTER, January 2001.
A Mathematical Introduction to Control Theory,
Shlomo Engelber, Imperial College Press,
pp. 147, The Effect of Zeros in the Right Half-Plane
3/26
RHP Zero of Boost and Buck-Boost Converters
Right-Half-Plane Zero - A simplified explanation, Lloyd Dixon, 1984, (slup084)
IL
D
vi
L
C
vo
IO
D
Flyback Circuit, Continuous Inductor Current Mode
IL
IO
dˆ
Switchmode power supply handbook
Keith H. Billings
Incremental changes in duty ratio.
4/26
台灣新竹‧交通大學‧電機與控制工程研究所‧808實驗室
電源系統與晶片、數位電源、馬達控制驅動晶片、DSP/FPGA控制
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2
課程講義：【電力電子】 DC-DC Converter - Modeling Techniques
交通大學 808-電力電子實驗室 June 4, 2009
40
Right-Half-Plane (RHP) Zero
20
VL  Vi D  VO (1  D )  (Vi  VO ) D  VO
iˆo dˆ
0
(dB)
fz
-20
-40
1
10
100
VˆL  (Vi  VO )dˆ  VˆO (1  D )  (Vi  VO )dˆ
1K
10K 100 (Hz)
 iˆo dˆ 0
(Deg)
-90
iO   j
z 
-180
(Vi  VO )(1  D ) ˆ
V
d  I Ldˆ   j i dˆ  I Ldˆ
L
L
RO Vi (1  D ) RO (1  D) 2
RO Vi 2


LVO
LD
LVO (Vi  VO )
Frequency response of RHP zero in voltage-mode control
40
20
iˆo iˆL
0
(dB)
fz
-20
-40
1
10
100
1K
L I L ˆ
L I L ˆ
Vi
iˆO  iˆL (1  D )  j
iL 
iˆL  j
iL
(Vi  VO )
(Vi  VO )
(Vi  VO )
10K 100
 iˆo iˆL 0
(Deg)
-90
The RHP zero is still present with current mode control!
Frequency response of RHP zero in current-mode control
-180
RHP Zero of CCM Buck-Boost (Flyback) Converter
D
vi
 z1 
L
1
rCC
• Buck/Boost
vo
C
  P1
0
D
LC
D
o 
vo ( s) Vi (1 rC Cs)(1 sDL ( D'2 R))
 '2
s
1
d ( s) D
( )2 
s 1
o
oQ
Q
o
1
L
rC
r

(
 L )C
(D )2 R D (D )2
 V

iO  dˆ  i  I L 
 sL

Vi
RO (1  D ) 2

z2 
LI L
LD
Rx
 P2
Q
0
2 Rx
6/26
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3
課程講義：【電力電子】 DC-DC Converter - Modeling Techniques
交通大學 808-電力電子實驗室 June 4, 2009
RHP Zero of CCM Boost Converter
 The effect of any control action during the ON time is delayed until the
switch is turned FF.
 Output response is initially in the opposite direction of the desired
correction.
RHP Zero
L
vi
D
C
R vo
Brian Lynch, Under the Hood of a DC-DC Boost Converter, 2008-09 Power Supply Design Seminar - SEM1800.
7/26
Compensation of RHP Zero
A current mode control boost regulator has an inherent right half plane zero (RHP zero). This
zero has the effect of a zero in the gain plot, causing an imposed +20dB/decade on the rolloff,
but has the effect of a pole in the phase, subtracting another 90° in the phase plot. This can
cause undesirable effects if the control loop is influenced by this zero.
To ensure the RHP zero does not cause instability issues, the control loop should be designed
to have a bandwidth of ½ the frequency of the RHP zero or less. This zero occurs at a
frequency of:
RFPzero 
VOUT ( D ' )2
(in Hz)
2 ILOAD L
where ILOAD is the maximum load current.
REF: LM5000 High Voltage Switch Mode Regulator
8/26
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4
課程講義：【電力電子】 DC-DC Converter - Modeling Techniques
交通大學 808-電力電子實驗室 June 4, 2009
Compensation of OP-Amp uA741
Complete Fairchild µA741 schematic. The primary signal path is comprised of two gain stages. The first gain stage is a
differential pair with active load (transistors Q1–Q6). The second gain stage is a common-emitter amplifier (transistors Q16
and Q17). The output buffer is a push-pull emitter follower (transistors Q14, Q20, and Q22).
Kent H. Lundberg, "Internal and External Op-Amp Compensation: A Control-Centric Tutorial,"
American Control Conference, 2004.
Compensation for OP-AMP
(a) Simplified schematic of the uncompensated Fairchild µA741 op amp.
Vin
A1
A2
1
(b) Simplified schematic of the Fairchild µA741 op amp
with compensation capacitor.
V0
C
Compensated
Vin
A1
A2
1
V0
(d) Equivalent circuit of uncompensated and compensated OP-Amp.
(d) Frequency response of uncompensated and compensated op
amp. The two low-frequency poles in the uncompensated transfer
function severely degrade the phase margin at crossover.
台灣新竹‧交通大學‧電機與控制工程研究所‧808實驗室
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5
課程講義：【電力電子】 DC-DC Converter - Modeling Techniques
交通大學 808-電力電子實驗室 June 4, 2009
RHP Zero of a Common-Emitter Amp
Cf
C
Cf
B
B
Ii
V
R1
(a) Common-emitter amp.
Vo
C
gmV
C1
C2
R2
(b) Equivalent circuit
( sC f  g m ) R1 R 2
Vo

I i 1  s[ C1 R1  C 2 R 2  C f ( g m R1 R 2  R1  R 2 )]  s 2 [ C1C 2  C f ( C1  C 2 )] R1 R 2
There is a RHP Zero located at s 
gm
Cf
For typical values, for example, in the µA741 of g m  6.8mA / V and
s
C f  30 pF,
3
gm 6.8  10

 36MHz
C f 30  1012
 The RHP zero is usually not a problem in bipolar op amps because it is at a much higher
frequency than the dominant pole, and can be neglected!
 In a CMOS op amp, where transistor transconductances can be much lower, the right-half
plane zero frequency can be quite close to the unity-gain frequency of the op amp.
3-dB Frequency
Poles and Zeros Can Be Easily Determined
Low-Frequency Response
A( s )  AM FH ( s )
A( s )  AM FL (s )
FL ( s ) 
( s  Z 1 )( s  Z 2 ) ( s   ZnL )
( s  P1 )( s   P 2 ) ( s  Pn L )
If  P1>>  P2,  P3,  ,  Z1,  Z2,
then for frequencies near the midband:
FL ( s ) 
s
s  P1
High-Frequency Response
(Dominant pole)
and,  L  P1 .
Otherwise,
 L  ωP2 1  ω P2 2    2( ωZ21  ωZ2 2  )
FH ( s) 
(1  s Z1 )(1  s Z 2 ) (1  s ZnH )
(1  s P1 )(1  s P 2 ) (1  s Pn H )
If  P1>>  P2,  P3,  ,  Z1,  Z2,
then for frequencies near the midband:
FH ( s) 
1
1  s  P1
(Dominant pole)
and, H  P1 .
Otherwise,
H  1
 1

1
1
1

   2 2  2  
ωP2 1 ω P2 2
ω
ω
 Z1

Z2
12/26
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6
課程講義：【電力電子】 DC-DC Converter - Modeling Techniques
交通大學 808-電力電子實驗室 June 4, 2009
3-dB Frequency
Poles and Zeros Cannot Be Easily Determined
Low-Frequency Response
FL ( s ) 
s nL  d1s nL1  
s nL  e1s nL1  
FH ( s ) 
b1 
e1  P1  P 2    PnL
nL
e1  
i 1
High-Frequency Response
1  a1s  a2 s 2  
1  b1s  b2 s2  
1
1

P1 P 2
 
1
PnH
nH
1
Ci Ris
b1   Ci Rio
i 1
If a dominant pole exists (say, P1), then
If a dominant pole exists (say, P1), then
e1  P1 and L  P1
b1 
Thus,
1
P 1
H   P1
and
Thus,
nL
1
L  
i1 Ci Ris
H  1
nL
C R
i 1
i
io
13/26
Dominant Pole
( sC f  g m ) R1 R 2
Vo

I i 1  s[ C 1 R1  C 2 R 2  C f ( g m R1 R 2  R1  R 2 )]  s 2 [ C 1C 2  C f ( C1  C 2 )] R1 R 2
If the RHP Zero be neglected,
Vo
 g m R1 R 2

I i 1  s [ C1 R1  C 2 R 2  C f ( g m R1 R 2  R1  R 2 )]  s 2 [ C1 C 2  C f ( C 1  C 2 )] R1 R 2
If the two poles are two separated real poles,
Vo
 g m R1 R 2



Ii
1  s  1  s

 p 1    p1





  P2
  P1
s
gm
Cf
14/26
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7
課程講義：【電力電子】 DC-DC Converter - Modeling Techniques
交通大學 808-電力電子實驗室 June 4, 2009
Dominant Pole
If  p1 <<  p2, then the  p1 can be regarded as the Dominant Pole.
  P2
  P1
The denominator polynominal D(s) can be written as:

s
D ( s )   1 

p1



1  s   1 



p1 

 1
1
s 



p2
 p1
2

1
s2
 s
    1 s    
p1 p 2
p1
p1 p 2

Vo
 g m R1 R 2

I i 1  s [ C1 R1  C 2 R 2  C f ( g m R1 R 2  R1  R 2 )]  s 2 [ C1 C 2  C f ( C 1  C 2 )] R1 R 2
 p1 
1
1

C 1 R1  C 2 R 2  C f ( g m R1 R 2  R1  R 2 ) C f g m R1 R 2
15/26
Dominant Pole
D(s)  1  s
1
 p1

s2
 p 1 p 2
 1  s[ C 1 R1  C 2 R 2  C f ( g m R1 R 2  R1  R 2 )]  s 2 [ C 1C 2  C f ( C 1  C 2 )] R1 R 2
 p 1 p 2 
1
[ C 1C 2  C f ( C1  C 2 )] R1 R 2
 p1 
1
C f g m R1 R 2
 p2 
g mC f
C 1C 2  C f ( C1  C 2 )
 p1 
1
R1C
Miller Effect
C  g m R 2 C f  AV C f
16/26
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8
課程講義：【電力電子】 DC-DC Converter - Modeling Techniques
交通大學 808-電力電子實驗室 June 4, 2009
Miller Theorem
Miller theorem describes the way to convert a floating load into
two grounded loads, in such way that the voltages and currents
are remained unchanged.
X
Z
I 
Y
I
Z1
A
VY
VX
V X  VY
Z
 Z1 
V
Z
1 Y
VX
V  VX
Z
VY  Z 2 I  Z 2 Y
 Z2 
V
Z
1 X
VY
I
X
V X  VY
,
Z
V X  Z 1I  Z1
Y
I
Z1 
Z2 
Z
1 A
Z
1
1
A
Z2
17/26
Miller Effect on the Compensation Capacitance
Cf
Cf
B
C
Ii
B
(a) Common-emitter amp.
V
R1
Vo
C
gmV
C1
C2
R2
(b) Equivalent circuit
Cf
B
Ii
R1
V
 AV
C1
AV  g m R 2
R2
C
B
Vo
C
C2
Ii
R1
V
C1
AV C f
Cf
Vo
R2
C2
(c) Equivalent circuit
18/26
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9
課程講義：【電力電子】 DC-DC Converter - Modeling Techniques
交通大學 808-電力電子實驗室 June 4, 2009
Poles Splitting By Miller Effect
C
increasing C
Vin
A1
V1
C1
C
A2
V0
1
V1
V0
C2
C1
V0
C
C2
C
C2
1'
1
2
2'
High-frequency model of the effective capacitive loading by the
compensation capacitor. When the compensation capacitor C is
removed from the circuit at left, the circuit is transformed into
the circuit at right so that the capacitive loading on each stage is
maintained.
19/26
Block Diagram of the OP-AMP Equivalent Circuit
sC
Vin
GM 1 R1
R1C1s  1
 GM 2
R2
R2C2 s  1
VO
sC
GM 1
Block diagram of the op-amp equivalent circuit, including the feedforward current through
the compensation capacitor. The feedforward term causes a right half-plane zero in the opamp transfer function.
Kent H. Lundberg, "Internal and External Op-Amp Compensation: A Control-Centric Tutorial,"
American Control Conference, 2004.
20/26
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10
課程講義：【電力電子】 DC-DC Converter - Modeling Techniques
交通大學 808-電力電子實驗室 June 4, 2009
RHP Zero of a Common-Source CMOS Amp
CMOS: circuit design, layout, and simulation,
R. Jacob Baker, IEEE Press, 2nd Ed., 2005.
21/26
Limitations Imposed by RHP Poles and Zeros
The control handbook,
Editor: W. S. Levine
22/26
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11
課程講義：【電力電子】 DC-DC Converter - Modeling Techniques
交通大學 808-電力電子實驗室 June 4, 2009
RHP Zero Compensation and Cancellation
[REFERENCES]
[1] D. M. Sable, B. H. Cho, and R. B. Ridley, "Elimination of the positive zero in fi xed frequency boost and flyback
converters," IEEE APEC Proc., 1990.
[2] Wei-Chung Wu, R. M. Bass, and J. R. Yeargan, "Eliminating the effects of the right-half plane zero in fixed frequency
boost converters," IEEE PESC Con. Rec., 1998.
[3] Right half-plane zero compensation and cancellation for switching regulators, In ventor: David W. Ritter,
Assignee: Micrel, Incorprated, San Jose, CA., Patten No.: US 2007/0252570 A1, Nov. 1, 2007.
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RHP Zero Compensation and Cancellation
US 2007/0252570 A1, Nov. 1, 2007.
Abstract —An improved method of canceling a RHPZ of a switching regulator can include detecting a
predetermined error signal provided to a pulse width modulation (PWM) circuit, wherein the
predetermined error signal is associated with the RHPZ. Once a RHPZ is detected, a ramp waveform
provided to the PWM circuit can be temporarily lengthened, thereby canceling the RHPZ. Notably,
temporarily lengthening the ramp waveform can be based on adjusting an RZ*CZ time constant. In one
embodiment, the ramp waveform can be lengthened to create a left half-plane zero (LHPZ), which
improves stability.
24/26
台灣新竹‧交通大學‧電機與控制工程研究所‧808實驗室
電源系統與晶片、數位電源、馬達控制驅動晶片、 DSP/FPGA控制
Lab-808: Power Electronic Systems & Chips Lab., NCTU, Taiwan
http://pemclab.cn.nctu.edu.tw/
12
課程講義：【電力電子】 DC-DC Converter - Modeling Techniques
交通大學 808-電力電子實驗室 June 4, 2009
Summary RHP Zero
Split LC switching converters operating in CCM will have
RHP zero due to the lagging inductor effect!
RHP zero CAN NOT be eliminated with current mode control!
EHP zero can be eliminated by using variable frequency
control.
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References: About RHP Zero
[1] Lloyd H. Dixon, Right-Half-Plane Zero - A simplified explanation, Unitrode Power Supply Design Seminar, 1984.
[2] C. Basso, Understanding the Right-Half-Plane Zero, Power Electronics Technology, 2009.
[3] Brian Lynch, Under the Hood of a DC-DC Boost Converter, 2008-09 Power Supply Design Seminar - SEM1800.
[4] D. M. Sable, B. H. Cho, and R. B. Ridley, "Elimination of the positive zero in fixed frequency boost and flyback converters,"
IEEE APEC Proc., 1990.
[5] Wei-Chung Wu, R. M. Bass, and J. R. Yeargan, "Eliminating the effects of the right-half plane zero in fixed frequency boost
converters," IEEE PESC Con. Rec., 1998.
[6] Right half-plane zero compensation and cancellation for switching regulators, In ventor: David W. Ritter, Assignee:
Micrel, Incorprated, San Jose, CA., Patten No.: US 2007/0252570 A1, Nov. 1, 2007.
26/26
台灣新竹‧交通大學‧電機與控制工程研究所‧808實驗室
電源系統與晶片、數位電源、馬達控制驅動晶片、 DSP/FPGA控制
Lab-808: Power Electronic Systems & Chips Lab., NCTU, Taiwan
http://pemclab.cn.nctu.edu.tw/
13