IEEE ELECTRON DEVICE LETTERS, VOL. 27, NO. 3, MARCH 2006
175
Ge n-MOSFETs on Lightly Doped Substrates With
High- Dielectric and TaN Gate
W. P. Bai, N. Lu, A. Ritenour, M. L. Lee, D. A. Antoniadis, Fellow, IEEE, and D.-L. Kwong, Senior Member, IEEE
Abstract—In this letter, we report successful fabrication of
Germanium n-MOSFETs on lightly doped Ge substrates with a
and
thin HfO2 dielectric (equivalent oxide thickness
TaN gate electrode. The highest peak mobility (330 cm2 /V s) and
saturated drive current (130 A/sq at –
V) have been
demonstrated for n-channel bulk Ge MOSFETs with an ultrathin
dielectric. As compared to Si control devices, 2.5 enhancement
of peak mobility has been achieved. The poor performance of
Ge n-MOSFET devices reported recently and its mechanism
have been investigated. Impurity induced structural defects are
believed to be responsible for the severe degradation.
=15
10 8 A)
Index Terms—Ammonia treatment, germanium (Ge), hafnium
oxide, high- dielectric, MOSFET.
I. INTRODUCTION
G
e has been considered as the channel material in replacement of Si for future high-speed CMOS technology since
it offers much higher carrier mobility than Si. Very promising
results for bulk Ge p-channel MOSFETs with both high- dielectrics [1]–[4] and GeO N dielectric [5] have been demonstrated, with 2 hole mobility enhancement. Ge-on-insulator
(GOI) devices also showed excellent performance [6]–[8]. Enigmatically, bulk Ge n-channel MOSFETs exhibited very poor
performance. The drive currents of n-type devices were one to
two orders lower than that of their p-type counterparts [2], [9],
[10], even though the fabrication processes were almost identical [2], [5], [10]. Recently, improved characteristics of bulk
Ge n-MOSFETs were reported, with plasma-PH treatment or
AlN surface passivation [4]. However the cause of the poor performance of n-channel devices has not been clarified yet. In
this letter, we report successful fabrication of Ge n-MOSFETs
cm ) substrates. The poor Ge
on lightly doped (
n-MOSFETs characteristics reported before might be ascribed
to the severe degradation on the channel transport caused by impurities related structural defects near Ge surface.
II. EXPERIMENT
MOSFETs were fabricated on (100) oriented p-type Ge subcm). Ge wafers were precleaned using
strates (Ga,
Manuscript received September 13, 2005; revised December 22, 2005. This
work was supported by the MARCO Materials, Structures and Devices Focus
Research Center. The review of this letter was arranged by Editor B. Yu.
W. P. Bai, N. Lu, and D.-L. Kwong are with the Microelectronics Research
Center, Department of Electrical and Computer Engineering, University of
Texas at Austin, Austin, TX 78758 USA (e-mail: baiwp@mail.utexas.edu).
A. Ritenour, M. L. Lee, and D. A. Antoniadis are with the Microsystems
Technology Laboratory, Massachusetts Institute of Technology, Cambridge,
MA 02139 USA.
Digital Object Identifier 10.1109/LED.2006.870242
cyclic HF dip method [11]. Rapid thermal NH anneal was performed at 450 C or 550 C for 2 min to form a stable interfacial layer between the Ge substrate and the high- dielectric [11]. 5 nm HfO film was then in situ deposited at 400 C
by rapid thermal chemical vapor deposition using C H HfO
precursor with or without introduction of O . 1500 TaN was
reactively sputtered as the top electrode layer. Ring-type transistor structures were used in order to eliminate the need of isocm As was implanted
lation. After gate patterning,
at 40 keV, followed by 500 C 5 min source/drain (S/D) activation in a forming gas furnace. 200-nm Al was sputtered on both
the frontside and the backside of the wafers for metallization.
Finally, 300 C annealing was performed in forming gas for 30
min after S/D metal pattering. In addition, Ge n-MOS capacicm and
tors on highly doped Ge p-substrates (
cm ) were also fabricated.
Si control devices were fabricated for comparison. To achieve
effective surface nitridation, NH annealing for Si devices was
carried out at 700 C for 10 sec. S/D activation annealing was
performed at 900 C for 30 s.
III. RESULTS AND DISCUSSION
The typical characteristics of Ge n-MOSFETs are displayed
–
in Fig. 1. Fig. 1(a) shows drain current-gate voltage
characteristics. The off-current
is
orders lower than
, which is due to the low substrate doping
the on-current
level and the narrow bandgap of Ge. Well-behaved drain
–
characteristics are shown in
current–drain voltage
Fig. 1(b). Fig. 1(c) shows the split capacitance–voltage (C–V)
characteristics of these devices. 10.8 equivalent oxide thickness (EOT) was extracted from the inversion C–V measurement
considering the quantum effect [12]1. The capacitance increase
V and on the inversion
on the accumulation C–V at
V is caused by the narrow bandgap of Ge
C–V at
and the lightly doped substrate, which make the p-n junction
between S/D and channel more conducting under reverse bias.
Gate leakage (I–V) characteristics [inset of Fig. 1(c)] demonV.
strate extremely low leakage current of 0.64 mA/cm at
The nonzero at zero
is due to trapping/detrapping current
and/or dielectric relaxation current [13]. The dependence of the
and at
V on the channel
peak transconductance
length (L) of these devices is shown in Fig. 2(a). In linear region,
, where
is the total resistance,
is the S/D series resistance,
is the measured drain
W is the channel width,
1CV simulation program available online at: http://www.device.eecs.
berkeley.edu/qmcv/
0741-3106/$20.00 © 2006 IEEE
176
IEEE ELECTRON DEVICE LETTERS, VOL. 27, NO. 3, MARCH 2006
Fig. 2. (a) Dependence of peak transconductance (left y axis) and drive
current at V = 2 V (right y axis) on MOSFET channel length. The peak
G and I data were obtained from the I –V plots. Due to the degradation
of drive current resulted from S/D series resistance, 30% correction at low
field and 53% correction at high field were made in calculation of mobility by
using I –V data of L = 20 m devices. (b) Extracted electron mobility as a
function of effective electrical field for Si control n-MOSFETs ( ) and bulk Ge
with different surface treatment and HfO deposition: 550 C NH + HfO
without O ; 550 CNH + HfO with O ; 450 C NH + HfO without
O .
}
Fig. 1. (a) I –V , (b) I –V , and (c) split C–V characteristics for Ge
n-MOSFET devices on lightly doped substrates with 550 C NH surface
treatment and non-O HfO deposition. Inset of (c): I–V characteristics for
these Ge n-MOSFETs.
current, and
is the ideal (non- ) drain current per
square. The intercepts on y axis of Fig. 2(a) indicate significant
, which is possibly caused by insufficient implantation
dose and/or poor ion activation at 500 C. To accurately
calculate the electron mobility
was extracted
. The
by
data and the
mobility was extracted by using
integrated inversion charge (obtained from split C–V measurements). Electron mobility as a function of the effective field
is shown in Fig. 2(b). Compared to Si control devices, 2.5
enhancement of peak mobility (330 cm /V s) is achieved for
Ge n-MOSFETs. Considering the 2 higher intrinsic electron
1
o
mobility in bulk Ge than in Si, this higher enhancement of
the channel mobility implies that nitrogen incorporation into
the interface of Ge devices brings less channel scattering and
mobility degradation than that for Si devices.
Different surface treatments and dielectric deposition
methods have led to different device performance on channel
transport, as shown in Fig. 2(b). The devices treated with higher
temperature (550 C) NH annealing and non-O HfO deposition exhibit the highest mobility (330 cm /V s). Deposition of
HfO with the introduction of O degrades the channel transport
characteristics with a peak mobility of 283 cm /V s. Devices
with 450 C NH treatment show the worst peak mobility of
230 cm /V s. NH treatment at higher temperature and non-O
dielectric deposition can form a more stable interlayer with
more nitrogen and less oxygen incorporated [14], [15]. This
helps to prevent the formation of poor quality GeO interlayer
[16], [17] and results in better channel transport characteristics.
In Table I we summarize the recent published data for bulk Ge
n-MOSFETs and p-MOSFETs, respectively [1]–[5], [9], [10].
One noticeable fact is that the doping level of the substrate used
BAI et al.: Ge n-MOSFETs ON LIGHTLY DOPED SUBSTRATES WITH HIGH- DIELECTRIC AND TaN GATE
SUMMARY
WORK;
DATA; I
177
TABLE I
(a) BULK Ge p-MOSFET RESULTS AND (b) BULK Ge n-MOSFET RESULTS PUBLISHED RECENTLY. NOTE: # REPRESENTS THIS
N
IN [9] WAS ESTIMATED FROM THE MINIMUM CAPACITANCE IN C–V MEASUREMENTS; EOT IN [1], [2], [5], [10] ARE CET
IN [2], [4] ARE VALUES AT V –V = 1:2 V. THE RECENT RESULTS OF GOI DEVICES ARE NOT INCLUDED FOR COMPARISON
BECAUSE THE SURFACE DOPING LEVELS OF GOI SUBSTRATES WERE UNCLEAR
OF
j
j
for p-MOSFET fabrication is at the range from
to
cm . For the n-MOSFETs which exhibited poor percm .
formance, the substrate doping level is above
Poor dopant activation and high S/D series resistance might be
one possible cause since S/D activation might need different activation conditions for different types of substrates. However,
is much less than the difthe saturation drain voltage
and the threshold voltage
ference of the gate-source bias
, as shown in – plots in [2] and [10], revealing the
presence of severe channel carrier scattering instead of poor S/D
contact.
Whang et al. [4] reported improved characteristics of Ge
n-MOSFETs. We notice that the p-substrate used in their
cm . The
experiment is at a doping concentration of
saturated drive current of n-MOSFETs is almost the same as
the p-type counterparts, indicating the degradation in n-type
devices still existed. Significant improvements on both peak
mobility and saturated drive current have been achieved in
our experiment by using the substrate at lower doping level
cm ). The substrate doping concentration seems
(
to play a key role in the poor n-MOSFETs performance reported recently. The much more severe degradation of drive
currents with increased substrate doping, as compared with Si
devices, indicates that besides the Coulomb scattering by ionic
impurities there exists some other scattering mechanism.
Fig. 3 shows high-frequency C–V and I–V characteristics of
Ge n-MOS capacitors fabricated on two highly doped p-subcm and
cm ) with identical
strates (
process conditions. Their almost identical I–V characteristics
indicate the same dielectric properties on both substrates.
While, devices fabricated on the substrate of
cm
exhibited abnormal C–V, i.e., low-frequency shape in
the inversion region even at 1-MHz measurement frequency. In
most semiconductors indirect recombination is the dominant
Fig. 3. High-frequency (1 MHz) C–V and I–V (inset) characteristics of Ge
n-MOS capacitors fabricated on p-substrates with doping concentration of 4
10 cm and 2 4 10 cm . 550 C NH surface treatment and HfO
deposition with O were carried out for these devices.
2
2
recombination process [18]. The generation/recombination rate
(R) is proportional to the doping concentration. Thus, the C–V
measurements in the inversion region should not depend on the
bulk doping level according to the high/low C–V criterion [19],
for high-frequency C–V and
i.e.,
for low-frequency C–V, where
is the substrate doping concentration,
is the intrinsic carrier
concentration, is the minority carrier lifetime ( =1/R), and
is the measurement frequency. Therefore, there must be
other surface recombination processes that significantly reduce
when the substrate doping level is sufficiently high.
Considering the high diffusion coefficient of Ga in Ge and
the self-diffusion coefficient of Ge (which is three and five orders of magnitude higher than that in Si, respectively), a possible
degradation mechanism is that the highly doped Ga impurities
may form diffusion-induced dislocations [20] or other structural
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IEEE ELECTRON DEVICE LETTERS, VOL. 27, NO. 3, MARCH 2006
defects near the substrate surface. These defects in turn will enhance the atom diffusion and help to form more defects [21].
The dramatically increased defects near surface lead to severe
additional scattering on the channel carriers and significantly reduce the carrier mobility. These surface defects can also act as
the generation/recombination centers of minority carriers, enhancing surface recombination process and reducing the lifetime of minority carriers. Consequently minority carriers can
response to small signals even at pretty high measurement frequency when the doping level is sufficiently high.
IV. CONCLUSION
We have demonstrated the characteristics of Ge n-MOSFETs
fabricated on lightly doped substrates. Ge devices exhibited
2.5X enhancement of peak electron mobility compared to Si
control devices. Less oxygen incorporation in the interfacial
layer improved the channel transport characteristics. The poor
performance of Ge n-MOSFETs reported recently is possibly
attributed to impurity induced structural defects near substrate
surface, which significantly increase the channel scattering and
reduce the minority lifetime when the substrate doping level is
sufficiently high.
REFERENCES
[1] C. O. Chui, H. Kim, D. Chi, B. B. Triplett, P. C. McIntyre, and K. C.
Saraswat, “A sub-400 C germanium MOSFET technology with high-
dielectric and metal gate,” in IEDM Tech. Dig., 2002, pp. 437–440.
[2] A. Ritenour, S. Yu, M. L. Lee, N. Lu, W. Bai, A. Pitera, E. A. Fitzgerald,
D. L. Kwong, and D. A. Antoniadis, “Epitaxial strained germanium
p-MOSFETs with HfO gate dielectric and TaN gate electrode,” in
IEDM Tech. Dig., 2003, pp. 433–436.
[3] N. Wu, Q. Zhang, C. Zhu, D. S. H. Chan, M. F. Li, N. Balasubramanian,
A. Chin, and D. L. Kwong, “Alternative surface passivation on Germanium for metal-oxide-semiconductor applications with high- gate dielectric,” Appl. Phys. Lett., vol. 85, pp. 4127–4129, 2004.
[4] S. J. Whang, S. J. Lee, F. Gao, N. Wan, C. X. Zhu, J. S. Pan, L. J.
Tang, and D. L. Kwong, “Germanium p- & n-MOSFETs fabricated with
novel surface passivation (plasma-PH and thin AlN) and TaN/HfO
gate stack,” in IEDM Tech. Dig., 2004, pp. 307–310.
[5] H. L. Shang, H. Okorn-Schmidt, K. K. Chan, M. Copel, J. A. Ott, P.
M. Kozlowski, S. E. Steen, S. A. Cordes, H.-S. P. Wong, E. C. Jones,
and W. E. Haensch, “High mobility p-Channel germanium MOSFETs
with a thin Ge oxynitride gate dielectric,” in IEDM Tech. Dig., 2002, pp.
441–444.
[6] T. Tezuka, S. Nakaharai, Y. Moriyama, N. Sugiyama, and S.-I. Takagi,
“Selectively-formed high mobility SiGe-on-Insulator pMOSFETs with
Ge-rich strained surface channels using local condensation technique,”
in VLSI Symp. Tech. Dig., 2004, pp. 198–199.
[7] D. S. Yu, A. Chin, C. C. Laio, C. F. Lee, C. F. Cheng, W. J. Chen, C.
Zhu, M.-F. Li, W. J. Yoo, S. P. McAlister, and D. L. Kwong, “3D GOI
CMOSFETs with novel IrO (Hf) dual gates and high- dielectric on
1P6M-0.18 um-CMOS,” in IEDM Tech. Dig., 2004, pp. 181–184.
[8] H. Shang, J. O. Chu, S. Bedell, E. P. Gusev, P. Jamison, Y. Zhang, J.
A. Ott, M. Copel, D. Sadana, K. W. Guarini, and M. Ieong, “Selectively formed high mobility strained Ge PMOSFETs for high performance CMOS,” in IEDM Tech. Dig., 2004, pp. 157–160.
[9] C. O. Chui, H. Kim, P. C. McIntyre, and K. C. Saraswat, “A germanium NMOSFET process integrating metal gate and improved hi-K dielectrics,” in IEDM Tech. Dig., 2003, pp. 437–440.
[10] H. Shang, K.-L. Lee, P. Kozlowski, C. D’Emic, I. Babich, I. Babuch,
E. Sikorski, M. Ieong, H.-S. P. Wong, and W. Haensch, “Self-aligned
n-channel germanium MOSFETs with a thin Ge oxynitride gate dielectric and tungsten gate,” IEEE Electron Device Lett., vol. 25, no. 2, pp.
135–137, Feb. 2004.
[11] W. P. Bai, N. Lu, J. Liu, A. Ramirez, D.-L. Kwong, D. Wristers, A.
Ritenour, L. Lee, and D. Antoniadis, “Ge MOS characteristics with CVD
HfO gate dielectrics and TaN gate electrode,” in VLSI Symp. Tech. Dig.,
2003, pp. 121–122.
[12] K. Yang et al., “Quantum effect in oxide thickness determination from
capacitance measurement,” in VLSI Symp. Tech. Dig., 1999, pp. 77–78.
[13] W. Luo, D. Sunardi, Y. Kuo, and W. Kuo, “Stress Testing and Characterization of high- Dielectric thin films,”, 2003 IRW final report.
[14] E. P. Gusev, H. Shang, M. Copel, M. Gribelyuk, C. D’Emic, P. Kozlowski, and T. Zabel, “Microstructure and thermal stability of HfO
gate dielectric deposited on Ge(100),” Appl. Phys. Lett., vol. 85, pp.
2334–2336, 2004.
[15] S. Van Elshocht, B. Brijs, M. Caymax, T. Conard, T. Chiarella, S. De
Gendt, B. De Jaeger, S. Kubicek, M. Meuris, B. Onsia, O. Richard, I.
Teerlinck, J. Van Steenbergen, C. Zhao, and M. Heyns, “Deposition of
HfO on Germanium and the impact of surface pretreatments,” Appl.
Phys. Lett., vol. 85, pp. 3824–3826, 2004.
[16] R. S. Johnson, H. Niimi, and G. Lucovsky, “New approach for the fabrication of device-quality Ge/GeO /SiO interfaces using low temperature remote plasma processing,” J. Vac. Sci. Technol., vol. A 18, pp.
1230–1233, 2000.
[17] R. P. H. Chang and A. T. Fiory, “Inversion layers on germanium with
low-temperature-deposited aluminum-phosphorus oxide dielectric
films,” Appl. Phys. Lett., vol. 49, pp. 1534–1536, 1986.
[18] B. G. Streetman and S. Banerjee, Solid State Electronic Devices. Englewood Cliffs, NJ: Prentice-Hall, 2000, p. 117.
[19] E. H. Nicollian and J. R. Brews, MOS Physics and Technology. New
York: Wiley, 1982.
[20] B. Tuck, Introduction to Diffusion in Semiconductors. Stevenage,
U.K.: Peregrinus, 1974, p. 213.
[21] B. I. Boltaks, Diffusion in Semiconductors: Infosearch Ltd., 1963, ch.
VI.