AN2170
APPLICATION NOTE
MOSFET Device Effects on
Phase Node Ringing in VRM Power Converters
INTRODUCTION
The growth in production volume of industrial equipment (e.g., power DC-DC converters devoted to lowmedium-voltage applications) has dramatically increased in recent years. This widespread increase occurred along with a similar production increase of power MOSFET devices, due to their higher switching
performance and ease of control with respect to bipolar transistors. High-tech products require more and
higher performance devices because of advancing specifications and a growing demand for highly efficient systems and equipment, such as PC motherboards, power supplies, and hand tools. These stringent
requirements demand innovation from power device designers, who must design to performance specifications, including suitable On-state resistance and gate-charge values, as well as high reliability characteristics which help to reduce wasted power.
The last generation of low voltage Power MOSFETs has achieved very impressive performances in terms
of Figure of Merit (FOM) RON*Qg. These switches have very low static loss, increased switching speed,
and very low driving energy requirements. However, these higher performing devices have also highlighted some undesired phenomena already present in their application.
– In particular, the fast voltage transition of the phase node can cause the inadvertent turn-on of the lowside switch, resulting in a converter malfunction and reducing efficiency.
– Another consequence of the increased switching speed is the ringing phenomenon, which occurs on
the phase node of a Buck converter used as a Voltage Regulated Module (VRM). Although this ringing
does not cause power loss (because of the fairly high Q), it could induce some sort of malfunction and/
or undesired stress of the power switches.
For these reasons, it is useful to understand the main parameters, their influence, and possible ways to
minimize undesired effects.
Rev 1
June 2005
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AN2170 - APPLICATION NOTE
TABLE OF CONTENTS
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
CdV/dt-INDUCED TURN-ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Buck Converter Simplified Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Buck Converter Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Low-Side Switch Current Paths, Control MOSFET Turned On . . . . . . . . . . . . . . . . . . . . . 5
Minimum dV/dt to Cause VGS > VTH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
VOLTAGE RINGING ON THE PHASE NODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 5. Switching Waveforms with Voltage Ringing on the Phase Node. . . . . . . . . . . . . . . . . . . . 6
Stray Inductance Effects on Phase Node Over Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 6. Energizing of L, L1, L2, L3 During Synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 7. Turn-on of the Upper Device and Over-Voltage Phenomenon . . . . . . . . . . . . . . . . . . . . . 7
APPROACHES TO VOLTAGE PHASE NODE RINGING REDUCTION . . . . . . . . . . . . . . . . . . . . . . . . 8
PCB Layout Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 8. VRM Converter Experimental Set-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 1. VRM Converter Device Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Changing the Low-Side Switch Gate Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Using a Snubber Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 9. Gate Resistance Effect on Strip MOSFET Switching: Without External Gate Resistance10
Figure 10.Gate Resistance Effect on Strip MOSFET Switching: With 3.3Ω Gate Resistance . . . . 10
Figure 11.Snubber Circuit Effect on Strip MOSFET Switching: Without Snubber . . . . . . . . . . . . . . 11
Figure 12.Snubber Circuit Effect on Strip MOSFET Switching: With Snubber . . . . . . . . . . . . . . . . 11
Figure 13.Snubber Circuit, Cross-Conduction Effects on the VRM Efficiency . . . . . . . . . . . . . . . . 12
CONCLUSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
APPENDIX A.VOLTAGE OSCILLATION SPIKE POTENTIAL ANALYSIS . . . . . . . . . . . . . . . . . . . . . 13
Figure 14.Simplified Equivalent Circuit During Ringing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 15.Definition of Peak Voltage and Oscillation Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Peak Voltage and Oscillation Frequency Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 2. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
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AN2170 - APPLICATION NOTE
CdV/dt-INDUCED TURN-ON
With buck converters dedicated to VRM applications (see Figure 1. and Figure 2.), it is essential that the
user chooses the appropriate pair of switching MOSFETs. Devices having quite similar nominal characteristics can behave in a very different manner, leading to an appreciably altered overall system efficiency.
This is especially the case with the switching behavior of a high-side switch which has a significant effect
on the low-side switch. The rise speed of the phase node when the high-side device switches on could
have two detrimental effects, depending on the device characteristics and how fast the voltage transition
is.
Figure 1. Buck Converter Simplified Schematic
Phase
Node
SW1
VIN
+
–
L
+
C
Control
IC
VO
SW2
AI11108
Figure 2. Buck Converter Waveforms
TS
VGS (SW1)
tON
tOFF
δTS
(1 – δ)TS
VGS (SW2)
Dead Time
ISW1
IL
ISW2
IL
ID_SW2
IL
AI11109
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The fast turn-on of the high-side switch (the control MOSFET) could induce a parasitic turn-on of the synchronous MOSFET, thus causing undesired conduction. This cross-conduction may originate from an improper dynamic polarization of the gate of the low-side device. Despite the fact that the gate is forced to
Ground by the control driver (see Figure 3., page 5), the capacitive divider that is formed by the parasitic
capacitances CGATE-DRAIN (CGD) and CGATE-SOURCE (CGS) forces the gate voltage of the low-side switch
to increase, and the threshold voltage of the device can be overcome. The drain-source voltage rate-ofchange leads to a current injection into the MOSFET gate, thus increasing the voltage at the gate node.
If the voltage rise time of the phase node (see Figure 3. and Figure 4., page 5) is much less than the time
constant of the equivalent gate circuit of the low side switch (1),
T m « R t ( C GS + C GD )
then the maximum gate voltage is described by the following equation (2):
C GD
V G S, max ≅ ----------------------------- V m
C GD + C GS
Since a spurious turn-on causes power loss, which in turn leads to decreased efficiency, any way to avoid
it is highly recommended. As shown in the maximum gate voltage equation (2), it is obvious that in order
to reduce the possibility of spurious turn-on of the low-side switches, the expression, “CGD/(CGS + CGD)”
deserves particular attention on the part of device designers. In fact, the amplitude of the gate voltage
peak is dependent on the absolute value of the intrinsic capacitances of the device, as well as on the capacitive divider at the gate node (which also needs to be considered). In other words, in order to reduce
the detrimental effects of fast variations of the drain node potential on the gate node, designers need to
achieve a well-balanced capacitive divider and low impedance gate path at the gate node of the low-side
switch.
Additionally, the dV/dt in the drain node can also be responsible for the turn-on of the parasitic transistor
in the inner MOSFET structure. If the voltage at the base node of the Bipolar Junction Transistor (BJT)
gets over the built-in potential of the base-emitter junction, it can lead to possible device failure.
Due to the dV/dt in the drain node, the drain-body capacitance (CDB) produces a current injection in the
base of the parasitic NPN bipolar transistor (see Figure 3.). Therefore, if the voltage drop on the parasitic
resistor R B exceeds the base emitter threshold voltage, the parasitic NPN bipolar transistor will turn on.
This condition can be expressed by using the following equation (3):
d V DS
V BE
C D B -------------- = ---------dt
RB
A lot of care has been taken at the Power MOSFET design level to minimize both RB and C DB. The design
allows for safe switching even if dV/dt exceeds several volts per nanosecond.
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AN2170 - APPLICATION NOTE
Figure 3. Low-Side Switch Current Paths, Control MOSFET Turned On
Drain
a
b
CGD
CDB
Gate
NPN
ZGS
CGS
dV
dt
RB
Source
AI11110
Figure 4. Minimum dV/dt to Cause VGS > VTH
Vm
VDS
VTH
VGS
t
Tm
AI11111
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VOLTAGE RINGING ON THE PHASE NODE
Another phenomenon can be caused by the concurrent effect of the high switching speed, the stray inductance of the board, and the parasitic capacitance of both the MOSFET and the eventual schottky diode. It
is the presence of wide voltage oscillations on the so-called “phase node” (see Figure 5.).
The parasitic inductance is energized during the synchronization cycle as it is depicted in Figure
6., page 7. However, as long as the high-side switch is turned-on (see Figure 7., page 7), the energy that
has been previously stored in the inductor will lead to voltage oscillations with potentially dangerous voltage spikes. A theoretical analysis of this phenomenon using a simple, comparable circuit is given in APPENDIX A., page 13, which explains some of the relationships between voltage peak, oscillation
frequency, the dumping factor of some circuitry elements, as well as device characteristics.
Figure 5. Switching Waveforms with Voltage Ringing on the Phase Node
Note: VGS=5V/div, VDS=5V/div, time=100ns/div
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AN2170 - APPLICATION NOTE
Stray Inductance Effects on Phase Node Over Voltage
The “C” capacitance is equal to the output (COSS) drain-to-source capacitance of the low-side MOSFET.
If a Schottky diode is used, its capacitance has to be taken in account as well.
Note: “L” is considered the effective stray inductance of the high-side power MOSFET which is added to
the trace inductance of the high-side MOSFET’s source to the low-side drain connection, as well as to the
trace inductance of the low-side ground connection.
The same consideration applies to “R,” and oscillations only occur if:
L
R < 2 ---C
Figure 6. Energizing of L, L1, L2, L3 During Synchronization
VCC
High-side
Turned OFF
–
–
L2
L
+
Charge
+
+
Low-side
C
Load
C1
–
–
L1
L3
+
+
AI11115
Figure 7. Turn-on of the Upper Device and Over-Voltage Phenomenon
VCC
High-side
–
–
L2
L
+
Extra
Voltage
+
+
Low-side
C
C1
–
L1
Load
–
L3
+
+
AI11116
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AN2170 - APPLICATION NOTE
APPROACHES TO VOLTAGE PHASE NODE RINGING REDUCTION
Voltage phase node ringing is influenced by several parameters. Several circuit approaches may be used
to reduce the severity of this transient:
■
Layout Optimization of the Printed Circuit Board (PCB)
■
Changing the Low-Side Switch Gate Resistance
■
Use a Snubber Circuit
PCB Layout Optimization
This minimizes the effects of the parasitic component controlling this phenomenon, which includes both
stray inductances and capacitances. Good layout technique involves the following:
– The output capacitor positioning such that they are located in symmetrically in relation to the
output inductors of the converter (this will minimize the output voltage ripple).
– The inductance and capacitor connections have to be as short as possible, and formed with a wide
area of copper.
– A multilayer PCB is required to provide an effective Ground plane.
– The MOSFET drive connection should be short, and the high current paths should be wide and
short.
Note: In order to attain good thermal exchange, some of the board areas may be used to provide
a heat sink to the MOSFETs and diodes.
If PCB optimization is not enough to limit the ringing to the desired value, then a design with an appropriate
resistance value and an auxiliary snubber circuit (connected in parallel to the low-side switch device) has
to be considered. The design can be applied to a test circuit to see how it will work with an actual VRM
(see Figure 8.). This type of power converter has the following characteristics:
– Switching frequency = 300kHz
– Rated Input Voltage = 12V
– Rated Output Voltage = 1.8V
– Rated Current = 10A
Figure 8. VRM Converter Experimental Set-up
+
VIN
–
High-side
1
16
2
15
3
4
5
14
Control
IC
13
+
12
6
11
7
10
8
9
VOUT
–
Low-side
AI11118
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AN2170 - APPLICATION NOTE
A logic and control IC unit is used to synchronize the gate voltages of the low-side and high-side switches
to provide a suitable dead-time between the two control signals. The output voltage of the buck converter
is sensed through a resistive network that acts as the input signal on the IC unit logic for dynamic regulation of the output voltage during load variations.
The switching behavior of the low-side device has been tested with different solutions. The main electrical
characteristics of the two switching devices are reported in Table 1.
Table 1. VRM Converter Device Characteristics
Device Type
BVDSS [V]
VTH (min) [V]
RDSon[mΩ]
Qg [nC]
RG [Ω]
COSS [pF]
High-side
30
1.0
8
9
1.2
285
Low-side
30
1.0
3.25
30
2.3
650
Changing the Low-Side Switch Gate Resistor
After the PCB design has been optimized, the next adjustment would the gate resistance of the low-side
switch. The increased gate resistance value allows for a reduction of voltage ringing (see Figure
9., page 10 and Figure 10., page 10).
In the experimental results reported for Figure 10., it appears that both the ringing and the voltage spikes
are reduced as long as the gate resistance increases. However, with this adjustment, the increased presence of noise that exceeds the gate threshold of the Power MOSFET has also been detected. This causes
the spurious turn-on of the converter which originates from the increased gate impedance, and therefore
decreases the converter efficiency (see Figure 13., page 12).
Using a Snubber Circuit
A more efficient way to reduce the ringing voltage with very few consequences to the converter efficiency
is to use a snubber circuit. Figure 11., page 11 and Figure 12., page 11 illustrate the commutation difference without and with a light RC Snubber (C = 1nF, R = 4.7Ω) connected in parallel to the low-side MOSFET. The beneficial effect of the snubber circuit on the voltage ringing reduction clearly emerges.
Moreover, this solution leads to a low number of voltage spikes and a small efficiency decrease with respect to the commutation without the snubber circuit. Figure 13., page 12 demonstrates the converter efficiency with and without the snubber circuit.
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AN2170 - APPLICATION NOTE
Figure 9. Gate Resistance Effect on Strip MOSFET Switching: Without External Gate Resistance
Note: VGS=5V/div, VDS=5V/div, time=100ns/div.
Figure 10. Gate Resistance Effect on Strip MOSFET Switching: With 3.3Ω Gate Resistance
Note: VGS=5V/div, VDS=5V/div, time=100ns/div.
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AN2170 - APPLICATION NOTE
Figure 11. Snubber Circuit Effect on Strip MOSFET Switching: Without Snubber
Note: VGS=2V/div, VDS=5V/div, time=20ns/div.
Figure 12. Snubber Circuit Effect on Strip MOSFET Switching: With Snubber
Note: VGS=2V/div, VDS=5V/div, time=20ns/div.
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AN2170 - APPLICATION NOTE
Figure 13. Snubber Circuit, Cross-Conduction Effects on the VRM Efficiency
CONCLUSION
The parasitic components of the board and high commutation speed of the strip MOSFET device indicate
the probable presence of high voltage ringing in the phase node. The previously mentioned approaches,
such as increasing the gate resistance or using a suitable snubber circuit have been successfully tested
and proven to reduce phase node voltage ringing. The use of a small snubber circuit has been observed
to significantly reduce the phase node voltage ringing without negatively affecting converter efficiency.
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AN2170 - APPLICATION NOTE
APPENDIX A. VOLTAGE OSCILLATION SPIKE POTENTIAL ANALYSIS
Figure 14. Simplified Equivalent Circuit During Ringing
R
VO
L
C
AI11117
Note: Oscillation occurs if R < RLIM.
Figure 15. Definition of Peak Voltage and Oscillation Frequency
VPEAK
T = 1/freq
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AN2170 - APPLICATION NOTE
Peak Voltage and Oscillation Frequency Analysis
1
Freq = -----------------2 π LC
V PEAK
π⎞
⎛ – --⎛
⎞
⎝ ω-⎠
⎜
e
sin ( π + Γ ) ⎟
= V O ⎜ 1 – --------------------------------------⎟
⎜
⎟
ω LC
⎝
⎠
ω =
R 2
1
-------- – ⎛ -------⎞
L C ⎝ 2 L⎠
ω
Γ = arc tan ⎛ ----⎞
⎝ α⎠
R
α = ------2L
L
R < R lim = 2 ---C
Note: Ringing occurs only if R<R lim.
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REVISION HISTORY
Table 2. Document Revision History
Date
Version
21-Jun-05
1
Description
First edition
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AN2170 - APPLICATION NOTE
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