Chapter 4
Multi-digit Display
1
CHAPTER 4. MULTI-DIGIT DISPLAY
4.1
Section Overview
Section 3 developed a design to drive a 7-segment display. This section will use POV (Persistance of Vision) to
display all 4 digits. Essentially this will turn on the 1000’s digit for a few milliseconds, then the 100’s digit, then the 10’s
digit, and finally the 1’s digit, before repeating the cycle starting at the 1000’s digit. A state machine controls the cycle
between the different digits.
4.2
Objective
In this section, the following items will be covered:
1. Build a system that will diplay a large binary value (maybe 10 bits) as an input and output 0 - 1023 on the seven
segment board.
2. Use the button board to generate an 8 bit digital value.
3. Design and test a state machine that will cycle through turning on 1 digit at a time.
4. Import a provided math module that separates a 10 digit value into 4 distinct 4 bit values for each digit.
5. Combine the digit cycler state machine, the provided digit separater module, and lab 3 into a multi-digit display.
6. Simulate the design and validate the hardware.
4.3
Materials
1. Lattice Diamond 3.5 software
2. MachXO2 Breakout board
3. 4digit.0
4. The ECE 271 textbook, Digital Design and Computer Architecture by Drs. David and Sarah Harris
4.4. PROCEDURE:
4.4
Procedure:
There are 6 steps to digital logic design
Figure 4.1: Use this process for the designing section 4.
In section 4 we will follow the same implementation steps we have used in previous labs. Only this time the
implementation steps will be applied to smaller blocks and again before integrating all the blocks into one system.
CHAPTER 4. MULTI-DIGIT DISPLAY
4.5
Display four digit reading on 4digit.0 board
Take lessons learned in section 3 about the 4digit.0 board and what we learned in section 4 about HDL and state
machines to make a display for the ADC readings.
Procedure:
1. Design HDL system that will display numerical values on all four digits of the seven segment board. A state
machine should be used to cycle between the four digits (four states). Use the 7-Seg SEL inputs to choose
which digit is being displayed. The frequency at which the digits are cycles will determine the brightness of the
LEDs.
Refer to HDL Example 4.24 on the Verilog reference sheet, available at Tekbots.com, for an
example on how to write a decoder in Verilog for a seven segment display.
A multiplexer works well for switching the value displayed on each digit.
Look up persistence of vision to find out how quickly the state machine should cycle
2. Using your design, enter the digital logic into the software
3. Simulate with enough possible inputs to have confidence that your design will perform as expected.
4. Follow synthesis and map design from previous labs, by connecting the seven segment board control lines to
the pins you selected in the pin assignments.
Figure 4.2: Display Board Wiring Diagram and Digit Select Table.
5. Program the FPGA
6. Test the implemented system by hard coding a multi-digit number into the input of the FPGA logic to verify that
you get the expected results.
TA Signature:
(A meaningful analog voltage is digitized and displayed on the seven segment display board)
4.6. STUDY QUESTIONS
4.6
Study Questions
1. Include a detailed block diagram of Section 4, the HDL Schematic, and a copy of the Verilog source.
4.7
Challenge
1. Use the PWM input on the 4digit.0 board to control the brightness of the numbers.