Shift Registers and Counters
ShiftReg @ P. Klimo
Shift Registers and Counters
Counters are sequential clocked circuits that:
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count pulses (Note the counting sequence can be other than the binary, e.g. Grey
Code, Binary Coded Decimal (BCD), etc.
repeatedly go through a cycle of ( not necessary all) states visiting each of the states
only once in each cycle.
The length of the sequence is called Modulo. (e.g. a decade counter counting from 0
to 9 is a modulo 10 counter)
Two types : Asynchronous (Ripple) and Synchronous.
Example of Asynchronous (Ripple) Modulo 8 Counter:
Modulo 8 Counter
( counts between 0 and 23-1)
Time propagation delay td (tPLH or tPHL in data sheets) - is the shortest time interval
between the active clock transition and the resulting change of the FF’s output Q.
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Shift Registers and Counters
ShiftReg @ P. Klimo
Note:
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the clock to each JK flip flop is delayed with respect to the input clock.
the total delay (i.e. the ripple) is proportional to the number of stages (i.e. 3x tpd
for Mod 8 counter )
the transition to new state is not simultaneous (synchronous)
for the correct operation the period between the two subsequent active edges of
the input clock needs to exceed the total propagation delay. This determines the
maximum operational frequency.
Example:
Estimate the maximum clock frequency for Mod 256 asynchronous counter implemented
with JK Flip Flops each having a propagation delay tpd = 6 ns.
Answer: Mod 256 counter requires 8 stages (28 = 256) so the total ripple delay is 8x6 ns
= 48 ns. The clock period T has to be larger than 48 ns so the maximum clock frequency
is 1/48 ns = 20 MHz.
Exercise: Modify the above mod 3 Ripple Counter by taking the clock signal for the
second and the third JK Flip Flops from outputs Q’ rather than Q. Show that this ripple
counter counts down rather than up.
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Shift Registers and Counters
Counters with MOD < 2 n
Example: Modulo 6 Counter:
The counting sequence:
C
B
A
0
0
0
reset state
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
last state
1
1
0
temporary state
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ShiftReg @ P. Klimo
Shift Registers and Counters
ShiftReg @ P. Klimo
Synchronous Counters:
Example of Modulo 4 Counter.
Note:
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The transition to the new state is synchronous with the clock
The delay of output is independent of the number of stages.
The maximum clock frequency is limited only by the operational speed of the JK
flip flops used (typically 20 MHz for the 74LS series but up to 50 MHz for the 74
HC fast series)
Exercise: Modify the above synchronous Modulo 4 counter so that it counts down rather
then up.
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Shift Registers and Counters
ShiftReg @ P. Klimo
Example of Modulo 8 Counter.
The Last stage requires Control Logic to feed inputs Jc and Kc of the third Flip-Flop.
Step 1: Derive the Truth Table for the Control Logic outputs JC and KC using the
Excitation Map for the JK Flip Flop:
Present State
C
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
A
0
1
0
1
0
1
0
1
Next State
C*
0
0
0
1
1
1
1
0
B*
0
1
1
0
0
1
1
0
A*
1
0
1
0
1
0
1
0
required
Jc
required
Kc
0
0
0
1
X
X
X
X
X
X
X
X
0
0
0
1
Step 2: Derive (minimum) Boolean expressions for Control Logic outputs JC and KC:
Choosing Do Not Care values denoted by X as shown in the table below makes the Jc and
Jk independent of the (input) variable C:
Present State
C
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
A
0
1
0
1
0
1
0
1
Next State
C*
0
0
0
1
1
1
1
0
B* A*
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
5
required
Jc
required
Kc
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
Shift Registers and Counters
ShiftReg @ P. Klimo
The above truth table gives the following expressions:
Jc = B.A
Kc = B.A
Step 3: Implement the logic equations from Step 2:
Example: Design a Synchronous Modulo 3 Down Counter.
Present State
B
0
1
0
A
0
0
1
Next State
B*
1
0
0
required
JB KB
required
JA KA
1 X
X 1
0 X
0 X
1 X
X 1
A*
0
1
0
By choosing X's carefully the expressions simplify.
Excitation equations are: JB = QA'
KB = QB
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JA = QB
KA = QA
Shift Registers and Counters
ShiftReg @ P. Klimo
Timing Diagram
With FF, the transitions to the next state are synchronised with a clock (rising or falling )
edges.
Synchronous inputs have to be stable for a minimum time ts – set up time before the
arrival of the clock edge and remain stable for a a duration th – hold up time.
Asynchronous inputs (set and reset) override the clock.
so the J, K inputs have to be stable for ts + th
and td > th
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Shift Registers and Counters
ShiftReg @ P. Klimo
Shift Registers:
Clocking the shift registers shifts right or left the binary number held in the FFs.
Both the input and the output may be configured for serial or parallel data transfer.
Applications are: algebraic operations (multiply and divide by two) and serial to parallel
conversion.
Four Stage SISO implemented from JK FFs.
Four Stage Serial In-Serial Out (right SISO) made of D FFs
To obtain a parallel input- serial output shift register one uses an additional control signal
shift/ load' which operates the data selection switches shown below
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Shift Registers and Counters
ShiftReg @ P. Klimo
When the shift is asserted (control high) the switch connects the input of the flip flop Dn
to the output of the Dn-1 flip flop ( Qn-1 ) and the register operates as a shift register. With
Load asserted (control low) the shift operation is suspended and the input of the flip flop
Dn is connected to the parallel data bit Bn.
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Shift Registers and Counters
ShiftReg @ P. Klimo
Counters using Shift Registers:
Block Diagram of a Counter
A counter based on a n stage shift register can be viewed as a FSM with up to 2n states.
We can label the states by assigning them binary numbers held by the shift register.
Depending on the type of feedback we can have: Ring Counters, Johnson (or Twisted)
Ring Counter, Linear Feedback Shift Register (LFSR
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Ring counter has a straight feedback from serial output to serial in. It
circulates through n states so it is also called modulo n ring counter.
Normally, with the ring counter only one of the FF is set high. The outputs
can be fed into an encoder in order to obtain the desired output values.
Self Starting Ring Counter
Example: Design of Self-Starting and Self-correcting Ring Counter.
It is required to design a sequential controller with a four bit output, repeating the
sequence Ch, 6h, 3h, 1h, 8h.
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Shift Registers and Counters
ShiftReg @ P. Klimo
Solution:
Because length of cycle is 5 needs a 5 stage counter
Hex Ouput
Binary representation:
B3 B2 B1 B0
C
1 1 0 0
6
0 1 1 0
3
0 0 1 1
1
0 0 0 1
8
1 0 0 0
We notice that the binary sequence can be realized using a 5 stage right shifting ring
counter loaded with the combination 11000, where only the first four outputs from the
left are used i.e:
Flip Flop
QA QB QC QD QE
C
1 1 0 0 | 0
6
0 1 1 0 | 0
3
0 0 1 1 | 0
1
0 0 0 1 | 1
8
1 0 0 0 | 1
Truth table for the serial input DA of Flip Flop A:
Flip Flop
QA QB QC QD QE
0
0
0
1
1
DA =
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
1
0
QB'.QC'.QD'.QE' ; first and fifth row
+ QA'.QB'.QC'.QD ; second and third row
+ QA.QB'.QC'.QD' ; fourth and fifth row
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; set the first 1 on self-start
; rotate 1
; set the second 1 on error
; rotate 1
; set the second 1 on error
Shift Registers and Counters
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ShiftReg @ P. Klimo
Johnson Counter has an inverted feedback. It has 2n states. It can achieve a
high operational speed because it does not follow the binary count sequence.
The decoded outputs are free of glitches because any output is subject to the
delay of only one stage.
Twisted Ring or Johnson Counter
Example: Possible States of a 4 stage Johnson Counter
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Shift Registers and Counters
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ShiftReg @ P. Klimo
Linear Feedback Shift Register (LFSR): use only exclusive OR gates in the
feedback loop. With a suitable feedback a maximum counting sequence can
be obtained (2n-1 states). For example, for a three stage LSFR the maximum
counting sequence is obtained if the XOR feedback is taken from the last two
stages.
LFSR can be used as a pseudo-random number generator and has applications
in cryptography.
Example: A 3 Stage LFSR
State Table for 3 stage LFSR:
QC
0
0
1
0
1
1
1
QB
0
1
0
1
1
1
0
QA
1
0
1
1
1
0
0
DA
0
1
1
1
0
0
1
Note: There are 7 out of 8 possible states. The state 000 is not admissible
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