OA1ZHA, OA2ZHA,
OA4ZHA
High precision 5 µV zero drift, low-power op amp
Datasheet - production data
6LQJOH 2$=+$
Benefits
'XDO 2$=+$
 High precision op amp without the need of
calibration
 Accuracy virtually unaffected by temperature
change
6&
0LQL62
'XDO 2$=+$
4XDG 2$=+$
Applications
 Wearable
 Fitness and healthcare
 Medical instrumentation
')1[
4)1[
Description
Features
 Very high accuracy and stability: offset voltage
5 µV max at 25°C, 8 µV over full temperature
range (-40°C to 125°C)
 Rail-to-rail input and output
 Low supply voltage: 1.8 - 5.5 V
 Low power consumption: 40 µA max. at 5 V
 Gain bandwidth product: 400 kHz
 High tolerance to ESD: 4 kV HBM
 Extended temperature range: -40 to +125°C
 Micro-packages: SC70-5, DFN8 2x2, and
QFN16 3x3
The OA1ZHA, OA2ZHA, OA4ZHA series of low
power, high precision op amp, offer very low input
offset voltages with virtually zero drift.
OA1ZHA, OA2ZHA, OA4ZHA are respectively the
single, dual and quad operational amplifier
versions, with pinout compatible with industry
standards.
The OA1ZHA, OA2ZHA, OA4ZHA series offers
rail-to-rail input and output, excellent
speed/power consumption ratio, and 400 kHz
gain bandwidth product, while consuming less
than 40 µA at 5 V. All devices also feature an
ultra-low input bias current.
The OA1ZHA, OA2ZHA, OA4ZHA family is the
ideal choice for wearable, fitness and healthcare
applications.
Table 1. Device summary
Order code
Temperature range
OA1ZHA22C
Package
Packaging
SC70-5
OA2ZHA22Q
K44
DFN8 2x2
-40 to +125 °C
Marking
K33
Tape and reel
OA2ZHA34S
MiniSO8
K143
OA4ZHA33Q
QFN16 3x3
K193
March 2014
This is information on a product in full production.
DocID025994 Rev 1
1/34
www.st.com
Contents
OA1ZHA, OA2ZHA, OA4ZHA
Contents
1
Package pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Absolute maximum ratings and operating conditions . . . . . . . . . . . . . 4
3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1
5
6
2/34
Operation theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1.1
Time domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1.2
Frequency domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.2
Operating voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.3
Input pin voltage ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.4
Rail-to-rail input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.5
Input offset voltage drift over temperature . . . . . . . . . . . . . . . . . . . . . . . . 20
4.6
Rail-to-rail output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.7
Capacitive load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.8
PCB layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.9
Optimized application recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.10
EMI rejection ration (EMIRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.11
Application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.11.1
Oxygen sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.11.2
Precision instrumentation amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.11.3
Low-side current sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.1
SC70-5 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.2
DFN8 2x2 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.3
MiniSO8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.4
QFN16 3x3 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
DocID025994 Rev 1
OA1ZHA, OA2ZHA, OA4ZHA
Package pin connections
Figure 1. Pin connections for each package (top view)
9&&
,1 9&&
287
,1
1&
,1 287
,1
9&&
1&
,1
287
287
,1
1& ,1
9&&
1&
287
,1
9&&
,1
287
,1
,1
9&&
287
,1
,1
,1
,1
287
287
DFN8 2x2
9&&
9&&
,1
,1
SC70-5
,1
1
Package pin connections
MiniSO8
QFN16 3x3
1. The exposed pads of the DFN8 2x2 and the QFN16 3x3 can be connected to VCC- or left floating.
DocID025994 Rev 1
3/34
34
Absolute maximum ratings and operating conditions
2
OA1ZHA, OA2ZHA, OA4ZHA
Absolute maximum ratings and operating conditions
Table 2. Absolute maximum ratings (AMR)
Symbol
Vcc
Vid
Vin
Iin
Tstg
Parameter
Supply voltage
(2)
±Vcc
Tj
Vcc- - 0.2 to Vcc++ 0.2
(4)
10
mA
-65 to +150
°C
Input voltage
Storage temperature
(5)(6)
SC70-5
205
DFN8 2x2
57
MiniSO8
190
QFN16 3x3
39
Maximum junction temperature
HBM: human body model, OA1ZHA
ESD
V
(3)
Thermal resistance junction-to-ambient
Rthja
Unit
6
Differential input voltage
Input current
Value
(1)
MM: machine model, OA1ZHA
only(7)
only(8)
CDM: charged device model
°C/W
150
°C
4
kV
300
V
1.5
CDM: charged device model, QFN16 3x3
TBD
Latch-up immunity
200
kV
mA
1. All voltage values, except differential voltage, are with respect to network ground terminal.
2. The differential voltage is the non-inverting input terminal with respect to the inverting input terminal.
3. Vcc - Vin must not exceed 6 V, Vin must not exceed 6 V.
4. Input current must be limited by a resistor in series with the inputs.
5. Short-circuits can cause excessive heating and destructive dissipation.
6. Rth are typical values.
7. Human body model: 100 pF discharged through a 1.5 kresistor between two pins of the device, done for
all couples of pin combinations with other pins floating.
8. Machine model: a 200 pF cap is charged to the specified voltage, then discharged directly between two
pins of the device with no external series resistor (internal resistor < 5 ), done for all couples of pin
combinations with other pins floating.
Table 3. Operating conditions
Symbol
4/34
Parameter
Vcc
Supply voltage
Vicm
Common mode input voltage range
Toper
Operating free air temperature range
Value
1.8 to 5.5
DocID025994 Rev 1
Vcc- - 0.1 to Vcc+ + 0.1
-40 to +125
Unit
V
°C
OA1ZHA, OA2ZHA, OA4ZHA
3
Electrical characteristics
Electrical characteristics
VCC+ = 1.8 V with VCC- = 0 V, Vicm = VCC/2, T = 25 °C, and RL = 10 k connected to VCC/2
(unless otherwise specified)
Table 4. Electrical characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
1
5
Unit
DC performance
T = 25 °C
Vio
Vio/T
Input offset voltage
-40 °C < T< 125 °C
Input offset voltage drift(1)
-40 °C < T< 125 °C
T = 25 °C
Iib
Input bias current (Vout = VCC/2)
30
50
200(2)
Input offset current (Vout = VCC/2)
nV/°C
300(2)
100
400(2)
pA
600(2)
-40 °C < T< 125 °C
Common mode rejection ratio 20 log
(Vicm/Vio), Vic = 0 V to VCC,
Vout = VCC/2, RL > 1 M
T = 25 °C
110
-40 °C < T< 125 °C
110
118
Avd
Large signal voltage gain
Vout = 0.5 V to (Vcc - 0.5 V)
T = 25 °C
-40 °C < T< 125 °C
110
VOH
High level output voltage
CMR
10
-40 °C < T< 125 °C
T = 25 °C
Iio
V
8
122
dB
135
T = 25 °C
30
-40 °C < T< 125 °C
70
T = 25 °C
30
-40 °C < T< 125 °C
70
mV
VOL
Low level output voltage
Isink (Vout = VCC)
Iout
7
-40 °C < T< 125 °C
6
T = 25 °C
5
-40 °C < T< 125 °C
4
8
mA
Isource (Vout = 0 V)
ICC
T = 25 °C
Supply current
(per channel, Vout = VCC/2,
RL > 1 M
T = 25 °C
7
28
40
µA
-40 °C < T< 125 °C
40
AC performance
GBP
Gain bandwidth product
400
Fu
Unity gain frequency
300
m
Phase margin
Gm
Gain margin
kHz
SR
ts
RL = 10 k, CL = 100 pF
(3)
Slew rate
Settling time
To 0.1%, Vin = 1 Vp-p,
RL = 10 k, CL = 100 pF
DocID025994 Rev 1
55
degrees
17
dB
0.17
V/s
50
µs
5/34
34
Electrical characteristics
OA1ZHA, OA2ZHA, OA4ZHA
Table 4. Electrical characteristics (continued)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
en
Equivalent input noise voltage
f = 1 kHz
f = 10 kHz
60
60
nV
-----------Hz
Cs
Channel separation
f = 100 Hz
120
dB
T = 25 °C
50
tinit
Initialization time
-40 °C < T< 125 °C
100
1. See Section 4.5: Input offset voltage drift over temperature. Input offset measurements are performed on x100 gain
configuration. The amplifiers and the gain setting resistors are at the same temperature.
2. Guaranteed by design.
3. Slew rate value is calculated as the average between positive and negative slew rates.
6/34
Unit
DocID025994 Rev 1
s
OA1ZHA, OA2ZHA, OA4ZHA
Electrical characteristics
VCC+ = 3.3 V with VCC- = 0 V, Vicm = VCC/2, T = 25 °C, and RL = 10 k connected to VCC/2
(unless otherwise specified)
Table 5. Electrical characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
1
5
Unit
DC performance
T = 25 °C
Vio
Vio/T
-40 °C < T< 125 °C
Input offset voltage drift(1)
8
-40 °C < T< 125 °C
10
Input bias current
(Vout = VCC/2)
T = 25 °C
Iib
T = 25 °C
Iio
Input offset current
(Vout = VCC/2)
Common mode rejection ratio
20 log (Vicm/Vio)
Vic = 0 V to VCC, Vout = VCC/2
RL > 1 M
T = 25 °C
115
-40 °C < T< 125 °C
115
CMR
V
Input offset voltage
Avd
Large signal voltage gain
Vout = 0.5 V to (Vcc - 0.5 V)
VOH
High level output voltage
60
30
200
nV/°C
(2)
300(2)
-40 °C < T< 125 °C
120
400(2)
pA
600(2)
-40 °C < T< 125 °C
128
dB
T = 25 °C
118
-40 °C < T< 125 °C
110
135
T = 25 °C
30
-40 °C < T< 125 °C
70
T = 25 °C
30
-40 °C < T< 125 °C
70
mV
VOL
Low level output voltage
Isink (Vout = VCC)
15
-40 °C < T< 125 °C
12
T = 25 °C
14
-40 °C < T< 125 °C
10
18
mA
Iout
Isource (Vout = 0 V)
ICC
T = 25 °C
Supply current
(per channel, Vout = VCC/2,
RL > 1 M
T = 25 °C
16
29
40
A
-40 °C < T< 125 °C
40
AC performance
GBP
Gain bandwidth product
400
Fu
Unity gain frequency
300
m
Phase margin
Gm
Gain margin
kHz
SR
ts
Slew rate
RL = 10 k, CL = 100 pF
(3)
Settling time
To 0.1%, Vin = 1 Vp-p,
RL = 10 k, CL = 100 pF
DocID025994 Rev 1
56
degrees
19
dB
0.19
V/s
50
s
7/34
34
Electrical characteristics
OA1ZHA, OA2ZHA, OA4ZHA
Table 5. Electrical characteristics (continued)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
en
Equivalent input noise voltage
f = 1 kHz
f = 10 kHz
40
40
nV
-----------Hz
Cs
Channel separation
f = 100 Hz
120
dB
T = 25 °C
50
tinit
Initialization time
-40 °C < T< 125 °C
100
1. See Section 4.5: Input offset voltage drift over temperature. Input offset measurements are performed on x100 gain
configuration. The amplifiers and the gain setting resistors are at the same temperature.
2. Guaranteed by design.
3. Slew rate value is calculated as the average between positive and negative slew rates.
8/34
Unit
DocID025994 Rev 1
s
OA1ZHA, OA2ZHA, OA4ZHA
Electrical characteristics
VCC+ = 5 V with VCC- = 0 V, Vicm = VCC/2, T = 25 °C, and RL = 10 k connected to VCC/2
(unless otherwise specified)
Table 6. Electrical characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
1
5
Unit
DC performance
T = 25 °C
Vio
Vio/T
-40 °C < T< 125 °C
Input offset voltage drift(1)
8
-40 °C < T< 125 °C
10
T = 25 °C
70
Iib
Input bias current
(Vout = VCC//2)
T = 25 °C
Iio
Input offset current
(Vout = VCC/2)
Common mode rejection ratio
20 log (Vicm/Vio)
Vic = 0 V to VCC/, Vout = VCC//2
RL > 1 M
T = 25 °C
115
-40 °C < T< 125 °C
115
Supply voltage rejection ratio
20 log (VCC//Vio)
VCC/ = 1.8 to 5.5 V,
Vout = VCC//2, RL > 1 M
T = 25 °C
120
-40 °C < T< 125 °C
120
Large signal voltage gain
Vout = 0.5 V to (Vcc - 0.5 V)
T = 25 °C
120
-40 °C < T< 125 °C
110
CMR
SVR
Avd
EMI rejection ratio
(3)
EMIRR
EMIRR =
-20 log (VRFpeak/Vio)
VOH
V
Input offset voltage
30
nV/°C
(2)
200
300(2)
-40 °C < T< 125 °C
140
400(2)
pA
600(2)
-40 °C < T< 125 °C
136
140
dB
135
VRF = 100 mVp, f = 400 MHz
84
VRF = 100 mVp, f = 900 MHz
87
VRF = 100 mVp, f = 1800 MHz
90
VRF = 100 mVp, f = 2400 MHz
91
dB
T = 25 °C
30
-40 °C < T< 125 °C
70
T = 25 °C
30
-40 °C < T< 125 °C
70
High level output voltage
mV
VOL
Low level output voltage
Isink (Vout = VCC/)
15
-40 °C < T< 125 °C
14
T = 25 °C
14
-40 °C < T< 125 °C
12
18
mA
Iout
Isource (Vout = 0 V)
ICC
T = 25 °C
Supply current
(per channel, Vout = VCC//2,
RL > 1 M
T = 25 °C
17
31
40
A
-40 °C < T< 125 °C
DocID025994 Rev 1
40
9/34
34
Electrical characteristics
OA1ZHA, OA2ZHA, OA4ZHA
Table 6. Electrical characteristics (continued)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
AC performance
GBP
400
Gain bandwidth product
Fu
Unity gain frequency
m
Phase margin
Gm
Gain margin
SR
Slew rate(4)
ts
Settling time
en
RL = 10 k, CL = 100 pF
kHz
300
53
degrees
19
dB
0.19
V/s
To 0.1%, Vin = 100 mVp-p,
RL = 10 k, CL = 100 pF
10
s
Equivalent input noise voltage
f = 1 kHz
f = 10 kHz
37
37
nV
-----------Hz
Cs
Channel separation
f = 100 Hz
120
dB
T = 25 °C
50
tinit
Initialization time
-40 °C < T< 125 °C
100
RL = 10 k, CL = 100 pF
1. See Section 4.5: Input offset voltage drift over temperature. Input offset measurements are performed on x100 gain
configuration. The amplifiers and the gain setting resistors are at the same temperature.
2. Guaranteed by design.
3. Tested on SC-70 package
4. Slew rate value is calculated as the average between positive and negative slew rates.
10/34
DocID025994 Rev 1
s
OA1ZHA, OA2ZHA, OA4ZHA
Electrical characteristics
Figure 2. Supply current vs. supply voltage
Figure 3. Input offset voltage distribution
at VCC = 5 V
40
60
35
T=-40°C
T=25°C
40
25
Population
Supply Current (µA)
30
T=125°C
20
15
30
20
10
10
5
VICM=VCC/2
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Supply voltage (V)
0
-5
-3
-2
-1
0
1
2
3
4
5
Input offset voltage (µV)
Figure 5. Input offset voltage distribution
at VCC = 1.8 V
60
60
T=25°C
Vcc=3.3V,
Vicm=1.65V
T=25°C
Vcc=1.8V,
Vicm=0.6V
50
40
Population
40
30
20
10
30
20
10
0
0
-5
-4
-3
-2
-1
0
1
2
3
4
5
-5
Input offset voltage (µV)
-3
-2
-1
0
1
2
3
4
5
Figure 7. Vio temperature co-efficient
distribution (25 °C to 125 °C)
60
50
-4
Input offset voltage (µV)
Figure 6. Vio temperature co-efficient
distribution (-40 °C to 25 °C)
60
T=-40°C to 25°C
Vcc=5V,
Vicm=2.5V
50
T=25°C to 125°C
Vcc=5V,
Vicm=2.5V
40
Population
40
Population
-4
Figure 4. Input offset voltage distribution
at VCC = 3.3 V
50
Population
T=25°C
Vcc=5V,
Vicm=2.5V
50
30
20
10
30
20
10
0
-0.030 -0.025 -0.020 -0.015 -0.010 -0.005 0.000 0.005 0.010 0.015 0.020 0.025 0.030
0
-0.030 -0.025 -0.020 -0.015 -0.010 -0.005 0.000 0.005 0.010 0.015 0.020 0.025 0.030
Input offset voltage drift [µV/°C]
Input offset voltage drift [µV/°C]
DocID025994 Rev 1
11/34
34
Electrical characteristics
OA1ZHA, OA2ZHA, OA4ZHA
Figure 8. Input offset voltage vs. supply voltage Figure 9. Input offset voltage vs. input common
mode at VCC= 1.8 V
5
5
4
4
3
3
T=125°C
2
1
Vio (µV)
1
Vio (µV)
T=125°C
2
0
-1
T=-40°C
-2
T=-40°C
0
-1
T=25°C
T=25°C
-2
-3
-3
Vicm=Vcc/2
-4
-5
2.0
2.3
2.5
2.8
3.0
3.3
3.5
3.8
4.0
4.3
4.5
4.8
-4
Vcc=1.8V
-5
5.0
0.0
0.2
0.4
0.6
Vcc(V)
Figure 10. Input offset voltage vs. input
common mode at VCC = 2.7 V
5
4
4
3
3
3
Vio (µV)
Vio (µV)
1.4
1.6
1.8
T=25°C
0
T=125°C
2
1
-1
T=-40°C
-2
1
T=25°C
0
-1
-2
-3
T=-40°C
-3
-3
-3
Vcc=2.7V
-4
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
Vcc=5.5V
-4
-5
2.8
0.0
0.4
0.8
1.2
1.6
2.0
Vicm (V)
2.8
3.2
3.6
4.0
4.4
4.8
5.2
5.6
Figure 13. VOH vs. supply voltage
20
/LPLWIRU 2$=+$
Output swing (mV from Vcc+)
18
2.4
Vicm (V)
Figure 12. Input offset voltage vs. temperature
,QSXWRIIVHWYROWDJH —9
1.2
3
T=125°C
2
9FF 99LFP 9
15
T=25°C
13
T=125°C
10
8
T=-40°C
5
3
Rl=10k
Vicm=Vcc/2
0
1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4
7HPSHUDWXUH ž&
12/34
1.0
Figure 11. Input offset voltage vs. input
common mode at VCC= 5.5 V
5
-5
0.8
Vicm (V)
Vcc (V)
DocID025994 Rev 1
OA1ZHA, OA2ZHA, OA4ZHA
Electrical characteristics
Figure 14. VOL vs. supply voltage
Figure 15. Output current vs. output voltage
at VCC = 1.8 V
30
20
20
15
13
T=125°C
10
T=25°C
8
T=-40°C
5
Output Current (mA)
Output swing (mV from Vcc-)
18
T=-40°C
T=25°C
10
T=125°C
0
T=25°C
T=125°C
-10
T=-40°C
-20
3
Rl=10k
Vicm=Vcc/2
0
-30
0.0
1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4
Vcc (V)
Figure 16. Output current vs. output voltage
at VCC = 5.5 V
Vcc=1.8V
0.3
0.5
0.8
1.0
1.3
Output Voltage (V)
1.5
1.8
Figure 17. Input bias current vs. common mode
at VCC = 5 V
100
30
T=-40°C
75
T=25°C
20
0
-10
T=25°C
IiBp
25
IiB (pA)
Output Current (mA)
50
T=125°C
10
0
-25
T=125°C
-50
-20
IiBn
Vcc=5V
T=25°C
-75
T=-40°C
Vcc=5.5V
-30
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Output Voltage (V)
-100
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Common Mode Voltage (V)
Figure 18. Input bias current vs. common mode Figure 19. Input bias current vs. temperature at
at VCC = 1.8 V
VCC = 5 V
100
100
75
75
50
50
IiBp
IiBp
25
IiB (pA)
IiB (pA)
25
0
-25
IiBn
-50
-25
-50
Vcc=1.8V
T=25°C
-75
-100
0
0.0
0.3
0.5
0.8
1.0
1.3
1.5
Common Mode Voltage (V)
1.8
IiBn
-75
Vcc=5V
-100
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-25
0
25
50
75
Temperature (°C)
100
125
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Electrical characteristics
OA1ZHA, OA2ZHA, OA4ZHA
Figure 20. Bode diagram at VCC = 1.8 V
Figure 21. Bode diagram at VCC = 2.7 V
250
250
Gain
T=-40°C
0
0
-50
Phase
-100
-40
1
10
-200
-50
Phase
-20
-100
-150
Vcc=2.7V, Vicm=1.35V, G=-100
Rl=10k, Cl=100pF, Vrl=Vcc/2
-40
-250
1000
100
50
0
0
-150
Vcc=1.8V, Vicm=0.9V, G=-100
Rl=10k, Cl=100pF, Vrl=Vcc/2
T=25°C
T=125°C
Gain (dB)
50
150
100
T=25°C
T=125°C
Gain
20
100
Phase (°)
Gain (dB)
T=-40°C
150
20
-20
200
40
200
Phase (°)
40
1
10
-200
-250
1000
100
Frequency (kHz)
Frequency (kHz)
Figure 22. Bode diagram at VCC = 5.5 V
Figure 23. Open loop gain vs. frequency
100
100
250
200
40
Gain
50
0
0
-50
Phase
-20
1
60
60
Gain
40
40
20
20
-100
-150
Vcc=5.5V, Vicm=2.75V, G=-100
Rl=10k, Cl=100pF, Vrl=Vcc/2
-40
80
Phase (°)
100
T=25°C
T=125°C
Gain (dB)
Gain (dB)
20
Phase
80
150
Phase (°)
T=-40°C
10
0
-200
100
-20
0.01
-250
1000
0
Vcc=5V, Vicm=2.5V,
Rl=10k , Cl=100pF
0.1
1
10
100
-20
1000
Frequency (kHz)
Frequency (kHz)
Figure 24. Positive slew rate vs. supply voltage Figure 25. Negative slew rate vs. supply voltage
0.2
T=-40°C
T=25°C
T=125°C
0.1
Rl=10k, Cl=100pF
Vin: from 0.3V to Vcc-0.3V
SR calculated from 10% to 90%
0.0
14/34
0.0
Negative Slew Rate (V/µs)
Positive Slew Rate (V/µs)
0.3
2.0
2.5
3.0
3.5
4.0
4.5
Supply Voltage (V)
5.0
5.5
T=125°C
-0.1
T=-40°C
T=25°C
-0.2
Rl=10k, Cl=100pF
Vin: from Vcc-0.3V to 0.3V
SR calculated from 10% to 90%
-0.3
DocID025994 Rev 1
2.0
2.5
3.0
3.5
4.0
4.5
Supply Voltage (V)
5.0
5.5
OA1ZHA, OA2ZHA, OA4ZHA
Electrical characteristics
Figure 27. Noise vs. frequency
Equivalent Input Voltage Noise (nV/Hz)
Figure 26. 0.1 Hz to 10 Hz noise
55
noise density (nV/(Hz))
50
45
40
35
30
25
20
Vcc = 5.5V
Vicm=Vcc/2
T=25°C
15
Noise 0.1Hz_10Hz
equivalent to 0.2 µVpp
10
100m
1
Frequency (Hz)
180
160
120
100
80
Vcc=1.8V
Vcc=3.3V
60
40
20
Vcc=5.5V
100
1k
Frequency (Hz)
10k
Figure 29. Output overshoot vs. load
capacitance
200
40
180
35
160
30
Vicm=Vcc/2
Vcc=5.5V
Overshoot (%)
140
Vicm=Vcc/2
Tamb=25°C
140
10
Figure 28. Noise vs. frequency and temperature
120
100
80
125°C
25°C
60
25
20
15
10
40
Vcc=5.5V,
100mVpp,
Rl=10k
5
-40°C
20
100
1k
Frequency (Hz)
10k
0
10
100
Load capacitance (pF)
Figure 30. Small signal
1000
Figure 31. Large signal
0.10
2.00
Output Voltage (V)
0.05
Output Voltage (V)
Equivalent Input Voltage Noise (nV/Hz)
200
0.00
Vcc = 5.5V
Rl=10k
Cl=100pF
T=25°C
-0.05
-0.10
-10
0
10
Time (µs)
0.00
Vcc = 5.5V
Rl=10k
Cl=100pF
T=25°C
-2.00
20
-100
30
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0
100
200
300
Time (µs)
400
500
600
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34
Electrical characteristics
OA1ZHA, OA2ZHA, OA4ZHA
Figure 32. Positive overvoltage recovery
at VCC = 1.8 V
Figure 33. Positive overvoltage recovery
at VCC = 5 V
1.0
1.0
0.00
0.00
0.5
Vin
Vin
0.5
0.0
-0.05
-0.05
-0.10
Vout (V)
Vout
-0.5
-1.0
-0.10
-1.5
Vin (V)
Vout
-0.5
Vin (V)
Vout (V)
0.0
-1.0
-2.0
-0.15
Vcc=1.8V, Vicm=0.9V, G=101
Rl=10k, Cl=100pF
-2.0
-50µ
0
50µ
100µ
150µ
200µ
250µ
300µ
350µ
Vcc=5.5V, Vicm=2.75V, G=101
Rl=10k, Cl=100pF
-2.5
-3.0
-0.20
-100µ
-0.15
-100µ
400µ
-0.20
-50µ
0
50µ
100µ
Figure 34. Negative overvoltage recovery
at VCC = 1.8 V
1.0
Vout
-0.5
Vcc=1.8V, Vicm=0.9V, G=101
Rl=10k, Cl=100pF
-1.0
100µ
150µ
0.15
2.5
0.15
0.10
2.0
200µ
250µ
300µ
350µ
Vin
Vout (V)
1.5
0.05
1.0
0.00
0.5
-0.05
-0.10
0.0
-0.10
-0.15
-0.5
-0.20
-1.0
400µ
Vcc=5.5V, Vicm=2.75V, G=101
Rl=10k, Cl=100pF
-0.20
-100µ
-50µ
0
50µ
100µ
150µ
200µ
250µ
300µ
350µ
400µ
Figure 37. Output impedance vs. frequency
-100
2000
1800
+PSRR
-80
1600
Output Impedance ()
PSRR (dB)
-0.15
Time (s)
Figure 36. PSRR vs. frequency
-60
-PSRR
-40
-20
Vcc=5.5V, Vicm=2.75V, G=1
Rl=10k, Cl=100pF, Vripple=100mVpp
100
1000
10000
100000
1400
Vcc=2.7V to 5.5V
Osc level=30mVRMS
G=1
Ta=25C
1200
1000
800
600
400
200
1000000
100
Frequency (Hz)
16/34
0.10
Vout
Time (s)
0
10
400µ
0.20
-0.05
50µ
350µ
3.0
0.00
0
300µ
0.20
0.05
0.0
-50µ
250µ
Figure 35. Negative overvoltage recovery
at VCC = 5 V
Vin (V)
Vout (V)
Vin
-100µ
200µ
Time (s)
Time (s)
0.5
150µ
Vin (V)
-1.5
DocID025994 Rev 1
1k
10k
Frequency (Hz)
100k
1M
OA1ZHA, OA2ZHA, OA4ZHA
Application information
4
Application information
4.1
Operation theory
The OA1ZHA, OA2ZHA and OA4ZHA are high precision CMOS op amp. They achieve a
low offset drift and no 1/f noise thanks to their chopper architecture. Chopper-stabilized
amps constantly correct low-frequency errors across the inputs of the amplifier.
Chopper-stabilized amplifiers can be explained with respect to:
4.1.1

Time domain

Frequency domain
Time domain
The basis of the chopper amplifier is realized in two steps. These steps are synchronized
thanks to a clock running at 400 kHz.
Figure 38. Block diagram in the time domain (step 1)
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Figure 39. Block diagram in the time domain (step 2)
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Figure 38 shows step 1, the first clock cycle, where Vio is amplified in the normal way.
Figure 39 shows step 2, the second clock cycle, where Chop1 and Chop2 swap paths. At
this time, the Vio is amplified in a reverse way as compared to step 1.
At the end of these two steps, the average Vio is close to zero.
The A2(f) amplifier has a small impact on the Vio because the Vio is expressed as the input
offset and is consequently divided by A1(f).
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34
Application information
OA1ZHA, OA2ZHA, OA4ZHA
In the time domain, the offset part of the output signal before filtering is shown in Figure 40.
Figure 40. Vio cancellation principle
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The low pass filter averages the output value resulting in the cancellation of the Vio offset.
The 1/f noise can be considered as an offset in low frequency and it is canceled like the Vio,
thanks to the chopper technique.
4.1.2
Frequency domain
The frequency domain gives a more accurate vision of chopper-stabilized amplifier
architecture.
Figure 41. Block diagram in the frequency domain
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The modulation technique transposes the signal to a higher frequency where there is no 1/f
noise, and demodulate it back after amplification.
1.
According to Figure 41, the input signal Vin is modulated once (Chop1) so all the input
signal is transposed to the high frequency domain.
2.
The amplifier adds its own error (Vio (output offset voltage) + the noise Vn (1/f noise)) to
this modulated signal.
3.
This signal is then demodulated (Chop2), but since the noise and the offset are
modulated only once, they are transposed to the high frequency, leaving the output
signal of the amplifier without any offset and low frequency noise. Consequently, the
input signal is amplified with a very low offset and 1/f noise.
4.
To get rid of the high frequency part of the output signal (which is useless) a low pass
filter is implemented.
To further suppress the remaining ripple down to a desired level, another low pass filter may
be added externally on the output of the OA1ZHA, OA2ZHA and OA4ZHA device.
18/34
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OA1ZHA, OA2ZHA, OA4ZHA
4.2
Application information
Operating voltages
OA1ZHA, OA2ZHA and OA4ZHA CMOS op amp can operate from 1.8 to 5.5 V. The
parameters are fully specified for 1.8 V, 3.3 V, and 5 V power supplies. However, the
parameters are very stable in the full VCC range and several characterization curves show
the OA1ZHA, OA2ZHA and OA4ZHA op amp characteristics at 1.8 V and 5.5 V.
Additionally, the main specifications are guaranteed in extended temperature ranges from 40 to +125 ° C.
4.3
Input pin voltage ranges
OA1ZHA, OA2ZHA and OA4ZHA CMOS op amp can operate from 1.8 to 5.5 V. The
parameters are fully specified for 1.8 V, 3.3 V, an have internal ESD diode protection on the
inputs. These diodes are connected between the input and each supply rail to protect the
input MOSFETs from electrical discharge.
If the input pin voltage exceeds the power supply by 0.5 V, the ESD diodes become
conductive and excessive current can flow through them. Without limitation this over current
can damage the device.
In this case, it is important to limit the current to 10 mA, by adding resistance on the input
pin, as described in Figure 42.
Figure 42. Input current limitation
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4.4
Rail-to-rail input
OA1ZHA, OA2ZHA and OA4ZHA CMOS op amp have a rail-to-rail input, and the input
common mode range is extended from VCC-- 0.1 V to VCC+ + 0.1 V.
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34
Application information
4.5
OA1ZHA, OA2ZHA, OA4ZHA
Input offset voltage drift over temperature
The maximum input voltage drift variation over temperature is defined as the offset variation
related to the offset value measured at 25 °C. The operational amplifier is one of the main
circuits of the signal conditioning chain, and the amplifier input offset is a major contributor
to the chain accuracy. The signal chain accuracy at 25 °C can be compensated during
production at application level. The maximum input voltage drift over temperature enables
the system designer to anticipate the effect of temperature variations.
The maximum input voltage drift over temperature is computed using Equation 1.
Equation 1
V io
V io  T  – V io  25C 
------------ = max ------------------------------------------------T
T – 25C
where T = -40 °C and 125 °C.
The OA1ZHA, OA2ZHA and OA4ZHA CMOS datasheet maximum value is guaranteed by
measurements on a representative sample size ensuring a Cpk (process capability index)
greater than 1.3.
4.6
Rail-to-rail output
The operational amplifier output levels can go close to the rails: to a maximum of 30 mV
above and below the rail when connected to a 10 k resistive load to VCC/2.
4.7
Capacitive load
Driving large capacitive loads can cause stability problems. Increasing the load capacitance
produces gain peaking in the frequency response, with overshoot and ringing in the step
response. It is usually considered that with a gain peaking higher than 2.3 dB an op amp
might become unstable.
Generally, the unity gain configuration is the worst case for stability and the ability to drive
large capacitive loads.
Figure 43 and Figure 44 show the serial resistor that must be added to the output, to make a
system stable. Figure 45 shows the test configuration using an isolation resistor, Riso.
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OA1ZHA, OA2ZHA, OA4ZHA
Application information
Figure 43. Stability criteria with a serial resistor Figure 44. Stability criteria with a serial resistor
at VDD = 5 V
at VDD = 1.8 V
10000
10000
Stable
Serial Resistor (Ohm)
Serial Resistor (Ohm)
Stable
1000
100
Unstable
Vcc=5V, Vicm=2.5V, T=25°C,
Rl=10 k, G=1
10
0.1
1
10
100
Capacitive Load (nF)
1000
100
Unstable
Vcc=1.8V, Vicm=0.9V, T=25°C,
Rl=10 k, G=1
10
1,000
0.1
1
10
100
Capacitive Load (nF)
1,000
Figure 45. Test configuration for Riso
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4.8
PCB layout recommendations
Particular attention must be paid to the layout of the PCB, tracks connected to the amplifier,
load, and power supply. The power and ground traces are critical as they must provide
adequate energy and grounding for all circuits. Good practice is to use short and wide PCB
traces to minimize voltage drops and parasitic inductance.
In addition, to minimize parasitic impedance over the entire surface, a multi-via technique
that connects the bottom and top layer ground planes together in many locations is often
used.
The copper traces that connect the output pins to the load and supply pins should be as
wide as possible to minimize trace resistance.
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34
Application information
4.9
OA1ZHA, OA2ZHA, OA4ZHA
Optimized application recommendation
OA1ZHA, OA2ZHA and OA4ZHA CMOS op amp are based on chopper architecture. As
they are switched devices, it is strongly recommended to place a 0.1 F capacitor as close
as possible to the supply pins.
A good decoupling has several advantages for an application. First, it helps to reduce
electromagnetic interference. Due to the modulation of the chopper, the decoupling
capacitance also helps to reject the small ripple that may appear on the output.
OA1ZHA, OA2ZHA and OA4ZHA CMOS op amp have been optimized for use with 10 k in
the feedback loop. With this, or a higher value of resistance, these devices offer the best
performance.
4.10
EMI rejection ration (EMIRR)
The electromagnetic interference (EMI) rejection ratio, or EMIRR, describes the EMI
immunity of operational amplifiers. An adverse effect that is common to many op amp is a
change in the offset voltage as a result of RF signal rectification.
OA1ZHA, OA2ZHA and OA4ZHA CMOS op amp have been specially designed to minimize
susceptibility to EMIRR and show an extremely good sensitivity. Figure 46 shows the
EMIRR IN+ of the OA1ZHA, OA2ZHA and OA4ZHA measured from 10 MHz up to 2.4 GHz.
Figure 46. EMIRR on IN+ pin
120
EMIRR In+(dB)
100
80
60
40
20
Vcc=5.5V, G=1
Prf=-10dBm
0
10
100
Frequency (MHz)
22/34
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1000
OA1ZHA, OA2ZHA, OA4ZHA
Application information
4.11
Application examples
4.11.1
Oxygen sensor
The electrochemical sensor creates a current proportional to the concentration of the gas
being measured. This current is converted into voltage thanks to R resistance. This voltage
is then amplified by OA1ZHA, OA2ZHA and OA4ZHA CMOS op amp (see Figure 47).
Figure 47. Oxygen sensor principle schematic
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The output voltage is calculated using Equation 2:
Equation 2
R2
V out =  I  R – V io    ------- + 1
R1
As the current delivered by the O2 sensor is extremely low, the impact of the Vio can
become significant with a traditional operational amplifier. The use of the chopper amplifier
of the OA1ZHA, OA2ZHA and OA4ZHA is perfect for this application.
In addition, using OA1ZHA, OA2ZHA and OA4ZHA op amp for the O2 sensor application
ensures that the measurement of O2 concentration is stable even at different temperature
thanks to a very good Vio/T.
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34
Application information
4.11.2
OA1ZHA, OA2ZHA, OA4ZHA
Precision instrumentation amplifier
The instrumentation amplifier uses three op amp. The circuit, shown in Figure 48, exhibits
high input impedance, so that the source impedance of the connected sensor has no impact
on the amplification.
Figure 48. Precision instrumentation amplifier schematic
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The gain is set by tuning the Rg resistor. With R1 = R2 and R3 = R4, the output is given by
Equation 3.
Equation 3
R 4 2R f
V out =  V 2 – V 1   -------   --------- + 1
R2 Rg
The matching of R1, R2 and R3, R4 is important to ensure a good common mode rejection
ratio (CMR).
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OA1ZHA, OA2ZHA, OA4ZHA
4.11.3
Application information
Low-side current sensing
Power management mechanisms are found in most electronic systems. Current sensing is
useful for protecting applications. The low-side current sensing method consists of placing a
sense resistor between the load and the circuit ground. The resulting voltage drop is
amplified using OA1ZHA, OA2ZHA and OA4ZHA CMOS op amp (see Figure 49).
Figure 49. Low-side current sensing schematic
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Vout can be expressed as follows:
Equation 4
R g2  R f2
R g2
R f1
R f1
R f1
V out = R shunt  I  1 – -------------------------   1 + ---------- + I p  -------------------------------   1 + ---------- – I n  R f1 – V io  1 + ----------

 R g2 + R f2  

R g2 + R f2  
R g1
R g1
R g1
Assuming that Rf2 = Rf1 = Rf and Rg2 = Rg1 = Rg, Equation 4 can be simplified as follows:
Equation 5
Rf
Rf
V out = R shunt  I  -------  – V io  1 + ------- + R f  I io
Rg
Rg
The main advantage of using the chopper of the OA1ZHA, OA2ZHA and OA4ZHA, for a
low-side current sensing, is that the errors due to Vio and Iio are extremely low and may be
neglected.
Therefore, for the same accuracy, the shunt resistor can be chosen with a lower value,
resulting in lower power dissipation, lower drop in the ground path, and lower cost.
Particular attention must be paid on the matching and precision of Rg1, Rg2, Rf1, and Rf2, to
maximize the accuracy of the measurement.
DocID025994 Rev 1
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Package information
5
OA1ZHA, OA2ZHA, OA4ZHA
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
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OA1ZHA, OA2ZHA, OA4ZHA
5.1
Package information
SC70-5 package information
Figure 50. SC70-5 package mechanical drawing
SIDE VIEW
DIMENSIONS IN MM
GAUGE PLANE
COPLANAR LEADS
SEATING PLANE
TOP VIEW
Table 7. SC70-5 package mechanical data
Dimensions
Symbol
Millimeters
Min.
Typ.
Inches
Max.
Min.
0.032
A
0.80
1.10
A1
0
0.10
A2
0.80
b
0.90
Typ.
Max.
0.043
0.004
1.00
0.032
0.035
0.15
0.30
0.006
0.012
c
0.10
0.22
0.004
0.009
D
1.80
2.00
2.20
0.071
0.079
0.087
E
1.80
2.10
2.40
0.071
0.083
0.094
E1
1.15
1.25
1.35
0.045
0.049
0.053
e
0.65
0.025
e1
1.30
0.051
L
0.26
<
0°
0.36
0.46
0.010
8°
0°
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0.014
0.039
0.018
8°
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Package information
5.2
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DFN8 2x2 package information
Figure 51. DFN8 2x2 package mechanical drawing
$06B9
Table 8. DFN8 2x2x0.6 mm package mechanical data (pitch 0.5 mm)
Dimensions
Symbol
A
Millimeters
Min.
Typ.
Max.
Min.
Typ.
Max.
0.51
0.55
0.60
0.020
0.022
0.024
A1
0.05
A3
0.002
0.15
0.006
b
0.18
0.25
0.30
0.007
0.010
0.012
D
1.85
2.00
2.15
0.073
0.079
0.085
D2
1.45
1.60
1.70
0.057
0.063
0.067
E
1.85
2.00
2.15
0.073
0.079
0.085
E2
0.75
0.90
1.00
0.030
0.035
0.039
e
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Inches
0.50
0.020
L
0.425
0.017
ddd
0.08
0.003
DocID025994 Rev 1
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Package information
Figure 52. DFN8 2x2 footprint recommendation
PP
PP
PP
PP
PP
PP
$06B9
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Package information
5.3
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MiniSO8 package information
Figure 53. MiniSO8 package mechanical drawing
Table 9. MiniSO8 package mechanical data
Dimensions
Symbol
Millimeters
Min.
Typ.
A
Max.
Min.
Typ.
1.1
A1
0
A2
0.75
b
Max.
0.043
0.15
0
0.95
0.030
0.22
0.40
0.009
0.016
c
0.08
0.23
0.003
0.009
D
2.80
3.00
3.20
0.11
0.118
0.126
E
4.65
4.90
5.15
0.183
0.193
0.203
E1
2.80
3.00
3.10
0.11
0.118
0.122
e
L
0.85
0.65
0.40
0.60
0.006
0.033
0.80
0.016
0.024
0.95
0.037
L2
0.25
0.010
ccc
0°
0.037
0.026
L1
k
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Inches
8°
0.10
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0°
0.031
8°
0.004
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5.4
Package information
QFN16 3x3 package information
Figure 54. QFN16 3x3 package mechanical drawing
*$06&%
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Package information
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Table 10. QFN16 3 x 3 mm package mechanical data (pitch 0.5 mm)
Dimensions
Symbol
Millimeters
Min.
Typ.
Max.
Min.
Typ.
Max.
A
0.80
0.90
1.00
0.031
0.035
0.039
A1
0
0.05
0
A3
0.20
b
0.18
D
2.90
D2
1.50
E
2.90
E2
1.50
e
L
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Inches
3.00
3.00
0.008
0.30
0.007
3.10
0.114
1.80
0.059
3.10
0.114
1.80
0.059
0.50
0.30
0.002
0.012
0.118
0.122
0.071
0.118
0.122
0.071
0.020
0.50
DocID025994 Rev 1
0.012
0.020
OA1ZHA, OA2ZHA, OA4ZHA
6
Revision history
Revision history
Table 11. Document revision history
Date
Revision
04-Mar-2014
1
Changes
Initial release.
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
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