Rajneesh Sharma
1
and Shekhar Verma
2
1
Asst. Prof.,
2
Lecturer,
Electronics Engineering Department, Domain Robotics, Lovely Professional University, Jalandhar (PB) India
Abstract
The choice of the CMOS logic to be used for implementation of a given specification is usually dependent on the optimization and the performance constraints that the finished chip is required to meet. This paper presents a comparative study of CMOS static and dynamic logic. Effect of voltage variation on power and delay of static and dynamic CMOS logic styles studied. The performance of static logic is better than dynamic logic for designing basic logic gates like NAND and NOR. But the dynamic casecode voltage switch logic
(CVSL) achieves better performance. 75% lesser power delay product is achieved than that of static CVSL. However, it observed that dynamic logic performance is better for higher fan in and complex logic circuits.
Index Terms:
Static CMOS circuits, Dynamic CMOS circuits, Logic synthesis, Power delay product.
Introduction
I
P D P avg
→
P a vg
a vg
Average delay
In this paper, static and dynamic 2 input NAND, NOR and dynamic cascode voltage switch logic (DCVSL) NAND are implemented with voltage ranging from 1V to 1.8V.
ELDO simulation results for 180nm technology nodes are given. operating principles Static and Dynamic logics. Section III compares the performance measures. Section IV discusses the results and section V concludes this paper.
Static and Dynamic Logic
Static logic
Static logic circuits allow versatile implementation [3] of logic t is well known that, for theoretical reasons, dynamic logic is less low-power consuming and have high speed than static logic. In particular, dynamic CMOS gates are supposed to be more advantageous than static ones mainly because of a total absence of output glitching and a reduced parasitic capacitance. However, the need of precharging operations introduces some extra dissipated power that does not affect static CMOS logic. In this project we observe experimentally how the choice of the CMOS technology influences the behavior, in terms of power consumption and delay, of digital circuit. An appropriate choice of logic can lead to design high performance, low power VLSI design.
This paper is organized as follows. Section II presents the functions based on static, or steady-state, behavior of simple
CMOS structures. A typical static logic gate generates its approach, however, may require a large number of transistors to implement a function, and may have cause considerable time delay. A basic function of static CMOS logic is explained with example of 2- input NAND gate [3]. There is conducting path between the output node and the ground only if input voltage VA and VB are equal to logic high value. If one of the inputs at low logic value then there is a path between voltage supply and output node is created i.e. except during switching, output connected to either VDD or GND via a low resistance path.
A comparative study of CMOS static and dynamic logic
[1-2] present power consumption which show that the power values for dynamic logic are lower than those for static logic.
However the performance comparison on the basis of power delay product is not present so far. Power delay product (PDP) is a fundamental parameter which is often used for measuring the quality and the performance of CMOS logic. As a physical quantity, the power-delay-product can be interpreted as the average energy required for a gate to switch its output voltage from low to high and from high to low. The amount of energy required to switch the output has been calculated as the product of power and delay. It is mainly dissipated as heat when the NMOS and PMOS transistor conduct current during switching. It is desirable to minimize the power delay product
(PDP) [3]. Figure 1. NAND logic using Static CMOS
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5 th IEEE International Conference on Advanced Computing & Communication Technologies [ICACCT-2011] ISBN 81-87885-03-3
Basic features of Static CMOS logic are [3]
• Very low static power dissipation
• High noise margins (full rail to rail swing)
• Low output impedance, high input impedance
• No steady state path between VDD and GND
• Delay is function of load capacitance and transistor resistance
• Comparable rise and fall times (under the appropriate transistor sizing conditions)
Dynamic logic
In high density, high performance digital implementations where reduction of circuit delay and silicon area is a major objective, dynamic logic circuits offer several significant advantages over static logic circuits. Fig. 2, shows a generalized CMOS dynamic logic circuit [3]. The operation of all dynamic logic gates depend upon on temporary storage of charge in parasitic [6]. This operational property necessitates periodic updating of internal node voltage levels, since stored charge in capacitor cannot retain indefinitely. Consequently, dynamic logic circuits require periodic clock signals in order to control charge refreshing. In the following, a dynamic
CMOS circuit technique which allows us to significantly reduce the number of transistors used to implement any logic function is introduced. The circuit based on first precharging the output node capacitance and subsequently, evaluating the output level according to the applied inputs. The precharge phase is setting the circuit at a predefined initial state while the actual logic response is determined during the evaluation phase [7]. Static CMOS offers good performance but cannot keep up with dynamic logic styles in terms of propagation delay [8]. The shorter delays mostly have to be traded off for increased power dissipation.
CLK
X
N-Logic
Block
VDD
OUT increasing and the delay decreased. Delay is inversely proportional to supply voltage and thereby it increases whereas power directly proportional therefore it decreases.
The optimum power delay product for static NOR and NAND is 1.936×10 -21 and 3.074×10 -22 respectively as seen (as shown in results) is very less as compare to dynamic NOR and
NAND. However Dynamic CVSL results in 6.129×10
-21 power delay product whereas PDP value of static DCVSL result 20.14×10 -21 , so dynamic CVSL perform 75% better than static. In the process technology utilized for this analysis, the attractive point for static logic circuit operation lies near 1.4V and for dynamic logic lies near 1V. Therefore it is concluded that dynamic logic can operate at much lower values of supply voltage.
60
50
40
30
20
10
0
Fig. 3.
1 1.2
1.4
Supply   Voltage   V
DD
(V)
Static
1.6
NOR
Domino   NOR
Variation of PDP with supply voltage
Table 1. Static 2 Input NOR
V
DD
(V) Power ( pW) Average
Delay (pS)
PDP
(x10 -21 Ws)
1.8
1.2 20.260 99.362 2.013
1.4 27.773 69.721 1.936
1.6 37.024 78.766 2.916
1.8 48.299 84.957 4.103
Table 2. Dynamic 2 Input NOR
GND
Fig. 2. Generalized Dynamic Logic circuit.
Results and Discussion
The performance analysis of static and dynamic CMOS circuits is carried out. ELDO simulation results for 180nm technology nodes are given. The effect of voltage variation on power dissipation and delay is studied .The result of static and dynamic 2 input NAND, NOR and dynamic cascode voltage switch logic (DCVSL) NAND are given with voltage ranging from 1V to 1.8V. It is observed from simulation result that with increased voltage, power dissipation of the circuits
V
DD
(V) Power ( pW) Average Delay
(pS)
PDP
(x10 -21 Ws)
1 24.318 858.54 20.848
1.2 34.446 747.5 25.748
1.4 46.990 689.7 32.409
1.6 62.342 655.75 40.88
1.8 80.929 634.65 51.361
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Comparative Analysis of Static and Dynamic CMOS Logic Design
1404
1204
1004
804
604
404
204
35
30
25
20
15
10
5
1
Fig. 5.
1.2
Static     NAND
Dynamic    NAND
4
1 1.2
1.4
1.6
1.8
Supply   Voltage   V
DD
(V)
Fig. 4.
Variation of PDP with supply voltage
Table 3. Power Delay Product (PDP) of Static NAND
V
DD
(V) Power(pW) Average Delay(pS) PDP(x10 -24 Ws)
1 2.919 173.6 506.7
1.2 3.860
1.4 4.904
69.6
69.6
388.9
341.1
1.6 6.047
1.8 7.285
55.2
42.2
333.8
307.4
Table 4.
Power Delay Product (PDP) of Dynamic NAND
V
DD
(V) Power(pW) Average Delay(pS) PDP(x10 -24 Ws)
1 2.206 313.6 691.5
1.2 2.935
1.4 3.752
1.6 4.658
1.8 5.648
277.7
249.2
224.2
42.2
815.0
934.3
1300.1
1173.7
1.4
Static   DCVL    NAND
Dynamic   DCVSL   NAND
Supply Voltage V
DD
(V)
1.6
Variation of PDP with supply voltage
1.8
Table 5. Static 2 input DCVSL NAND
V
DD
(V) Power (pW) Average Delay (nS) PDP(x10 -21 Ws)
1 20.0715 0.295 5.924
1.2 27.9937
1.4 37.655
1.115
0.652
31.212
24.536
1.6 49.3151
1.8 62.9988
0.408
0.360
20.135
22.707
V
DD
Table 5. Dynamic 2 Input DCVSL NAND
(V) Power (pW) Average Delay (pS) PDP (x10 -21 Ws)
1 21.439 290.32 6.224
1.2 30.336 203.05
1.4 41.368 148.179
1.6 54.859 119.04
1.8 71.19 108.08
6.159
6.129
6.302
7.694
Conclusions and Futurework
In this work the impact of voltage variation on delay and power in static and dynamic CMOS circuits has been carried out. It has been observed from the results that the choice of static and dynamic CMOS logic depends upon the requirements of application. For simpler logic implementation, e.g. NAND, NOR etc., we can use static logic because they provide comparable performance with respect to dynamic logic at low cost and less complexity, whereas dynamic logic preferable in complex logic circuit design, e.g. microprocessor, microcontroller etc. The present work is very useful for comparative study of analysis and simulation of static and dynamic CMOS circuits. An appropriate choice of logic along with voltage variation can lead to the design of high performance, low power VLSI chips.
This work shall be further carried out on bigger circuits like XOR, adder etc. so that we can analyze this comparative study more judiciously.
References
[1] E. M. M. Poncino, “Power Consumption of Static and
Dynamic CMOS circuits,” IEEE, 2 nd International
Conference on ASIC, pp. 425-427, October 1996.
[2] R. Chandel, Y. Nataraj, G. Khanna, “Performance
Analysis of Voltage-Scaled Static and Dynamic
CMOS circuits,” Nanoelectronics and Optoelectronics, vol. 3, pp. 171-176, 2008.
[3] S.M. Kang and Y. Leblebici, CMOS Digital integrated
Circuits- Analysis and Design, Tata McGraw Hill,
New Delhi, India, 2003.
[4] M. Kontiala, M. Kuulusa and J. Nurmi, “Comparison of Static Logic Styles for Low-Voltage Digital
Design,” IEEE, The 8 th International conference on
Electronics, Circuits and System, vol. no. 3, pp. 1421 -
1424 September 2001.
[5] M. E. S. Elrabaa, “A New Static Differential CMOS
Logic With Superior Low Power Performance,” in
Proc. Int. Sym. Circuits and Systems, vol. no. 2, pp.
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5 th IEEE International Conference on Advanced Computing & Communication Technologies [ICACCT-2011] ISBN 81-87885-03-3
810-813 December 2003.
[6] S. Perri and P.Corsonello, “Performance comparison between static and dynamic CMOS logic implementations of a pipelined square rooting circuits,” IEEE Proc. Circuits devices system, vol. no.
147, pp. 347-355 December 2000.
[7] T. J. Thorp, G. S. Yee and C.M. Sechen, “Design and
Synthesis of Dynamic Circuits ” IEEE Transactions on
Very Large Scale Integration (VLSI) systems, vol. no.
11, pp. 141-149 , February 2003.
[8] G. Yee and C. Sechen, “Clock-Delayed Domino for
Dynamic Circuit Design”, IEEE Transactions on VLSI
Systems, vol. no. 8, pp. 425-430, Aug. 2000.
[9] N. H. E. Weste and D. Harris, CMOS VLSI Design:
A Circuits and Systems Perspective, 3rd Edition,
Addison-Wesley, 2005.
[10] F. Grassert, and D. Timmermann, “Dynamic Single
Phase Logic with Self-timed Stages for Power
Reduction in Pipeline Circuit Designs,” IEEE
International Symposium on Circuits and Systems
(ISCAS), vol. no. 4, pp. 144-147 May 2001.
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