EECS 141 – S02
Advanced Logic Styles
Digital Integrated Circuits
Logic
© J. Rabaey 2000
Past and Present Lecture
Last Lecture
Sizing of CMOS Logic
Ratioed Logic
Today’s Lecture
Pseudo-NMOS Logic and Variants
Pass-transistor Logic
Digital Integrated Circuits
Logic
© J. Rabaey 2000
1
Ratioed Logic
VDD
• N transistors + Load
Resistive
Load
• VOH = V DD
RL
RPN
• VOL =
RPN + RL
F
In1
In2
In3
• Assymetrical response
PDN
• Static power consumption
• tpL = 0.69 RL CL
VSS
Digital Integrated Circuits
© J. Rabaey 2000
Logic
Pseudo-NMOS
VD D
A
B
C
D
F
CL
VOH = VDD (similar to complementary CMOS)
2
V OL
kp


2
k n ( VDD – V Tn )V OL – ------------ = ------ ( V DD – VTp )
2
2


V
OL
kp
– V ) 1 – 1 – -----= (V
(assuming that V = V
= V
)
DD
T
T
Tn
Tp
k
n
SMALLER AREA & LOAD BUT STATIC POWER DISSIPATION!!!
Digital Integrated Circuits
Logic
© J. Rabaey 2000
2
Pseudo-NMOS NAND Gate
VDD
GND
Digital Integrated Circuits
© J. Rabaey 2000
Logic
Improved Loads
VDD
M1
Enable
M2
M1 >> M2
F
A
B
C
D
CL
Adaptive Load
Digital Integrated Circuits
Logic
© J. Rabaey 2000
3
Improved Loads (2)
VDD
VDD
M1
M2
Out
Out
A
A
B
B
PDN1
PDN2
VSS
VSS
Dual Cascode Voltage Switch Logic (DCVSL)
Digital Integrated Circuits
© J. Rabaey 2000
Logic
Example
Out
Out
B
B
B
A
B
A
XOR-NXOR gate
Digital Integrated Circuits
Logic
© J. Rabaey 2000
4
Pass-Transistor Logic
Inputs
B
Out
Switch
A
Out
Network
B
B
• N transistors
• No static consumption
Digital Integrated Circuits
© J. Rabaey 2000
Logic
NMOS-only switch
C = 2.5 V
C = 2.5V
M2
A = 2.5 V
A = 2.5 V
B
Mn
B
M1
CL
VB does not pull up to 2.5V, but 2.5V -VTN
Threshold voltage loss causes
static power consumption
Digital Integrated Circuits
Logic
© J. Rabaey 2000
5
(1) NMOS Only Logic: Level Restoring
Transistor
VDD
VDD
Level Restorer
Mr
B
M2
X
Mn
A
Out
M1
• Advantage: Full Swing
• Disadvantage: More Complex, Larger Capacitance
• Other approaches: reduced threshold NMOS
Digital Integrated Circuits
© J. Rabaey 2000
Logic
Level Restoring Transistor
5.0
with
5.0
3.0
VB
1.0
-1.00
without
3.0
with
VX
Vout (V)
without
2
t (nsec)
1.0
4
6 -1.00
4
6
t (nsec)
(a) Output node
Digital Integrated Circuits
2
(b) Intermediate node X
Logic
© J. Rabaey 2000
6
Solution 2: Single Transistor Pass Gate with
VT=0
VDD
VDD
0V
2.5V
Out
0V
VDD
2.5V
WATCH OUT FOR LEAKAGE CURRENTS
Digital Integrated Circuits
© J. Rabaey 2000
Logic
Complimentary Pass Transistor Logic
A
A
B
B
Pass-Transistor
F
Network
(a)
A
A
B
B
B
Inverse
Pass-Transistor
Network
B
B
A
F
B
B
A
A
B
F=AB
A
B
F=A+B
F=AB
AND/NAND
Digital Integrated Circuits
A
F=A ⊕ΒÝ
(b)
A
A
B
B
F=A+B
B
OR/NOR
Logic
A
F=A ⊕ΒÝ
EXOR/NEXOR
© J. Rabaey 2000
7
4 Input NAND in CPL
Digital Integrated Circuits
© J. Rabaey 2000
Logic
Solution 3: Transmission Gate
C
A
C
A
B
B
C
C
C = 2.5 V
A = 2.5 V
B
CL
C=0 V
Digital Integrated Circuits
Logic
© J. Rabaey 2000
8
Resistance of Transmission Gate
30
2. 5 V
Resistance, ohms
Rn
20
Rp
2.5 V
Rn
Vout
Rp
0V
10
Rn || Rp
0
0.0
1.0
2.0
Vou t, V
Digital Integrated Circuits
© J. Rabaey 2000
Logic
Pass-Transistor Based Multiplexer
S
S
S
S
VDD
S
A
V DD
M2
F
S
M1
B
S
GND
In1
Digital Integrated Circuits
Logic
In2
© J. Rabaey 2000
9
Transmission Gate XOR
B
B
M2
A
A
F
M1
M3/M4
B
B
Digital Integrated Circuits
© J. Rabaey 2000
Logic
Delay in Transmission Gate Networks
2.5
2.5
V1
In
C
0
2.5
Vi
Vi-1
C
0
2.5
Vn-1
Vi+1
C
0
Vn
C
C
0
(a)
Req
Req
V1
In
Req
Vi
C
Vn-1
Vi+1
C
C
Req
Vn
C
C
(b)
m
Req
Req
Req
Req
Req
Req
In
C
CC
C
C
CC
C
(c)
Digital Integrated Circuits
Logic
© J. Rabaey 2000
10
Delay Optimization
Digital Integrated Circuits
© J. Rabaey 2000
Logic
Transmission Gate Full Adder
P
VDD
A
A
P
P
A
B
VDD
Ci
A
S Sum Generation
Ci
P
B
P
VDD
A
Co Carry Generation
P
Ci
Ci
A
P
Setup
Digital Integrated Circuits
VDD
Ci
Logic
© J. Rabaey 2000
11
Dynamic CMOS
In static circuits at every point in time (except
when switching) the output is connected to
either GND or VDD via a low resistance path.
» fan-in of N requires 2N devices
Dynamic circuits rely on the temporary
storage of signal values on the capacitance of
high impedance nodes.
» requires on N + 2 transistors
Digital Integrated Circuits
© J. Rabaey 2000
Logic
Dynamic Gate
CLK
CLK
Mp
Mp
Out
In1
In2
In3
CLK
CL
Out
A
PDN
C
B
Me
CLK
Me
Two phase operation
Precharge (CLK = 0)
Evaluate (CLK = 1)
Digital Integrated Circuits
Logic
© J. Rabaey 2000
12
Dynamic Gate
CLK
CLK
Mp
off
Mp on
1
Out
!((A&B)|C)
Out
In1
In2
In3
CLK
CL
A
PDN
C
B
Me
CLK
off
Me on
Two phase operation
Precharge (CLK = 0)
Evaluate (CLK = 1)
Digital Integrated Circuits
Logic
© J. Rabaey 2000
Conditions on Output
Once the output of a dynamic gate is
discharged, it cannot be charged again until
the next precharge operation.
Inputs to the gate can make at most one
transition during evaluation.
Output can be in the high impedance state
during and after evaluation (PDN off), state is
stored on CL
Digital Integrated Circuits
Logic
© J. Rabaey 2000
13
Properties of Dynamic Gates
Logic function is implemented by the PDN only
» number of transistors is N + 2 (versus 2N for static complementary
CMOS)
Full swing outputs (VOL = GND and VOH = VDD)
Nonratioed - sizing of the devices is not important
for proper functioning
Faster switching speeds
» reduced load capacitance due to lower input capacitance (Cin)
» reduced load capacitance due to smaller output loading (Cout)
» no Isc, so all the current provided by PDN goes into discharging CL
Digital Integrated Circuits
Logic
© J. Rabaey 2000
Properties of Dynamic Gates,
con’t
Overall power dissipation usually significantly
higher than static CMOS
» no static current path ever exists between VDD and GND
(including Psc)
» no glitching
» higher transition probabilities
» extra load on CLK
PDN starts to work as soon as the input signals
exceed VTn, so set VM, VIH and VIL equal to VTn
» low noise margin (NML)
Needs a precharge clock
Digital Integrated Circuits
Logic
© J. Rabaey 2000
14