Lecture 100 – MOS Capacitor Model and Large Signal Model Dependence (3/24/10)
Page 100-1
LECTURE 100 – MOS CAPACITOR MODEL AND LARGE
SIGNAL MODEL DEPENDENCE
LECTURE ORGANIZATION
Outline
• MOSFET capacitor model
• Dependence of the large signal model on process
• Dependence of the large signal model on voltage
• Dependence of the large signal model on temperature
• Summary
CMOS Analog Circuit Design, 2nd Edition Reference
Pages 79-86
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 100 – MOS Capacitor Model and Large Signal Model Dependence (3/24/10)
Page 100-2
MOSFET CAPACITOR MODEL
Submicron Technology
Physical perspective:
SiO2
Gate
Source
C1
Drain
C2
C3
FOX
FOX
CBS
C4
CBD
Bulk
Fig120-06
MOSFET capacitors consist of:
• Depletion capacitances
• Charge storage or parallel plate capacitances
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 100 – MOS Capacitor Model and Large Signal Model Dependence (3/24/10)
Page 100-3
Deep Submicron Technology
Physical perspective:
MOSFET capacitors consist of:
• Depletion capacitances
• Charge storage or parallel plate capacitances
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 100 – MOS Capacitor Model and Large Signal Model Dependence (3/24/10)
MOSFET Depletion Capacitors
Model:
1.) vBS FC·PB
CJ·AS
CJSW·PS
CBS = +
,
MJ
vBS vBSMJSW
1-
1-
PB PB and
2.) vBS> FC·PB
V BS
CJ·AS CBS =
1+MJ 1-(1+MJ)FC+MJ PB 1-FC +
CJSW·PS
1-FC
1+MJSW
Page 100-4
Polysilicon gate
H
G
C
D
Source
Drain
F
E
A
SiO2
B
Bulk
Fig. 120-07
Drain bottom = ABCD
Drain sidewall = ABFE + BCGF + DCGH + ADHE
CBS
V BS
1-(1+MJSW)FC+MJSW PB vBS ≥ FC·PB
vBS ≤ FC·PB
where
AS = area of the source
PS = perimeter of the source
CJSW = zero bias, bulk source sidewall capacitance
MJSW = bulk-source sidewall grading coefficient
For the bulk-drain depletion capacitance replace "S" by "D" in the above.
CMOS Analog Circuit Design
PB
vBS
FC·PB
Fig. 120-08
© P.E. Allen - 2010
Lecture 100 – MOS Capacitor Model and Large Signal Model Dependence (3/24/10)
Page 100-5
SM Charge Storage (Parallel Plate) MOSFET Capacitances - C1, C2, C3 and C4
Mask L
LD
Actual
L (Leff)
Oxide encroachment
Mask
W
Actual
W (Weff)
Overlap capacitances:
C1 = C3 = LD·Weff·Cox = CGSO or CGDO
(LD 0.015 μm for LDD structures)
Gate
Channel capacitances:
C2 = gate-to-channel = CoxW eff·(L-2LD) =
CoxW eff·Leff
C4 = voltage dependent channelbulk/substrate capacitance
Drain-gate overlap
capacitance CGD (C3)
Source-gate overlap
capacitance CGS (C1)
Gate
FOX
Source
Gate-Channel
Capacitance (C2)
Bulk
FOX
Drain
Channel-Bulk
Capacitance (C4)
Fig. 120-09
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 100 – MOS Capacitor Model and Large Signal Model Dependence (3/24/10)
Page 100-6
SM Charge Storage (Parallel Plate) MOSFET Capacitances - C5
View looking down the channel from source to drain
Overlap
Overlap
FOX C5
Gate
Source/Drain
C5 FOX
Bulk
Fig120-10
C5 = CGBO
Capacitance values based on an oxide thickness of 140 Å or Cox=24.7 10-4 F/m2:
Type
CGSO
CGDO
CGBO
CJ
CJSW
MJ
MJSW
CMOS Analog Circuit Design
P-Channel
220 10-12
220 10-12
700 10-12
560 10-6
350 10-12
0.5
0.35
N-Channel
220 10-12
220 10-12
700 10-12
770 10-6
380 10-12
0.5
0.38
Units
F/m
F/m
F/m
F/m2
F/m
© P.E. Allen - 2010
Lecture 100 – MOS Capacitor Model and Large Signal Model Dependence (3/24/10)
Page 100-7
DSM Charge Storage MOSFET Capacitances - C1, C2, C3, C4 and C5
C2
C1
C3
C4
Shallow
Trench
Isolation
C5
Shallow
Trench
Isolation
Shallow
Trench
Isolation
C5
Shallow
Trench
Isolation
Channel
View Down Channel
Side View
070330-04
C1 and C3 are overlap capacitors due to lateral diffusion of the source and drain
C2 is the gate to channel capacitance
C4 is the depletion capacitance between the channel and the bulk
C5 is the fringing capacitance between the gate and the bulk around the edges of the
channel
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 100 – MOS Capacitor Model and Large Signal Model Dependence (3/24/10)
Page 100-8
MOSFET Capacitors for the Cutoff Region
Side view:
Drain-gate overlap
capacitance CGD (C3)
Source-gate overlap
capacitance CGS (C1)
Source-gate overlap
capacitance CGS (C1)
Drain-gate overlap
capacitance CGD (C3)
Gate
FOX
Source
Gate-Channel
Capacitance (C2)
Bulk
FOX
Drain
Channel-Bulk
Capacitance (C4)
Gate-Channel
Shallow Capacitance (C )
2
Trench
Isolation
Channel-Bulk
Capacitance (C4)
Shallow
Trench
Isolation
070330-05
As the gate-source voltage varies from 0 to VT, the channel-bulk capacitor varies from a
very large capacitor (because of a very small depletion region) to a capacitor much
smaller than C2.
Capacitors in Cutoff:
CGS
C1 = Cox·LD·W = CGSO·W
CGD
CGB
C3 = Cox·LD·W = CGDO·W
CBD
C2 varies from Cox·L·W to 2C5
CBD = (CJ·AD)/[1 – (vBD/PB)]MJ + (CJSW·PD)/[1 – (vBD/PB)]MJSW
CBS
CBS = (CJ·AS)/[1 – (vBS/PB)]MJ + (CJSW·PS)/[1 – (vBS/PB)]MJSW
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 100 – MOS Capacitor Model and Large Signal Model Dependence (3/24/10)
Page 100-9
MOSFET Capacitors for the Saturation Region
Side view:
Drain-gate overlap
capacitance CGD (C3)
Source-gate overlap
capacitance CGS (C1)
Source-gate overlap
capacitance CGS (C1)
Drain-gate overlap
capacitance CGD (C3)
Gate
FOX
Source
Gate-Channel
Capacitance (C2) Bulk
Drain
FOX
Shallow
Trench
Isolation
Gate-Channel
Shallow Capacitance (C )
2
Trench
Isolation
070330-06
In the saturation region, C4, becomes small and is not shown above.
Capacitors in Saturation:
CGS
CGD
CGB
CBD
CBS
C1 = Cox·LD·W + (2/3)Cox·L·W = [CGSO + (2/3)Cox·L]W
C3 = Cox·LD·W = CGDO·W
2C5 = 2·CGBO·W
CBD = (CJ·AD)/[1 – (vBD/PB)]MJ + (CJSW·PD)/[1 – (vBD/PB)]MJSW
CBS = (CJ·AS)/[1 – (vBS/PB)]MJ + (CJSW·PS)/[1 – (vBS/PB)]MJSW
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 100 – MOS Capacitor Model and Large Signal Model Dependence (3/24/10)
Page 100-10
MOSFET Capacitors for the Active Region
Side view:
Drain-gate overlap
capacitance CGD (C3)
Source-gate overlap
capacitance CGS (C1)
Source-gate overlap
capacitance CGS (C1)
Drain-gate overlap
capacitance CGD (C3)
Gate
FOX
Source
Gate-Channel
Capacitance (C2)
Drain
Bulk
FOX
Gate-Channel
Shallow Capacitance (C )
2
Trench
Isolation
Shallow
Trench
Isolation
070330-07
In the saturation region, C4, becomes small and is not shown above.
Capacitors in Active:
CGS
CGD
CGB
CBD
CBS
C1 = Cox·LD·W + (1/2)Cox·L·W = [CGSO + (1/2)Cox·L]W
C3 = Cox·LD·W + (1/2)Cox·L·W = [CGSO + (1/2)Cox·L]W
2C5 = 2·CGBO·W
CBD = (CJ·AD)/[1 – (vBD/PB)]MJ + (CJSW·PD)/[1 – (vBD/PB)]MJSW
CBS = (CJ·AS)/[1 – (vBS/PB)]MJ + (CJSW·PS)/[1 – (vBS/PB)]MJSW
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 100 – MOS Capacitor Model and Large Signal Model Dependence (3/24/10)
Page 100-11
Illustration of CGD, CGS and CGB
Comments on the variation of CBG in the cutoff region:
1
CBG = 1
Capacitance
1 + 2C5
+
C4 Large
C2 C4
C2 + 2C5
1.) For vGS 0, CGB C2 + 2C5
(C4 is large because of the thin
inversion layer in weak inversion
where VGS is slightly less than VT))
CGS
C1+ 0.67C2
C1+ 0.5C2
2.) For 0 < vGS VT, CGB 2C5
(C4 is small because of the thicker
inversion layer in strong inversion)
C1, C3
2C5
0
CGS, CGD
vDS = constant
vBS = 0
C4 Small
CGS, CGD
CGD
CGB
Off
Saturation
VT
CMOS Analog Circuit Design
vGS
NonSaturation
vDS +VT
Fig120-12
© P.E. Allen - 2010
Lecture 100 – MOS Capacitor Model and Large Signal Model Dependence (3/24/10)
Page 100-12
DEPENDENCE OF THE LARGE SIGNAL MODEL ON PROCESS
How Does Technology Vary?
1.) Thickness variations in layers (dielectrics and metal)
tox(max)
tox(min)
060225-01
2.) Doping variations
n+
n-well
p+
p+
Diffusion Differences
060225-02
3.) Process biases –
differences between
the drawn and actual dimensions due to process (etching, lateral diffusion, etc.)
Drawn Dimension
Actual Dimension
060225-03
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 100 – MOS Capacitor Model and Large Signal Model Dependence (3/24/10)
Page 100-13
Large Signal Model Dependence on Process Variations
1.) Threshold voltage
V T = VT0 + |-2F+vSB|- |-2F|
where
2qsiNA
Qb0 QSS
V T0 = MS - 2F - C - Cox
and
= Cox
ox
If VBS = 0, then VT is dependent on doping and oxide thickness because
kT NSUB
1
F = q ln
ni and
Cox tox
(Recall that the threshold is also determined by the threshold implant during processing)
2.) Transconductance parameter
1
K’ = μoCox tox
For short channel devices, the mobility is degraded as given by
μo
2x10-9m/V
and
μeff = 1+(VGS-VT)
tox
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 100 – MOS Capacitor Model and Large Signal Model Dependence (3/24/10)
Page 100-14
Process Variation “Corners”
For strong inversion operation, the primary influence is the oxide thickness, tox. We see
that K’ will tend to increase with decreasing oxide thickness whereas VT tends to
decrease.
PMOS
If the “speed” of a transistor is increased
Speed
by increasing K’ and decreasing VT, then
Large Kʼ
the variation of technology can be
Fast
Small VT
expressed on a two-dimensional graph
PMOS
Acceptable
Technology
resulting in a rectangular area of
Parameters
“acceptable” process limitation.
Slow
PMOS
Three corner versus five corner models
CMOS Analog Circuit Design
060118-10
Small Kʼ
Large VT
Slow
NMOS
Fast
NMOS
NMOS Speed
© P.E. Allen - 2010
Lecture 100 – MOS Capacitor Model and Large Signal Model Dependence (3/24/10)
Page 100-15
DEPENDENCE OF THE LARGE SIGNAL MODEL ON VOLTAGE
What is Voltage Variation?
Voltage variation is the influence of power supply voltage on the component.
(There is also power supply influence on the circuit called power supply rejection ratio,
PSRR. We will deal with this much later.)
Power supply variation comes from:
1.) Influence of depletion region widths on components.
2.) Nonlinearity
3.) Breakdown voltage
Note: Because the large-signal model for the MOSFET includes all the influences of
voltage on the transistor, we will focus on passive components except for breakdown.
CMOS Analog Circuit Design
Lecture 100 – MOS Capacitor Model and Large Signal Model Dependence (3/24/10)
© P.E. Allen - 2010
Page 100-16
Models for Voltage Dependence of a Component
1.) ith-order Voltage Coefficients
In general a variable y = f(v) which is a function of voltage, v, can be expressed as a
Taylor series,
y(v = V0) y(V0) + a1(v- V0) + a2(v- V0)2+ a3(v- V0)3 + ···
where the coefficients, ai, are defined as,
df(v) |
1 d2f(v) |
a1 = dv v=V0 , a2 = 2 dv2 v=V0 , ….
The coefficients, ai, are called the first-order, second-order, …. voltage coefficients.
2.) Fractional Voltage Coefficient or Voltage Coefficient
Generally, only the first-order coefficients are of interest.
In the characterization of temperature dependence, it is common practice to use a term
called fractional voltage coefficient, VCF, which is defined as,
1
df(v) |
VCF(v=V0) = f(v=V0) dv v=V0 parts per million/V (ppm/V)
or more simply,
1 df(v)
VCF = f(v) dv parts per million/V (ppm/V)
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 100 – MOS Capacitor Model and Large Signal Model Dependence (3/24/10)
Page 100-17
Influence of Voltage on a Diffused Resistor – Depletion Region
Influence of the depletion region on the p+ resistor:
Thickness of
p+ p+ Resistor
FOX
FOX
p+
STI
n- well
Thickness of
p+ Resistor
p+
Depletion region
STI
n-well
p- substrate
060305-01
Older LOCOS Technology
As the voltage at the terminals of the resistor become smaller than the n-well potential,
the depletion region will widen causing the thickness of the resistor to decrease.
L
R = t W VR
where VR is the reverse bias voltage from the resistor to the well.
This effect is worse for well resistors because the doping concentration of the resistor is
smaller.
Voltage coefficient for diffused resistors 200-800 ppm/V
Voltage coefficient for well resistors 8000 ppm/V
CMOS Analog Circuit Design
Lecture 100 – MOS Capacitor Model and Large Signal Model Dependence (3/24/10)
© P.E. Allen - 2010
Page 100-18
Voltage Coefficient of Polysilicon Resistors
Why should polysilicon resistors be sensitive to voltage?
There is a small depletion region between the polysilicon and its surrounding material
that has a very small dependence on the voltage between the polysilicon and the
surrounding material.
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 100 – MOS Capacitor Model and Large Signal Model Dependence (3/24/10)
Page 100-19
Voltage Nonlinearity and Breakdown Voltage
Conductivity modulation:
As the current in a resistor increases, the conductivity becomes modulated and the
resistance increases.
i
i = Rv
Example of a n-well resistor:
0.1A
Conductivity
modulation
v
060311-01
As the reverse bias voltage across a pn junction
becomes large, at some point, called the breakdown
voltage, the current will rapidly increase. Both
transistors, diodes and depletion capacitors experience
this breakdown.
Model for current multiplication factor:
1
M=
vR n
1+BV
CMOS Analog Circuit Design
Lecture 100 – MOS Capacitor Model and Large Signal Model Dependence (3/24/10)
iR
Breakdown
voltage
060311-02
BV
vR
© P.E. Allen - 2010
Page 100-20
DEPENDENCE OF THE LARGE SIGNAL MODEL ON TEMPERATURE
Temperature Dependence of the MOSFET
Transconductance parameter:
K’(T) = K’(T0) (T/T0)-1.5
(Exponent becomes +1.5 below 77°K)
Threshold Voltage:
V T(T) = VT(T0) + (T-T0) + ···
Typically NMOS = -2mV/°C to –3mV/°C from 200°K to 400°K (PMOS has a + sign)
Example
Find the value of ID for a NMOS transistor at 27°C and 100°C if VGS = 2V and W/L =
5μm/1μm if K’(T0) = 110μA/V2 and VT(T0) = 0.7V and T0 = 27°C and NMOS = -2mV/°C.
Solution
At room temperature, the value of drain current is,
110μA/V2·5μm
ID(27°C) =
(2-0.7)2 = 465μA
2·1μm
At T = 100°C (373°K), K’(100°C)=K’(27°C) (373/300)-1.5=110μA/V2·0.72=79.3μA/V2
and
V T(100°C) = 0.7 – (.002)(73°C) = 0.554V
79.3μA/V2·5μm
ID(100°C) =
(2-0.554)2 = 415μA
2·1μm
CMOS Analog Circuit Design
(Repeat with VGS = 2.0855V)
© P.E. Allen - 2010
Lecture 100 – MOS Capacitor Model and Large Signal Model Dependence (3/24/10)
Page 100-21
Zero Temperature Coefficient (ZTC) Point for MOSFETs
For a given value of gate-source voltage, the drain current of the MOSFET will be
independent of temperature. Consider the following circuit:
Assume that the transistor is saturated and that:
ID
T -1.5
μ = μoTo
and V T(T) = VT(To) + (T-To)
VGS
= -0.0023V/°C and To = 27°C
where
Fig. 4.5-12
μoCoxW T -1.5
2
ID(T) = 2L T [V GS – VT0 - (T-To)]
o
dID -1.5μoCox T -2.5
T -1.5
2
=
[V
-V
(T-T
)]
+
μ
C
[V GS-V T0-(T-To)] = 0
GS T0
o
o oxTo
dT
2To
To
V GS – VT0 - (T-To) =
-4T
3
VGS(ZTC)=VT0-To- 3 Let K’ = 10μA/V2, W/L = 5 and VT0 = 0.71V.
At T=27°C(300°K), VGS(ZTC)=0.71-(-0.0023)(300°K)-(0.333)(-0.0023)(300°K)=1.63V
At T = 27°C (300°K), ID = (10μA/V2)(5/2)(1.63-0.71)2 = 21.2μA
At T=200°C(473°K),VGS(ZTC)=0.71-(-0.0023)(300°K)-(0.333)(-0.0023)(473°K)=1.76V
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 100 – MOS Capacitor Model and Large Signal Model Dependence (3/24/10)
Page 100-22
Experimental Verification of the ZTC Point
The data below is for a 5μm n-channel MOSFET with W/L=50μm/10μm,
NA=1016 cm-3, tox = 650Å, uoCox = 10μA/V2, and VT0 = 0.71V.
25°C
100°C
150°C
200°C
250°C
100
VDS = 6V
80
ID (A)
275°C
60
300°C
40
150°C
275°C 250°C 200°C
Zero TC Point
20
25°C
100°C
0
0
0.6
1.2
1.8
VGS (V)
2.4
3
0600613-01
A similar result holds for the p-channel MOSFET.
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 100 – MOS Capacitor Model and Large Signal Model Dependence (3/24/10)
Page 100-23
ZTC Point for UDSM Technology
50 nm CMOS:
1.0
25°C
50°C
100°C
140°C
0.5
Normalized Drain Current
Normalized Drain Current
0.6
0.4
Zero Temperature
Coefficient
0.3
0.2
0.8
50°C
NMOS
L=500nm
0.7
0.6
100°C
140°C
0.5
0.4
Zero Temperature
Coefficient
0.3
0.2
0.1
0
25°C
0.9
NMOS
L=50nm
0.7
0.1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Gate Source Voltage
071108-01
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Gate Source Voltage
071108-02
Note that the ZTC point is close to VDD.
PMOS will have similar characteristics.
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 100 – MOS Capacitor Model and Large Signal Model Dependence (3/24/10)
Bulk-Drain (Bulk-Source) Leakage Currents
Cross-section of a NMOS in a p-well:
V GS>VT:
B
Page 100-24
;;;
;;;;;;;
VG > VT
VD > VDS(sat)
S
Depletion
Region
Polysilicon
p+
;;;;;;;
n+
n+
p-well
n- substrate
V GS<VT:
;;;
;;;
;;
;;; ;;
VG <VT
B
S
Polysilicon
p+
Fig.3.6-5
VD > VDS(sat)
n+
Depletion
Region
n+
p-well
n- substrate
Fig.3.6-6
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 100 – MOS Capacitor Model and Large Signal Model Dependence (3/24/10)
Page 100-25
Temperature Modeling of the PN Junction
PN Junctions (Reverse-biased only):
V Dnnpo qAD n2i
Dppno
Go
3
iD Is = qA Lp + Ln L N = KT exp V t Differentiating with respect to temperature gives,
V V dIs 3KT3
qKT3V Go
3Is Is V Go
Go
Go
+
=
exp
exp
2
Vt Vt = T + T Vt
dT
T
KT
dIs
3
1 V Go
TCF = IsdT = T + T V t
Example
Assume that the temperature is 300° (room temperature) and calculate the reverse
diode current change and the TCF for a 5° increase.
Solution
The TCF can be calculated from the above expression as TCF = 0.01 + 0.155 = 0.165.
Since the TCF is change per degree, the reverse current will increase by a factor of 1.165
for every degree (or °C) change in temperature. Multiplying by 1.165 five times gives
an increase of approximately 2. Thus, the reverse saturation current approximately
doubles for every 5°C temperature increase.
Experimentally, the reverse current doubles for every 8°C increase in temperature
because the reverse current is in part leakage current.
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 100 – MOS Capacitor Model and Large Signal Model Dependence (3/24/10)
Page 100-26
Experimental Verification of the PN Junction Temperature Dependence
Theory:
V G(T)
Is(T) T 3 exp kT CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 100 – MOS Capacitor Model and Large Signal Model Dependence (3/24/10)
Page 100-27
Temperature Modeling of the PN Junction – Continued
PN Junctions (Forward biased – vD constant):
v D
iD Is exp V t Differentiating this expression with respect to temperature and assuming that the diode
voltage is a constant (vD = VD) gives
diD iD dIs 1 V D
dT = Is dT - T V t iD
The fractional temperature coefficient for iD is
1 diD 1 dIs V D 3 V Go-VD
iD dT = Is dT - TVt = T + TVt If VD is assumed to be 0.6 volts, then the fractional temperature coefficient is equal to
0.01+(0.155-0.077) = 0.0879. The forward diode current will approx. double for a 10°C.
PN Junctions (Forward biased – iD constant):
V D = Vt ln(ID/Is)
Differentiating with respect to temperature gives
V
dvD vD
vD 3Vt V Go
Go-vD 3V t
1 dIs
=
V
=
=
t Is dT dT
T
T T
T
T - T
Assuming that vD = VD = 0.6 V the temperature dependence of the forward diode voltage
at room temperature is approximately -2.3 mV/°C.
CMOS Analog Circuit Design
Lecture 100 – MOS Capacitor Model and Large Signal Model Dependence (3/24/10)
© P.E. Allen - 2010
Page 100-28
Resistor Dependence on Temperature
Diffused Resistors:
The temperature dependence of resistors depends mostly on the doping level of diffused
and implanted resistors. As the doping level or sheet resistance increases from 100 /
to 400 /, the temperature coefficient varies from about +1000 ppm/°C to +4000
ppm/°C. Diffused and implanted resistors have good thermal conduction to the substrate
or well.
Polysilicon Resistors:
Typically has a sheet resistance of 20 / to 80 / and has poor thermal conduction
because it is electrically isolated by oxide layers.
Metal:
Metal is often used for resistors and has a positive temperature coefficient.
Temperature Coefficients of Resistors:
n-well = 4000 ppm/°C
Diffusion = +1500 ppm/°C
Polysilicon = 500-2000 ppm/°C
Ion implanted = +400 ppm/°C
Metal = +3800 ppm/°C (aluminum)
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 100 – MOS Capacitor Model and Large Signal Model Dependence (3/24/10)
Page 100-29
SUMMARY
• The large signal capacitance model includes depletion and parallel plate capacitors
• The depletion capacitors CBD and CBS vary with their reverse bias voltage
• The capacitors CGD, CGS, and CGB have different values for the regions of cutoff, active
and saturated
• The large signal model varies with process primarily through μo and tox
• Voltage dependence of resistors and capacitors is primarily due to the influence of
depletion regions
• The temperature dependent large signal model of the MOSFET yields a gate-source
voltage where the derivative of drain current with respect to temperature is zero
• Other MOSFET temperature dependence comes from the leakage currents across
reverse biased pn junctions
CMOS Analog Circuit Design
© P.E. Allen - 2010