IDT74ALVC162268
3.3V CMOS 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
EXTENDED COMMERCIAL TEMPERATURE RANGE
3.3V CMOS 12-BIT TO
TO 24-BIT REGISTERED
BUS EXCHANGER WITH
3-STATE OUTPUTS
DESCRIPTION:
FEATURES:
–
–
–
–
–
–
–
–
–
–
Drive
–
–
IDT74ALVC162268
ADVANCE
INFORMATION
This registered bus exchanger is built using advanced dual metal
CMOS technology. This device is used for applications in which data
must be transferred from a narrow high-speed bus to a wide, lowerfrequency bus.
The ALVC162268 device provides synchronous data exchange
between the two ports. Data is stored in the internal registers on the lowto-high transition of the clock (CLK) input when the appropriate clockenable (CLKEN) inputs are low. The select (SEL) line is synchronous
with CLK and selects 1B or 2B input data for the A outputs. For data
transfer in the A-to-B direction, a two-stage pipeline is provided in the Ato-1B path, with a single storage register in the A-to-2B path. Proper
control of these inputs allows two sequential 12-bit words to be presented
synchronously as a 24-bit word on the B-port. Data flow is controlled by
the active-low output enables (OEA and OEB). These control terminals
are registered to synchronize the bus-direction changes with CLK.
The ALVC162268 has series resistors in the device output structure
of the “B” port which will significantly reduce line noise when used with
light loads. This driver has been designed to drive ±12mA at the
designated threshold levels. The “A” port has a ±24mA driver.
0.5 MICRON CMOS Technology
Typical tSK(0) (Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
0.635mm pitch SSOP, 0.50mm pitch TSSOP,
and 0.40mm pitch TVSOP packages
Extended commercial range of – 40°C to + 85°C
VCC = 3.3V ± 0.3V, Normal Range
VCC = 2.7V to 3.6V, Extended Range
VCC = 2.5V ± 0.2V
CMOS power levels (0.4µ W typ. static)
Rail-to-Rail output swing for increased noise margin
Features for ALVC162268:
High Output Drivers: ±24mA (A port)
Balanced Output Drivers: ±12mA (B port)
APPLICATIONS:
• 3.3V High Speed Systems
• 3.3V and lower voltage computing systems
Functional Block Diagram
29
CLK
2
CLKEN1B
27
CLKEN2B
30
CLKE NA 1
55
CLKE NA 2
C1
56
O EB
1D
C1
28
SEL
1D
1
O EA
CE
C1
1D
1D
23
1B 1
C1
A1
CE
C1
0
8
1D
1
CE
C1
CE
C1
1D
1D
6
2B 1
CE
C1
1D
1 of 12 Channels
EXTENDED COMMERCIAL TEMPERATURE RANGE
APRIL 1999
1
c
1999 Integrated Device Technology, Inc.
DSC-4550/-
IDT74ALVC162268
3.3V CMOS 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
EXTENDED COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATING
PIN CONFIGURATION
Symbol
VTERM(2)
OEA
1
56
OEB
CLKEN1B
2
55
CLKENA2
2B 3
3
54
2B 4
GND
4
53
GND
(1)
Max.
– 0.5 to + 4.6
Unit
V
– 0.5 to
VCC + 0.5
– 65 to + 150
V
TSTG
Description
Terminal Voltage
with Respect to GND
Terminal Voltage
with Respect to GND
Storage Temperature
°C
IOUT
DC Output Current
– 50 to + 50
mA
IIK
± 50
mA
– 50
mA
±100
mA
VTERM(3)
2B 2
5
52
2B 5
2B 1
6
51
2B 6
VCC
7
50
VCC
IOK
Continuous Clamp Current,
VI < 0 or VI > VCC
Continuous Clamp Current, VO < 0
A1
8
49
2B 7
A2
9
48
2B 8
ICC
ISS
Continuous Current through
each VCC or GND
A3
10
47
2B 9
GND
11
46
GND
A4
12
A5
13
A6
14
45
SO56-1
SO56-2 44
SO56-3
43
2B12
A7
15
42
1B12
A8
16
41
1B11
A9
17
40
1B10
GND
18
39
GND
A10
19
38
1B 9
A11
20
37
1B 8
A12
21
36
1B 7
VCC
22
35
VCC
1B 1
23
34
1B 6
1B 2
24
33
1B 5
GND
25
32
GND
1B 3
26
31
1B 4
CLKEN2B
27
30
CLKENA1
SEL
28
29
CLK
NEW16link
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. VCC terminals.
3. All terminals except VCC.
2B10
2B11
FUNCTION TABLES (1)
OUTPUT ENABLE
Inputs
CLK
↑
↑
↑
↑
Outputs
OEA
H
H
L
L
OEB
H
L
H
L
Ax
Z
Z
Active
Active
1Bx, 2Bx
Z
Active
Z
Active
A-TO-B STORAGE (OEB = L AND OEA = H)
Inputs
SSOP/
TSSOP/ TVSOP
TOP VIEW
Outputs
CLKENA1
CLKENA2
CLK
Ax
1Bx
2Bx
H
H
X
X
1B0(2)
2B0(2)
L
L
X
X
L
L
L
L
↑
↑
↑
↑
L
H
L
H
L(3)
H(3)
X
X
L
H
L
H
CAPACITANCE (TA = +25oC, f = 1.0MHz)
Symbol
CIN
Parameter(1)
Input Capacitance
Conditions
VIN = 0V
Typ.
5
Max.
7
Unit
pF
COUT
Output
Capacitance
I/O Port
Capacitance
VOUT = 0V
7
9
pF
VIN = 0V
7
9
pF
CI/O
NEW16link
NOTE:
1. As applicable to the device type.
c 1998 Integrated Device Technology, Inc.
2
DSC-123456
IDT74ALVC162268
3.3V CMOS 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
EXTENDED COMMERCIAL TEMPERATURE RANGE
FUNCTION TABLES (continued)
B-TO-A STORAGE (OEA = L AND OEB = H)
Inputs
Output
CLKEN1B
CLKEN2B
CLK
SEL
1Bx
2Bx
Ax
H
X
X
H
X
X
A0(2)
X
H
X
L
X
X
A0(2)
L
L
X
X
X
X
L
L
↑
↑
↑
↑
H
H
L
L
L
H
X
X
X
X
L
H
L
H
L
H
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High Impedance
↑ = LOW-to-HIGH Transition
2. Output level before the indicated steady-state input conditions were established.
3. Two CLK edges are needed to propagate data.
PIN DESCRIPTION
Pin Names
I/O
Description
Ax(1:12)
I/O
Bidirectional Data Port A. Usually connected to the CPU's Address/Data bus.
1Bx(1:12)
I/O
Bidirectional Data Port 1B. Usually connected to the even path or even bank of memory.
2Bx(1:12)
I/O
Bidirectional Data Port 2B. Usually connected to the odd path or odd bank of memory.
CLK
I
Clock Input
CLKENA1
I
Clock Enable Input for the A-1B Register. If CLKENA1 is LOW during the rising edge of CLK, data will be
clocked into register A-1B (Active LOW).
CLKENA2
I
CLKEN1B
I
Clock Enable Input for the A-2B Register. If CLKENA2 is LOW during the rising edge of CLK, data will be
clocked into register A-2B (Active LOW).
Clock Enable Input for the 1B-A Register. If CLKEN1B is LOW during the rising edge of CLK, data will be
clocked into register 1B-A (Active LOW).
CLKEN2B
I
Clock Enable Input for the 2B-A Register. If CLKEN2B is LOW during the rising edge of CLK, data will be
clocked into register 2B-A (Active LOW).
SEL
I
1B or 2B Port Selection. When HIGH during the rising edge of CLK, SEL enables data transfer from 1B Port
to A Port. When LOW during the rising edge of CLK, SEL enables data transfer from 2B Port to A Port (Active LOW).
OEA
I
Synchronous Output Enable for A Port (Active LOW).
OEB
I
Synchronous Output Enable for B Port (Active LOW).
3
IDT74ALVC162268
3.3V CMOS 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
EXTENDED COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = – 40°C to +85°C
Symbol
VIH
VIL
Parameter
Input HIGH Voltage Level
Input LOW Voltage Level
VCC = 2.3V to 2.7V
Min.
1.7
Typ.(1)
—
Max.
—
VCC = 2.7V to 3.6V
2
—
—
VCC = 2.3V to 2.7V
—
—
0.7
VCC = 2.7V to 3.6V
—
—
0.8
±5
Test Conditions
Unit
V
V
IIH
Input HIGH Current
VCC = 3.6V
VI = VCC
—
—
µA
IIL
Input LOW Current
VCC = 3.6V
VI = GND
—
—
±5
IOZH
High Impedance Output Current
VCC = 3.6V
VO = VCC
—
—
± 10
µA
IOZL
(3-State Output pins)
VO = GND
—
—
± 10
µA
VIK
Clamp Diode Voltage
VCC = 2.3V, IIN = – 18mA
—
– 0.7
– 1.2
V
VH
Input Hysteresis
VCC = 3.3V
—
100
—
mV
ICCL
ICCH
ICCZ
∆ICC
Quiescent Power Supply Current
VCC = 3.6V
VIN = GND or VCC
—
0.1
40
µA
Quiescent Power Supply
Current Variation
One input at VCC − 0.6V,
other inputs at VCC or GND
—
—
750
µA
NEW16link
NOTE:
1. Typical values are at VCC = 3.3V, +25°C ambient.
OUTPUT DRIVE CHARACTERISTICS
Symbol
VOH
Parameter
Output HIGH Voltage
VCC
(A PORT)
Test Conditions(1)
= 2.3V to 3.6V
IOH = – 0.1mA
IOH = – 6mA
2
—
VCC = 2.3V
IOH = – 12mA
1.7
—
2.2
—
VCC = 3.0V
Output LOW Voltage
Max.
—
VCC = 2.3V
VCC = 2.7V
VOL
Min.
VCC – 0.2
2.4
—
VCC = 3.0V
IOH = – 24mA
2
—
VCC = 2.3V to 3.6V
IOL = 0.1mA
—
0.2
VCC = 2.3V
IOL = 6mA
—
0.4
IOL = 12mA
—
0.7
VCC = 2.7V
IOL = 12mA
—
0.4
VCC = 3.0V
IOL = 24mA
—
0.55
Unit
V
V
NEW16link
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the
appropriate VCC range. TA = – 40°C to + 85°C.
4
IDT74ALVC162268
3.3V CMOS 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
OUTPUT DRIVE CHARACTERISTICS
Symbol
VOH
Parameter
Output HIGH Voltage
VCC
EXTENDED COMMERCIAL TEMPERATURE RANGE
(B PORT)
Test Conditions(1)
= 2.3V to 3.6V
IOH = – 0.1mA
VCC = 2.3V
VCC = 2.7V
VCC = 3.0V
VOL
Output LOW Voltage
VCC = 2.3V to 3.6V
VCC = 2.3V
VCC = 2.7V
VCC = 3.0V
Min.
VCC – 0.2
Max.
—
IOH = – 4mA
1.9
—
IOH = – 6mA
1.7
—
IOH = – 4mA
2.2
—
IOH = – 8mA
2
—
IOH = – 6mA
2.4
—
IOH = – 12mA
2
—
IOL = 0.1mA
—
0.2
IOL = 4mA
—
0.4
IOL = 6mA
—
0.55
IOL = 4mA
—
0.4
IOL = 8mA
—
0.6
IOL = 6mA
—
0.55
IOL = 12mA
—
0.8
Unit
V
V
NEW16link
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the
appropriate VCC range. TA = – 40°C to + 85°C.
OPERATING CHARACTERISTICS, TA = 25oC
Symbol
Parameter
CPD
Power Dissipation Capacitance
Outputs enabled
CPD
Power Dissipation Capacitance
Outputs disabled
Test Conditions
CL = 0pF, f = 10Mhz
5
VCC = 2.5V ± 0.2V
VCC = 3.3V ± 0.3V
Typical
87
Typical
120
80
118
Unit
pF
pF
IDT74ALVC162268
3.3V CMOS 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
EXTENDED COMMERCIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS (A PORT)(1)
VCC = 2.5V ± 0.2V
Symbol
fMAX
VCC = 3.3V ± 0.3V
Min.
120
Max.
—
Min.
125
Max.
—
Min.
150
Max.
—
Unit
MHz
Propagation Delay
CLK to Ax (1B)
Propagation Delay
CLK to Ax (2B)
Propagation Delay
CLK to Ax (SEL)
Output Enable Time
CLK to Ax
Output Disable Time
CLK to Ax
Set-up Time, Ax data before CLK↑
1.6
5.8
—
5.4
1.7
4.8
ns
1.6
5.8
—
5.3
1.8
4.8
ns
2.5
7.3
—
6.5
2.4
5.8
ns
2
6.2
—
5.6
1.8
5.1
ns
2
6.5
—
5.4
2.1
5
ns
4.5
—
4
—
3.4
—
ns
tSU
Set-up Time, SEL before CLK↑
1.4
—
1.6
—
1.3
—
ns
tSU
Set-up Time, CLKENA1 or CLKENA2 before CLK↑
3.6
—
3.4
—
2.8
—
ns
tSU
Set-up Time, OEA before CLK↑
4.2
—
3.9
—
3.2
—
ns
tH
Hold Time, Ax data after CLK ↑
0
—
0
—
0.2
—
ns
tH
Hold Time, SEL after CLK↑
1
—
1
—
1
—
ns
tH
Hold Time, CLKENA1 or CLKENA2 after CLK↑
0.1
—
0.1
—
0.4
—
ns
tH
tW
Hold Time, OEA after CLK↑
Pulse Width, CLK HIGH or LOW
0
3.3
—
—
0
3.3
—
—
0.2
3.3
—
—
ns
ns
Output Skew(2)
—
—
—
—
—
500
ps
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tSU
tSK(o)
Parameter
VCC = 2.7V
NOTES:
1. See test circuits and waveforms. TA = – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
SWITCHING CHARACTERISTICS (B PORT)(1)
VCC = 2.5V ± 0.2V
Symbol
fMAX
Parameter
VCC = 2.7V
VCC = 3.3V ± 0.3V
Min.
120
Max.
—
Min.
125
Max.
—
Min.
150
Max.
—
Unit
MHz
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tSU
Propagation Delay
CLK to 1Bx, 2Bx
Output Enable Time
CLK to 1Bx, 2Bx
Output Disable Time
CLK to 1Bx, 2Bx
Set-up Time, Bx data before CLK↑
1.6
6.1
—
5.9
1.8
5.4
ns
2.7
7.2
—
6.8
2.6
6.1
ns
2.8
7.2
—
6.1
2.5
5.9
ns
0.8
—
1.2
—
1
—
ns
tSU
Set-up Time, CLKEN1B or CLKEN2B before CLK↑
3.2
—
3
—
2.5
—
ns
tSU
Set-up Time, OEB before CLK↑
4.2
—
3.9
—
3.2
—
ns
tH
Hold Time, Bx data after CLK↑
1.3
—
1.2
—
1.3
—
ns
tH
Hold Time, CLKEN1B or CLKEN2B after CLK↑
0.1
—
0
—
0.5
—
ns
Hold Time, OEB after CLK↑
Output Skew(2)
0
—
—
—
0
—
—
—
0.2
—
—
500
ns
ps
tH
tSK(o)
NOTES:
1. See test circuits and waveforms. TA = – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
6
IDT74ALVC162268
3.3V CMOS 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
EXTENDED COMMERCIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS:
TEST CONDITIONS
PROPAGATION DELAY
Symbol
VLOAD
VCC(1)= 3.3V±0.3V
VCC(1)= 2.7V
VCC(2)= 2.5V±0.2V
6
6
2 x Vcc
Unit
V
VIH
2.7
2.7
Vcc
V
SAME PHASE
INPUT TRANSITION
VT
1.5
1.5
Vcc / 2
V
OUTPUT
VLZ
300
300
150
mV
VHZ
300
300
150
mV
CL
50
50
30
tPLH
tPHL
tPLH
tPHL
V IH
VT
0V
V OH
VT
V OL
V IH
VT
0V
OPPOSITE PHASE
INPUT TRANSITION
pF
NEW16link
ALVC Link
TEST CIRCUITS FOR ALL OUTPUTS
ENABLE AND DISABLE TIMES
V LOAD
V CC
500Ω
(1, 2)
V IN
CONTROL
INPUT
GND
tPZL
V OUT
Pulse
Generator
D.U.T.
OUTPUT
SWITCH
NORMALLY
CLOSED
LOW
tPZH
OUTPUT
SWITCH
NORMALLY
OPEN
HIGH
500 Ω
RT
CL
ALVC Link
DEFINITIONS:
CL= Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.
Switch
VLOAD
SYNCHRONOUS
CONTROL
Open
tPHL1
tSK (x)
tPHZ
VT
V OH
V OH - V HZ
0V
0V
tSU
V IH
VT
0V
V IH
VT
0V
V IH
VT
0V
V IH
VT
0V
tH
tREM
tSU
tH
V IH
VT
0V
PULSE WIDTH
V OH
OUTPUT 1
V OL + V LZ
V OL
ALVC Link
(x)
tPLH1
V LOAD/2
VT
ASYNCHRONOUS
CONTROL
NEW16link
INPUT
V LOAD/2
TIMING
INPUT
GND
TSK
0V
SET-UP, HOLD, AND RELEASE TIMES
DATA
INPUT
Test
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other tests
tPLZ
V IH
VT
ALVC Link
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
SWITCH POSITION
OUTPUT SKEW -
DISABLE
ENABLE
Open
LOW-HIGH-LOW
PULSE
VT
V OL
tSK (x)
tW
V OH
VT
V OL
OUTPUT 2
VT
HIGH-LOW-HIGH
PULSE
VT
ALVC Link
tPLH2
tPHL2
tSK (x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
ALVC Link
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
7
IDT74ALVC162268
3.3V CMOS 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
EXTENDED COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
ID T
XX
A LV C
Tem p. R ange
X
XX
XXX
XX
B u s -H o ld
F a m ily
D e v ic e T y p e
P ackage
PV
PA
PF
S h rin k S m a ll O u tlin e P a c ka g e (S O 5 6 -1 )
T h in S h rin k S m a ll O u tlin e P a c ka g e (S O 5 6 -2 )
T h in V e ry S m a ll O u tlin e P a c k a g e (S O 5 6 -3 )
268
1 2 -B it to 2 4 -B it R e g iste re d B u s E x c h a n g e r w ith 3 -S ta te O u tp u ts
162
D o u b le -D e n sity , ± 2 4 m A (A p o rt)
± 1 2 m A (B p o rt)
B la n k
N o B u s -H o ld
74
– 4 0 °C to + 8 5 °C
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8