SUPERVISOR: DR. W. N. MWEMA
EXAMINER: DR. H. A. OUMA
Objective
The Objective of the Project is to design and implement a logic
prober to display truth-tables of combinational logic circuits
with upto 3 inputs. The truth table display will be as “1” and
“0” on an ordinary 60 MHz CRO
Introduction
The Combinational Logic Circuit Prober is a device that can
give the truth table of combinational logic circuits in form of
‘1’ and ‘0’ on an ordinary oscilloscope
The Combinational Logic Circuit Prober is more user friendly
in comparison to the Logic analyzer since no prior knowledge
is required and is also cheaper
The Combinational Logic Circuit Prober can also display data
from several channels making it useful in the analysis of
digital circuits as compared to the Logic Probe.
Design Overview
Lissajous patterns were used to plot ‘0’and ‘1’ on the
oscilloscope screen. To plot ‘0’, two sinusoidal signals in
quadrature were applied to the X and Y channels of the scope
set to the X-Y mode and to plot a ‘1’, the signal to the X
channel was blocked from reaching the scope
Two staircase waveforms were used to shift the ‘0’s and ‘1’s
on the oscilloscope screen so as to produce all the required 32
patterns for a 3-input combinational logic circuit
Design
Ouadrature Oscillator
The function of the quadrature oscillator in the project is to
produce two signals in quadrature
The quadrature oscillator was selected to be used in the
combinational logic circuit since it can economically produce
two signals in quadrature
The quadrature oscillator was operated at a frequency of 7 kHz
since this was the maximum frequency the designed oscillator
could operate without significant distortion at the output. This
frequency was also above the minimum required frequency of
2.6 kHz
Ouadrature Oscillator
Ouadrature Oscillator
The operational amplifier based oscillators were chosen over
the transistor based oscillators due to the availability of the
general purpose LM741 Op-Amp
The quadrature oscillator is economical compared to bubba
oscillator which requires four Op-Amps or a normal sinusoidal
oscillator with an integrator which will require more passive
components
Staircase Waveform Generator
Two staircase waveform generators are used to produce the two
staircase waveforms required by the project. One a 4 step staircase
waveform and the other an 8 step staircase waveform
The four step staircase waveform is responsible for the shift in the
horizontal direction with the 8 step staircase waveform being
responsible for the vertical shift of the pattern
The 4 step staircase waveform has the four levels selected by
Counter 1. The 8 step staircase waveform has the 8 levels selected
Counter 2
The staircase waveform generator is made up of a combination
timers, counters, potential dividers and analogue multiplexers
Staircase Waveform Generator
X and Y Position Controls
The X Position control is used to select the logic levels to be
displayed on the truth table, either a ‘1’ or a ‘0’ in addition to
shifting the pattern along the x axis
The X position control is comprised of a 4 channel analogue
switch, a 4 x 1 analogue multiplexer and the 4 step staircase
waveform generator. The channels of the analogue switch are
switched by a counter 2 with counter 1 providing the selection
bits for the analogue switch
The Y position control is used to shift the pattern along the y
axis
X Position Control
Other Modules
The Combinational Logic Circuit Prober is also made up of
two timers i.e. Timer 1 and Timer 2. Timer 1 is a clock pulse
generator of 1.8 kHz while Timer 2 generates a clock pulse of
446 Hz. The timers are used for driving the counters
Counter 1 and Counter 2 are 4 bit counters driven by Timer 1
and Timer 2 respectively. The counters are used for selection
purposes
Buffer circuits are also used in the Combinational Logic
Circuit Prober to prevent the loading of the various waveforms
Timer Requirements
To give the sinusoidal signals ample time to draw a complete
“0’ or a complete “1” on the oscilloscope screen, the frequency
of Timer 1 should be atleast half that of the oscillator. The
frequency of Timer 2 should allow all the first four patterns to
be plotted on the scope before moving to the second level.
Therefore the frequency of Timer 1 should be four times that
of Timer 2 at the very minimum.
The refresh rate is about 18 ms or 55 Hz
Results
Truth Table for a 3 Input NAND Gate
Results
Truth Table for a Simple Even Bit Parity Generator Circuit
Discussion
In the obtained truth tables, the “1”s on the oscilloscope screen
appeared unstable, though they were clearly distinguishable from
the “0”s. This was as a result of imperfect switching by the analogue
switch. The signals at the gate outputs were transmitted faithfully
when the channel was connected, but when the channel was
disconnected an unstable and attenuated version of the sinusoidal
signal was transmitted when no signal was to be transmitted.
Some of the “0” were also noted to be elliptic in shape while others
were perfect zeros. This was as a result of the nonlinear attenuating
effect of the staircase waveform on the sinusoidal signal. The
attenuation factor increases up the staircase and was as a result of
the different impedance seen by the sinusoidal signal up the
staircase waveform in both the X and the Y paths.
Conclusion
The ‘0’s and ‘1’s obtained by the Combinational Logic Circuit
Prober were clearly distinguishable therefore showing that the
truth table for a 3 Input combinational logic circuit can be
obtained in form of ‘0’s and ‘1’s on an ordinary 60 MHz
oscilloscope
Further Work
The problem of the difference between the zeros can be
eliminated by implementing a nonlinear amplifier with the
gain factor dependent on the input signal amplitude. It is
therefore recommended that such a circuit be complement the
Combinational Logic Circuit Prober
It is also recommended that a suitable adapter for ECL logic
families be implemented to enable their truth tables be
extracted by the Combinational Logic Circuit Prober