CMOS Comparators
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' ♣ IsLab | & 9 r h Û ¼% 7 ½ ¨z ´ Ä » @ © / Analog Integrated Circuit Design $ COMP-21 CMOS Comparators _ × õ > ¦ »Á כ É þ Ù Kyungpook National University & % Integrated Systems Lab, Kyungpook National University ' ♣ IsLab | & 9 r h Û ¼% 7 ½ ¨z ´ Ä » @ © / Analog Integrated Circuit Design $ COMP-1 Comparators ❏ A comparator is used to detect whether a signal is greater or smaller than zero, or to compare the value of one signal to another. ❏ The second most widely used components after amplifiers. ❏ Widespread use in A/D converters, data transmission, switching power regulators. ❏ Using an opamp for a comparator: too slow but a good example to discuss design principles for minimizing VOS and charge injection. ❏ Other approaches: multistage comparators, positive-feedback track-and-latch comparators, fully differential comparators. & Integrated Systems Lab, Kyungpook National University % ' ♣ IsLab | & 9 r h Û ¼% 7 ½ ¨z ´ Ä » @ © / Analog Integrated Circuit Design $ COMP-2 Using An Opamp for A Comparator ❏ Using an open-loop opamp for a comparator. ❏ Slow response time due to slewing and settling time. ❏ A simple approach. VOS vi −+ + vo − ❏ Limited resolution due to VOS of 2 ∼ 5 mV for typical MOS processes. & ' % Integrated Systems Lab, Kyungpook National University ♣ IsLab | & 9 r h Û ¼% 7 ½ ¨z ´ Ä » @ © / Analog Integrated Circuit Design $ COMP-3 Switched-Capacitor Comparator ❏ Operation: reset phase (φ1 ) + comparison phase (φ2 ). C vi φ1a − φ2 φ1 + vo ❏ φ1a is a slightly advanced version of φ1 so that charge-injection effects are reduced to the effect due to only the switch φ1a . ❏ The opamp must be stable for unity-gain feedback during φ1a . ❏ The bottom plate of integrated capacitors has more significant parasitic capacitance between it and substrate than the top plate. & Integrated Systems Lab, Kyungpook National University % ' ♣ IsLab | & 9 r h Û ¼% 7 ½ ¨z ´ Ä » @ © / Analog Integrated Circuit Design $ COMP-4 ❏ Therefore, the bottom plate is always connected to the less sensitive node rather than critical node. ❏ Although used in early ADCs, this opproach is not preferable nowadays due to slow operation (500 Hz). ❏ A technique for speeding up (50 times) the comparision time is to disconnect the compensation capacitor during the comparision phase. ❏ The input capacitor C is never charged or discharged during operation, vC remains at 0 V. Use a reasonably large C to minimize charge injection and clock-feedthrough effects. ❏ If φ1 and φ2 of switches attached to the bottom plate interchanged, the comparision operation would be noninverting. But C must be charged or discharged during reset phase. & ' Integrated Systems Lab, Kyungpook National University ♣ IsLab | & 9 r h Û ¼% 7 ½ ¨z ´ Ä » @ © / Analog Integrated Circuit Design Cancelling Input-Offset Voltage Errors % $ COMP-5 ❏ The reset phase. VOS vi φ2 − φ1 + φ1a − + vo VOS + − ❏ The comparision phase. VOS vi φ2 − φ1 & + φ1a − + vo VOS + − Integrated Systems Lab, Kyungpook National University % ' ♣ IsLab | & 9 r h Û ¼% 7 ½ ¨z ´ Ä » @ © / Analog Integrated Circuit Design Charge-Injection Errors $ COMP-6 ❏ Charge injection (clock feedthrough): unwanted charges is injected into the circuit when the transistors turn off. ❏ The comparator with switches: channel charge + overlap C. φ1a φ2 Cov1 vi v1 Q1 φ1 Cov2 & Cov3 v2 C Q3 − vo + Q2 Integrated Systems Lab, Kyungpook National University ' ♣ IsLab | & 9 r h Û ¼% 7 ½ ¨z ´ Ä » @ © / Analog Integrated Circuit Design ❏ Channel charge: VDS = 0. % $ COMP-7 Qch = W LCox (VGS − Vt ) ❏ When Q3 turns off: ∆v2c (channel charge) + ∆v2o (overlap C). ∆v2c ∆v2o Qch /2 Cox W3 L3 Veff3 Cox W3 L3 (VDD − Vtn ) =− =− C 2C 2C (VDD − VSS )Cov3 ∆vGS3 Cov3 =− = − C + Cov3 C + Cov3 = v2 vGS3 Cov3 & C ∴ Resolution ≫ |∆vC | = |∆v2c + ∆v2o | ≃ 13 + 10 = 23 mV Integrated Systems Lab, Kyungpook National University % ' ♣ IsLab | & 9 r h Û ¼% 7 ½ ¨z ´ Ä » @ © / Analog Integrated Circuit Design $ COMP-8 Making Charge-Injection Signal Independent ❏ When Q2 turns off, its charge injection causes a negative glitch at v1 , but this will not cause any change in the charge stored in C since the right side of C is connected to an open node (no current flow). i=C dvC = 0, dt ∆vC = v2 − v1 = 0 ❏ Thus, v2 is unaffected by the charge injection of Q2 . When Q1 turns on, v1 will settle to vi regardless of the charge injection of Q2 . The charge injection of Q1 has no effect due to similar reason. ❏ By turning off φ1a first, the circuit is affected only by the charge injection of Q3 . And the charge injection is signal independent. & ' Integrated Systems Lab, Kyungpook National University ♣ IsLab | & 9 r h Û ¼% 7 ½ ¨z ´ Ä » @ © / Analog Integrated Circuit Design A Clock Generator with Advanced Phases % $ COMP-9 ❏ Nonoverlapping two-phase clock with phases advanced by two inverter delays. φ1a φ1 φ2a φ2 φ & Integrated Systems Lab, Kyungpook National University % ' ♣ IsLab | & 9 r h Û ¼% 7 ½ ¨z ´ Ä » @ © / $ Analog Integrated Circuit Design COMP-10 Minimizing Errors Due to Charge Injection ❏ The simplest way is to use larger capacitors, but this would require a large amount of silicon area: ∆vC ∝ 1/C. ❏ Integrated capacitors have parasitic capacitances between the bottom plate and the substrate. This bottom plate capacitance might be about 20% of the size of the realized capacitor. This capacitor would have to be driven by the input circuits, which would slow down the circuits. A top plate capacitance also exists due primarily to interconnect capacitance, but it is typically on the order of 1 to 5% of the realized capacitance. & % Integrated Systems Lab, Kyungpook National University ' ♣ IsLab | & 9 r h Û ¼% 7 ½ ¨z ´ Ä » @ © / Analog Integrated Circuit Design $ COMP-11 ❏ A fully differential switched-capacitor comparator: the charge injection of Q3a matches that of Q3b → ∆vC /10. φ2 φ1a C + Q1 φ2 vi Q3a Q2 φ1 C − −+ +− Q3b + vo − Q3 Q4 & φ1 φ1a Integrated Systems Lab, Kyungpook National University % ' ♣ IsLab | & 9 r h Û ¼% 7 ½ ¨z ´ Ä » @ © / Analog Integrated Circuit Design $ COMP-12 ❏ A multistage switched-capacitor comparator: error voltage storing (φ1 ) + eliminating (φ2 ), the uncompensated error voltage in the input of the last stage ∆vCn , ∆vC1 = charge injection + offset, input equivalent error voltage ∆vi (57 µV), refer to clock waveforms. v1 (φ̄11 ) = −A1 (∆vC1 ) = −vC2 , v1 (φ2 ) = −A1 (vi + ∆vC1 ) v2 (φ2 ) = v1 (φ2 ) + vC2 = −A1 (vi + ∆vC1 ) + A1 ∆vC1 = −A1 vi ∆vC2 −∆vCn vo = −A2 (v2 + ∆vC2 ) = A1 A2 vi − → ∆vi = A1 A1 A2 · · · An−1 φ2 ∆vC1 vi φ1 & −C + 1 φ11 − + v1 v2 −C + A1 2 φ12 − + vo A2 % Integrated Systems Lab, Kyungpook National University ' ♣ IsLab | & 9 r h Û ¼% 7 ½ ¨z ´ Ä » @ © / $ Analog Integrated Circuit Design COMP-13 Speed of Multistage Comparators ❏ A multistage comparator using a cascade of inverters: very high resolution as combining with fully differential design techniques. Although the multistage comparator has speed limitation due to multiphase clock, it can be reasonably fast and stable because of high-speed individual stages that have only a 90◦ phase shift. ❏ The parasitic load capacitance of the ith stage: except for the last stage, Cpi ≃ Co,i + Cgs,i+1 < 2Cgs,i for large W if Cgs ≫ Co , Cr . vo vi & A1 Cp1 A2 Cp2 A3 Integrated Systems Lab, Kyungpook National University Cp3 % ' ♣ IsLab | & 9 r h Û ¼% 7 ½ ¨z ´ Ä » @ © / $ Analog Integrated Circuit Design COMP-14 ❏ The unity-gain frequency of a single stage i: CL = 2Cgs,i . ωti ≃ gmi ωT = 2Cgs,i 2 ❏ The transfer function of a single stage: dominant-pole approximation. Ai (s) ≃ A0i , 1 + s/ωpi ωpi ≃ ωti A0i ❏ The overall transfer function of an n-stage comparator. A(s) = Y Q An0 A0i P ≃ Ai (s) ≃ 1 + s 1/ωpi 1 + sn/ωpi ❏ The overall time constant of an n-stage comparator. & n 2nA0 Cgs 4nA0 L2 τ≃ = ≃ ≃ 4 ns ωpi gm 3µn Veff % Integrated Systems Lab, Kyungpook National University ' ♣ IsLab | & 9 r h Û ¼% 7 ½ ¨z ´ Ä » @ © / $ Analog Integrated Circuit Design COMP-15 Latched Comparators ❏ A modern high-speed comparator: preamp + track-and-latch stage. vL vL vo+ Preamplifier vi+ +− vi− −+ & vo− vL vL track and latch Integrated Systems Lab, Kyungpook National University % ' ♣ IsLab | & 9 r h Û ¼% 7 ½ ¨z ´ Ä » @ © / Analog Integrated Circuit Design $ COMP-16 ❏ Preamplifiers: low gain (4 ∼ 10) for high speed, used for higher resolution and reduction of kickback effects. Kickback denotes the charge transfer either into or out of the inputs when the TAL stage goes from track mode to latch mode. Without a preamplifier, cause very large glitches in the input circuit, especially when the input impedances are not perfectly matched → limited accuracy. ❏ The track-and-latch stage: amplifies the signal further during the track phase, and then amplifies it again during the latch phase by positive feedback → minimizes the total number of gain stages. ❏ Hysteresis might be eliminated by connecting internal nodes to one of power supplies or by connecting differential nodes together (no memory). ❏ For high resolution, coupling capacitors and reset switches are included to eliminate any VOS and ∆vC errors. & % Integrated Systems Lab, Kyungpook National University ' ♣ IsLab | & 9 r h Û ¼% 7 ½ ¨z ´ Ä » @ © / $ Analog Integrated Circuit Design COMP-17 Latch-Mode Time Constant ❏ Two back-to-back inverters as a simplified model of a TAL stage in the latch phase. The inverters can be modelled as a VCCS driving an RC load for vx ≃ vy . + vy vx vx − + RL CL Av vy RL RL − CL Av vx RL ❏ Node equations by KCL: τL = RL CL , ∆v ≡ vx − vy . τL & dvy dvx + vx + Av vy = 0, τL + vy + A v vx = 0 dt dt τL d∆v = ∆v Av − 1 dt Integrated Systems Lab, Kyungpook National University % ' ♣ IsLab | & 9 r h Û ¼% 7 ½ ¨z ´ Ä » @ © / Analog Integrated Circuit Design $ COMP-18 ❏ Voltage difference between the output voltages of inverters. ∆v = ∆v0 e(Av −1)t/τL ≡ ∆v0 et/τ ❏ Latch-mode time constant: CL ≃ k1 W LCox , Gm ≃ k2 gm . τL RL CL CL k1 L2 L2 τ= ≃ = = = (2 ∼ 4) Av − 1 Av Gm k2 µn Veff µn Veff ❏ The latch time for a voltage difference ∆v → ∆vL (valid logic voltage) → the speed would be limited by preamplifiers and TAL during track phase. ∆vL ≃ 0.5 ns → 1 GHz tlatch = τ ln ∆v0 ❏ If ∆v0 is small, the rise time can be larger than the allowed time for the latch phase → undetermined logic value for succeeding circuitry. This is called metastability. Even when ∆v0 is large enough, circuit noise can cause ∆v0 to become small enough to cause metastability. & % ' $ Integrated Systems Lab, Kyungpook National University ♣ IsLab | & 9 r h Û ¼% 7 ½ ¨z ´ Ä » @ © / Analog Integrated Circuit Design COMP-19 A Two-Stage Comparator with Digital Output ❏ Low-impedance nodes and diode-connected loads for high speed, precharging nodes to eliminate hysteresis, fully differential comparator. Latch Preamplifier + v − o Digital output + vi − Positive feedback Latch & Integrated Systems Lab, Kyungpook National University % ' ♣ IsLab | & 9 r h Û ¼% 7 ½ ¨z ´ Ä » @ © / Analog Integrated Circuit Design $ COMP-20 A Two-Stage Comparator with Capacitive Coupling ❏ Capacitive coupling to eliminate VOS and charge-injection errors: resolution ∆v < 0.1 mV at a 2-MHz clock frequency for 5-µm technology. Positive feedback CMFB circuitry C2 φ2 C1 φ11 + vi − φ11 φ12 C2 φ1 φ2 C1 & φ12 Track Track Second gain stage First SC gain stage % Integrated Systems Lab, Kyungpook National University ' ♣ IsLab | & 9 r h Û ¼% 7 ½ ¨z ´ Ä » @ © / Analog Integrated Circuit Design $ COMP-21 Homework ❏ Problems: 7.1, 7.6, 7.7, 7.8, 7.11. ❏ Describe the operation principle and the important properties of the comparator used in [1]. References [1] Y. T. Wang and B. Razavi, “An 8-Bit 150-MHz CMOS A/D Converter”, IEEE J. of Solid-State Circuits, vol. 35, no. 3, pp. 308–317, 2000. [2] A. Worapisher, J. B. Hughes, and C. Toumazou, “Speed and accuracy enhancement techniques for high-performance switched-current comparators”, IEEE J. of Solid-State Circuits, vol. 36, no. 4, pp. 687–690, 2001. & Integrated Systems Lab, Kyungpook National University %
