Comparator Design
Ken Martin
Dept. of Elec. and Comp. Eng.
University of Toronto
Toronto, Canada M5S 1A4
martin@eecg.toronto.edu
(416) 978-6695
© K.W. Martin, 1997
1
Comparators
Using an Op-Amp for a Comparator
• Can use an uncompensated op-amp for a comparator.
• This comparator has a resolution limited to the input-offset-voltage of the op-amp
on the order of 2mV to 5mV for typical MOS processes.
• In many applications, this would be inadequate.
V in
Vout
• An alternative architecture which can resolve signals with accuracies much less
than the input-offset-voltages of op-amps is shown below.
φ1'
φ2
Sr
C
V in
φ1
Vout
Bottom Plate
• During φ 1 the bottom plate of the capacitor C (i.e. the left side of capacitor C) is
connected to ground and the top plate is connected to the inverting input of the
op-amp. At the same time, the output of the op-amp is also connected to the
inverting input of the op-amp by closing switch S r .
• During the comparison phase, the reset switch, S r , is turned off, and the top plate
of the capacitor is connected to the input voltage. If the input signal is greater
than zero, the output of the op-amp will saturate negative; if the input signal is
less than zero, the output of the op-amp will saturate positive. These two cases
are easily resolved and stored using a simple digital latch.
© K.W. Martin, 1997
2
• The limitations of this approach become apparent when one considers non-ideal
op-amps, having finite gains, and needing compensation in order to be stable
during the reset phase.
• For example, consider the case where a 0.5mV signal must be resolved. After
comparison, the output of the op-amp should have a 5V difference between the
cases when the input signal is -0.25mV and +0.25mV. This means the gain of the
op-amp must be at least 10,000. Thus, the open-loop time constant of the
comparator will be on the order of 10 4 ⁄ ω ta . This limits the clock frequency to
about 500kHz which is normally unacceptably slow.
• During the comparison time, the compensation capacitor should be disconnected
as shown below.
Vin
Vin
Q1
φ1
Cc
Vout
• Transistor Q1 is used to achieve lead compensation when it is on during the reset
phase, φ 1 . During the comparison phase, Q1 is turned off which disconnects the
compensation capacitor C c thereby greatly speeding up the op-amp during this
phase.
© K.W. Martin, 1997
3
Multi-Stage Versus Single Stage Approach
Assume that a gain stage has a unity-gain frequency ω t given by
W
µ n C ox -----V eff
g
1
1 µ n V eff
L
1 m
ω t-i = --- --------- = --- --------------------------------- = --- ---------------3 2
2 L2
3 C gs
--- WLC ox
3
(1)
Note that g m ⁄ C gs is the approximate unity-gain frequency of a transistor. This
approximation is optimistic for single stages having very large gain. Further
assume each stage is approximated by a first order transfer function
A i-0
A i(s) = ------------------------------1 + s ⁄ ω -3dB
(2)
From (2) and using A i(ω t) = 1 , we have
ω t-i
ω -3dB ≅ --------A i-0
(3)
The settling time constant of a single stage is 1 ⁄ ω -3dB .
A i-0 L 2
τ i = 2 ---------------µ n V eff
(4)
Assuming we need 3τ i for settling time in half a period T ⁄ 2 , we have
ω t-i
1 µ n V eff
1
1
F max = --- = ------- = ------------- = ------ ---------------12 A L 2
6A i-0
T
6τ i
i-0
(5)
For a single stage, assume we have A 0 = 10 4 , L = 0.5µm , V eff = 0.25V ,
µ n = 0.05M 2 ⁄ V ⋅ S . This gives F max = 417kHz . For a cascade of three
stages, A i-0 = 3 A 0 = 3 10 4 = 21.5 , but we now need three times the settling
time as for a single stage and we get F max = 1 ⁄ 18τ i = 65MHz .
Thus, the cascade of three lower-gain comparators is 155 times faster than a
single high-gain stage.
© K.W. Martin, 1997
4
Clock-Feedthrough Errors
• Perhaps the major limitation on the resolution of comparators is due to what is
called clock-feedthrough.
• This error is due to transistor channel-charge flow when transistors turn off.
• When they turn off, there are two mechanisms whereby charge errors occur. The
first is due to the channel charge which must flow out from the channel region of
the transistor to the drain and the source junctions. The channel charge of a
transistor having zero V DS is given by
Q CH = W 3 L 3 C V eff = W 3 L 3 C ox ( V GS – V t )
(6)
ox
• Another, usually somewhat smaller charge, unless V eff is very small, is due to
the overlap capacitance between the gate and the junctions.
• Shown below is the comparator using n-channel switches and parasitic capacitors
to model the overall charge efffects when transistors turn off.
φ'1
φ2
C3a
C 1a
C3b
C1b
Q1
Vin
V'
C
V''
Q3
Vout
φ1
C2a
Q2
C2b
The comparator of
shown.
with n-channel switches and the parasitic capacitances
• Consider first when Q 3 turns off. If the clock waveform is very fast, the channel
charge due to Q 3 will flow equally out through both junctions [Shieh/87].
• The charge that goes to the output node of the op-amp will have very little effect
other than causing a temporary glitch.
© K.W. Martin, 1997
5
• However, the charge that goes to the inverting-input node of the op-amp will
cause the voltage across C to change which introduces an error. Since this charge
is negative, for an n-channel transistor, the node voltage V″ will go negative. The
voltage change due to the channel charge is given by
Q ch
V eff3 C ox W 3 L 3
( V DD – V tn )C ox W 3 L 3
∆V″ = ---------- = – --------------------------------------- = – --------------------------------------------------------(7)
2C
2C
2C
since
the
effective
gate-source
voltage
of
Q3
is
given
by
V eff3 = V GS3 – V tn = V DD – V tn . The above voltage change in V″ is based
on the assumption that Q 2 turns off slightly after Q 3 . More will be said about
this assumption shortly.
• To calculate the change in voltage due to the overlap capacitance, we have
– ( V DD – V SS ) C ov
∆V″ = -----------------------------------------------C ov + C
(8)
• The clock feedthrough of transistors Q 1 and Q 2 may cause temporary glitches
but will have much less effect than the clock feedthrough of Q 3 , if it is assumed
that Q 2 turns off slightly after Q 3 [Haigh/83]. (This time difference is the reason
why the clock voltage of Q 2 is denoted φ 1 , whereas the clock voltage of Q 3 is
denoted φ 1 ′ ).
• The argument for this is slightly complicated but goes as follows. When Q 2 turns
off, its clock feedthrough will cause a negative glitch at V′ , but this will not cause
any change in the charge stored in C since the right side of C is connected to an
effective open circuit assuming Q 3 has already turned off. Later, when Q 1 turns
on, the voltage V′ will settle to V in irrespective of the previous clock
feedthrough of Q 2 . Thus, the voltage at the left of C is unaffected by the clockfeedthrough of Q 2 , and the voltage across C is also unaffected by the clockfeedthrough of Q 2 . Therefore, the voltage V″ is unaffected by the clock
feedthrough of Q 2 . This would not be the case if Q 2 was turned off at the same
time or before turning off Q 3 . The clock-feedthrough of Q 1 has no effect due to
a simpler argument, the comparison has already been made when it turns off. In
addition, its clock-feedthrough has no effect when it turns on because the right
side of C is connected to an open circuit at that time, assuming non-overlapping
clocks.
© K.W. Martin, 1997
6
Input-Offset-Voltage Cancellation
• Another source of error is due to the input-offset voltage of the op-amp.
• In switched-capacitor comparators, such as that shown above, it is not a problem
as it is stored onto the capacitor during the reset phase as shown below.
During φ1:
φ1'
C
φ1
Sr
Voff
Vout
Voff
Voff
During φ2:
φ2
V in + Voff
φ1'
Sr
C
V in
Vout
Voff
Voff
•
• Not only does this technique eliminate input-offset-voltage errors, but it also
minimizes errors caused by low-frequency 1/f noise which can be quite large in
CMOS IC’s.
© K.W. Martin, 1997
7
Minimizing Errors Due to Clock Feed-through
• The simplest way to reduce errors due to clock feedthrough is to use larger
capacitors. For our previous example, capacitors on the order of 100 pF, or so,
would guarantee that the clock-feedthrough errors were less than 0.5 mV.
• An alternative approach for minimizing errors due to clock feedthrough is to use
fully-differential design techniques for comparators as shown below.
φ2
φ1'
C
Q3a
φ1
Vin
Vout
φ2
φ1
Q3b
C
φ1'
• Ideally, when the comparator is taken out of reset mode, the clock-feedthrough of
reset switch Q 3a will match the clock-feedthrough of Q 3b . The only errors now
will be due to mismatches in the clock-feedthrough of the two switches which
will be at least ten times smaller, typically, than in the single-ended case.
Normally, comparators are always designed as fully differential, although we will
often show them as single-ended to simplify schematics.
• A third alternative, that can be used along with fully-differential design
techniques, is to realize a multi-stage comparator where the clock-feedthrough of
the first stage is stored on coupling capacitors between the first and second stage,
thereby eliminating its effect. Also, the clock feed-through of the second stage
can be stored on the coupling capacitors between the second and the third stages,
etc. A single-ended version is shown below.
• Consider the time when φ1' goes low and the switch of the first stage has charge
injection. When φ1' goes low, Q 1 will inject charge into both the inverting input
and the output of the first stage. The charge injected at the first stage output will
only cause a temporary glitch there. The charge injected at the inverting input
© K.W. Martin, 1997
8
φ 1'
Vin φ2
C1
φ1
φ1''
C2
OA1
φ1'''
C3
OA2
Vout
OA3
φ1
φ1'
φ1''
φ1'''
φ2
will cause this node to go negative. The amount this node voltage will be in the
range of tens of millivolts or so. After the inverting input goes negative, the
output of the first stage will go positive by an amount equal to the negative
transition of the inverting input multiplied by the first stage’s gain. However, at
this time φ1'' is still high. Therefore, the second-stage is still being reset.
Therefore, C 2 is charged up to whatever the error caused by the clockfeedthrough of the first stage is. This eliminates its effect. In a similar manner,
when φ1'' turns off and the second-stage goes from closed-loop reset mode to
open-loop comparison mode, the third stage is still in reset mode and the clockfeedthrough of the second stage is stored on coupling capacitor C 3 . Finally,
when the third stage turns off, its clock feedthrough is not cancelled. However,
the error it causes in resolving an input voltage to all three stages is equal to the
voltage transition at the inverting input of the third stage divided by the negative
of the gains of the first two stages. (i.e. This is the input voltage needed to cancel
the effect of the clock-feedthrough of the third stage coming out of reset mode.)
© K.W. Martin, 1997
9
Latched Comparators
• Modern comparators will have 1-3 gain stages followed by a track-and-latch
stage. The track-and-latch stage operates as an amplifier during φ 1 and then is
reconfigured into a positive-feedback latch during φ 2 .
Latch-Mode Time-Constant
• Consider two inverting amplifiers connected in a positive-feedback loop.
Vy
Vx
• This can be modelled by small-signal model where each inverter has a
transconductance given by G m = A V ⁄ R L where A V is the inverter gain.
AV
-------V y
RL
Vy
CL
RL
RL
CL
Vx
AV
-------V x
RL
• We have
AV
dV x  V x 
-------V y = – C L  ---------- –  -------
RL
dt
 R L
(9)
AV
dV y  V y 
-------V x = – C L  ---------- –  -------
RL
dt
 R L
(10)
and
Multiplying (9) and (10) by R L and rearranging gives
© K.W. Martin, 1997
10
dV x

τ ---------- + V x = – A V V y
 dt 
(11)
dV y
τ  ---------- + V y = – A V V x
 dt 
(12)
and
where τ = R L C L is the time-constant at the output node of each invertor.
Subtracting (12) from (11) and rearranging terms gives
τ   d∆V 
 --------------- = ∆V
 A – 1-  ---------dt 
(13)
V
where ∆V = V x – V y is the voltage difference between the output voltages of
the invertors. Equation (13) is a first-order differential equation with no forcing
function. Its solution is given by
∆V = ∆V 0 e
AV – 1
 --------------t
 τ -
(14)
where ∆V 0 is the initial voltage difference at the beginning of the latch phase.
Thus, the voltage difference increases exponentially in time with a time-constant
given by
RL CL
CL
τ
τ ltch = ---------------- ≅ --------------- = --------AV – 1
AV
Gm
(15)
where again G m = A V ⁄ R L is the transconductance of each invertor. Note that
τ ltch is roughly equal to the inverse of the unity-gain frequency of each
invertor.
• In the case of MOS devices, normally the output load will be proportional to the
gate-source capacitance of a single transistor, or specifically,
C L = K 1 WLC ox
© K.W. Martin, 1997
11
(16)
Here, K 1 is a proportionality constant which might be between 1 and 2. Also, the
invertor transconductance will be proportional to the transconductance of a single
transistor given by
W
G m = K 2 g m = K 2 µ n C ox -----V eff
L
(17)
where K 2 might be between 0.5 and 1. Substituting (16) and (17) into (15) gives
K1 L 2
L2
τ ltch = ------ ----------------- = K 3 ----------------K 2 µ n V eff
µ n V eff
(18)
where K 3 might be between 2 and 4. Note that (18) implies that τ ltch is
dependant primarily on the technology and is not very dependant on the design
(assuming a reasonable design is used that maximizes V eff and minimizes C L ).
Note also the similarity between (18) and (4), the equation for the time-constant
of a cascade of gain stages. For a given technology, (18) is very useful in
determining a rough estimate for the maximum clock frequency of a latch-andtrack comparator.
• If it is necessary for a voltage difference of ∆V logic to be obtained for succeeding
logic circuitry to safely recognize the correct output value, then through the use
(14), the time necessary for this to happen is given by
C L  ∆V logic
 ∆V logic
L2
T ltch = --------- ln  ------------------ = K 3 ----------------- ln  ------------------
G m  ∆V 0 
µ n V eff  ∆V 0 
This analysis is the basis for understanding Comparator Metastability.
© K.W. Martin, 1997
12
(19)
Examples of Modern High-Speed CMOS Comparators
• A modern high-speed CMOS comparator will typically have one or two stages of
pre-amplification followed by a track-and-latch stage, as is shown below
[Yukawa, 85].
Q5a
Q4a Q4b
Q5b
Vltch
Vltch
Vout+
V2a
Vin+
Vltch
Vin-
V1a
V2b
Q3a
Q3b
Vltch
Vout-
V1b
Q1b
Q1a
Preamplifier Stage
Q2aQ2b
Track-and-Latch Stage
• The preamplifier (or preamplifiers) are required to obtain higher resolution and to
minimize the effects of ‘flash-back’. The output of the preamplifier, although
larger than the comparator input, is still much smaller than the voltage levels
needed to drive digital circuitry. The track-and-latch stage then amplifies this
signal further during the track-phase, and then also during the latch-phase when
the positive feedback is enabled which regenerates the analog signal into a fullscale digital signal. The use of the track-and-latch stage minimizes the total
number of gain stages required, even when good resolution is needed, and, thus,
is faster than the multi-stage approach just described.
• Flash-back denotes the charge transfer either into or out of the inputs when the
track-and-latch stage goes from track-mode to latch-mode. It is caused by the
charge needed to turn the transistors in the positive feedback circuitry on, and by
the charge that needs to be removed in order to turn transistors in the tracking
circuitry off. Without having a preamplifier or buffer, this flash-back will go into
the driving circuitry causing very large glitches, especially in the case when the
impedance seen looking into the two inputs is not perfectly matched.
© K.W. Martin, 1997
13
• In the above design, the pre-amp is a simple p-channel input differential
amplifier. During reset mode, its outputs are shorted together. At the same time,
Q 3a and Q 3b are off. This causes nodes V 1a and V 1b to be reset low since
Q 1a and Q 1b are on. At the same time, Q 5a and Q 5b are on causing V 2a and
V 2b to be reset high. Next, during the sample and latch mode, the two crosscoupled latches are connected together by Q 3a and Q 3b and nodes V 2a and
V 2b will dicscharge negatively until the cross-coupled pair of Q 4a and Q 4b is
activated. When this happens, the positive feedback of this cross-coupled pair and
of Q 2a and Q 2b quickly amplifies the small differential signal to full logic
levels.
• In high-resolution applications, capacitive coupling and reset switches will also
typically be included to eliminate any input-offset-voltage and clock-feedthrough
errors, in a manner similar to what was described previously.
• Another example of the above architecture is shown below [Song/90]. This
Vout
Vin
Trk
Preamp
Gain Stage
Positive Feedback
A two-stage comparator having a preamplifier and a positive-feedback track-andlatch stage.
comparator actually has the positive feedback of the second stage always enabled.
In track mode, when the two diode-connected transistors of the gain-stage are
© K.W. Martin, 1997
14
enabled, the gain around the positive-feedback loop is less than one and the
circuit is stable. The combination of the diode-connected transistors of the gain
stage and the transistors of the positive-feedback loop act as a moderately large
impedance giving gain from the preamplifier stage to the track-and-latch stage.
The diode-connected loads of the preamplifier stage give a limited amount of gain
in order to maximize speed, while still buffering the flash-back from the input
circuitry.
• A third example is shown below. . [Norsworthy/89]. This design also uses diode-
Latch
Vout
Digital SignalLevel Restoration
Vin
Latch
Preamp
Positive Feedback
A two-stage comparator from [Norsworthy/89].
connected loads in order to keep all nodes relatively low impedance (similar to
current-mode circuit-design techniques), thereby keeping all node time constants
small and giving fast operation. This design also uses pre-charging to eliminate
any memory from the previous decision. For example, the positive-feedback stage
© K.W. Martin, 1997
15
is pre-charged low, whereas the digital-restoration stage is pre-charged high
somewhat similar to what is done in Domino CMOS logic.
• A fourth example was designed by one of the authors [Martin/84] and is shown in
. The appropriate clock-waveforms for this design are shown in . This design
First-Stage Common-Mode
Feedback
φ1 ′
φ2
Vin
C1A
φ1 ′
φ1
φ2
C1B
First SC Gain Stage
Second Gain Stage
C2A
C2A
φ1 ″
Positive Feedback
Stage
φ1 ″
Trk
Trk
A two-stage comparator with capacitive coupling to eliminate input-offset voltage and
clock-feedthrough errors, along with positive feedback for fast operation.
© K.W. Martin, 1997
16
φ1
φ1 ′
φ1 ″
Trk
The clock waveforms required by the comparator of .
eliminates any input offset voltages form both the first and second stages by using
capacitive coupling. It also has common-mode feedback circuitry for the first
preamplifier stage which allows for input signals having large common-mode
signals. Unlike in fully-differential op-amps, the linearity of the common-mode
feedback circuitry in fully-differential comparators is non-critical as whenever
large signals are present (and the common-mode feedback circuitry becomes nonlinear) there is no ambiguity in resolving the sign of the input signal. Measured
(but unpublished) performance of this circuit resulted in a 0.1mV resolution at a
2MHz clock frequency, despite a very old 5µm technology. The performance
measured was limited by the test set-up rather than the circuitry.
• A fifth example, realized in a BiCMOS technology, that exhibited very good
performance, was described in [Razavi/92]. Indeed, at the time of publication,
this comparator is one of the better BiCMOS designs to date. It is based on the
realization that it not necessary to reset the first stage and the input-offset errors
of the first stage can still be eliminated by resetting the right side of the coupling
capacitors between the first stage and the second stage, based on the assumption
that the gain of the first stage is not too large [Poujois, 1978] [Vittoz, 1985]. A
simplified schematic of this comparator is shown in . During reset phase, the
inputs to the preamplifier are connected directly to ground (or a reference
voltage), while the outputs of the coupling capacitors are connected to ground as
well. This stores any offset voltages of the first stage on the capacitors. When the
comparator is taken out of reset phase, then the effect of the clock-feedthrough of
S 5 and S 6 on the input resolution is divided by the gain of the first stage. In the
realization described in [Razavi/92], the first stage was a BiCMOS preamplifier
consisting of MOS source followers followed by a bipolar differential amplifier
and emitter-follower output buffers as is shown in . Notice that the circuit
operates between ground and a negative voltage supply. Note also that the
switches are realized using p-channel transistors. The track-and-latch stage of
© K.W. Martin, 1997
17
S1
Vin
S3 φ1
S5
φ1
PositiveFeedback
Latch
φ1
S2
φ1
S4
φ1
Vout
S6 φ1
A simplified schematic of the comparator described in [Poujois, 1978]
[Razavi/92].
φ1
Vout-
Vout+
φ1
Vin+
Vinφ1
φ1
The BiCMOS preamplifier of [Razavi/92].
[Razavi/92] has both a bipolar latch and a CMOS latch as is shown in . During
the reset phase, φ 1 is low and φ 2 is high, X 1 and Y 1 are connected to ground
through switches M 1 and M 2, C 3 is discharged to the minus supply through M 11,
and X 2 and Y 2 are discharged to the minus supply through M 9 and M 10. Also, at
this time, M 3 and M 4 are off. Next, φ 1 goes high which leaves X 1 and Y 1 floating
and connects the inputs of the preamplifier to its input signal. After a short delay,
which is needed for the transient response of the preamplifier, φ 2 goes low, which
turns on M 12 thereby activating the positive feedback action of Q 5 and Q 6. This
develops a differential voltage between X 1 and Y 1 of about 200mv, since C 3 is
about 1/5 the size of C 1 and C 2. The offset of this bipolar latch is quite small,
typically on the order of one millivolt or less. Also, note that, when activated, the
© K.W. Martin, 1997
18
φ1
X1
M1 M2
φ1
Y1
Vin+
VinC1
C2
Q5
M12
Q6
M3
φ2
C3
M4
M5
M11
M6
X2
Y2
Vout+
Voutφ2
φ2
M9
M7
M8
M10
The BiCMOS track-and-latch stage of [Razavi/92].
only power dissipated is that required to charge C 3; there is no d.c. power
dissipation. A short time after the bipolar latch is activated, the inverter connected
to C 3 will change state and its output will go high. This turns on M 3 and M 4
which activates the CMOS part of the latch consisting of cross coupled M 5 and
M 6 and cross-coupled M 7 and M 8. The reason for including cross-coupled M 5 and
M 6 is to prevent nodes X 1 and Y 1 from being discharged very far from ground
towards the minus power supply while at the same time amplifying the 200mV
difference signal developed by the bipolar latch to almost a full-level CMOS
voltage change. Thus, the latch is accurate, relatively fast, and low power. Also
described in [Razavi/92] is an interesting CMOS only comparator which will not
be described here, but which interested readers might want to investigate.
© K.W. Martin, 1997
19
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