Receiver Architectures – Part 2
M. Renfors, TUT/DCE
TLT-5806/RxArch2/1
01.10.08
Receiver Architectures - Part 2
Increasing the role of DSP
in receiver front-ends
Markku Renfors
Department of Communications Engineering
Tampere University of Technology, Finland
markku.renfors@tut.fi
www.cs.tut.fi/tlt
Topics:
- Classification of DSP-Based Receiver Architectures
- Characteristics of Alternative Flexible Wideband
Receiver Architectures
- DSP for Flexible Receivers
- Digital Channel Selection & Down-Conversion
Techniques
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Receiver Architectures – Part 2
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Classification of DSP-Based Receiver
Architectures
Location of ADC (A/D-converter)
1. Baseband or low IF
2. IF
3. RF
Analog front-end bandwidth - ADC bandwidth
1. Single channel
2. Few channels
3. Frequency slice
4. Service band (e.g., GSM)
5. Frequency band (like 2 GHz range)
The bandwidths of the analog front-end and ADC may or
may not go hand in hand. Some examples below.
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Narrowband front-end
Per-channel down-conversion (0, or IF)
-
Selectivity in analog part, good IF filters needed.
"Normal" frequency sythesizer needed.
No big demands for ADC dynamic range or jitter.
Sampling rate requirements are such that it is enough
to attenuate aliasing to the desired band.
- Narrowband (baseband or bandpass) ADC (like ΣΔ)
can be utilized.
RF-stages
Mixer
IF-stages
BP/LP
filter
ADC
LO
fIF
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Wideband front-end, per-channel downconversion so that desired channel is around a
fixed center frequency (0 or IF)
- Analog front-end simplified in the sense that highly
selective IF filters are not needed.
- "Normal" frequency synthesizer needed.
- Selectivity in digital part, with fixed center frequency.
- High demands for ADC dynamic range and jitter.
- Sampling rate requirements are such that it is enough
to attenuate aliasing to the desired band.
- Narrowband ADC (like ΣΔ) can be utilized.
RF-stages
Mixer
IF-stages
BP/LP
filter
ADC
LO
fIF
BIF
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Wideband front-end, wideband (like slice or
service band) down-conversion so that desired
channel is located in a wider frequency range
- Analog front-end simplified in the sense that highly
selective IF filters are not needed.
- Single or few LO frequencies needed for each service
band -> simplified synthesizer; fast frequency hopping
becomes feasible.
- Selectivity in digital part, with tunable center
frequency.
- High demands for ADC dynamic range and jitter.
- Sampling rate requirements are such that no aliasing
into the whole band is allowed.
- Wideband ADC (or ΣΔ with tunable center
frequency!?) needed.
RF-stages
Mixer
IF-stages
BP
filter
ADC
LO
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BIF
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About the Choice Between Lowpass and
Bandpass Sampling
Due to the I/Q gain and phase imbalance problems in
practical analog circuitry, the wideband downconversion wideband sampling approach is very difficult to implement
at 0 (or low) IF. But utilizing a combination of different
techniques for mitigating these effects, the mentioned
approach is becoming feasible, but mostly on the basestation side.
On the other hand, wideband IF sampling is very
challenging due to the apperture jitter and other
implementation problems concerning the sampling
circuitry (usually track&hold).
The ADC requirements (apart from the sampling process)
concern mainly the spurious-free dynamic range, and are
not so heavily depending on the choice between lowpass
or IF sampling.
However, the useful ADC bandwidth has a great impact,
e.g., on power consumption. So the cost/complexity
metrics for per-channel A/D-conversion (usually ΣΔ) and
multichannel A/D-conversion (usually something else than
ΣΔ) are quite different.
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Some Dependencies and Conclusions
Considering sampling and A/D-conversion
• highest signal frequency determines the T/H
bandwidth and jitter requirements
• signal bandwidth (after analog RF/IF/baseband
filtering) determines the minimum sampling rate
Increasing the degree of bandpass subsampling
( f c / f s ) leads to
• lower sampling rate
• more selectivity needed before sampling
• more noise aliasing => more gain needed before
sampling
• lower processing gain -> more bits from ADC &
tighter jitter requirements
Implementing the receiver selectivity in DSP-part
leads to
• simplified analog part
• hard requirements for the T/H and ADC dynamic
range
Wideband sampling
• has been mostly considered at IF due to I/Qimbalance problems; direct conversion/low-IF
becoming feasible, depending on system specs
Using IF sampling
• sets hard requirements for the T/H circuitry and jitter
of the sampling clock.
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Connection to Advanced Broadband
Wireless System Developments
The latest and future wireless communication systems
use increasing bandwidths for data transmission. For
example, 3GPP-LTE and WiMAX have the maximum
bandwidth of 20 MHz, and the next generation (“IMTadvance”) is targeted to bandwidths of up to 100 MHz.
Especially, LTE is using frequency-division duplexing, and
the spectrum entering the receiver resembles that of a
multichannel receiver for more narrowband systems.
Some characteristics and comments:
- The wide bandwidth makes it possible to utilize fast
frequency hopping and other forms of frequency diversity,
to enhance the transmitted data rate.
- In LTE (and other similar systems) the power levels of the
frequency slots of different users are well-controlled (e.g.,
20 dB maximum variation in the power levels). This is in
contrast to, e.g., multichannel GSM receiver, were the
dynamic range is much bigger. This makes it feasible to
implement the needed wideband receivers for such
systems.
- Direct conversion architecture is preferred. Actually, for
most of the frequency channels, the low-IF model is valid.
- IQ-imbalance is significant, but not very critical because
of the well-controlled power levels. DSP-based IQimbalance compensation is interesting in case of highorder modulations.
- In these systems, and in OFDM systems in general, the
frequencies at or close to DC in baseband processing are
commonly not utilized in order to make direct conversion
receiver design easier.
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About Direct Sampling Architecture
In high-performance systems, it is necessary to have
some selectivity and gain before sampling. The reasons
are
• signal aliasing
• noise aliasing
Sampling is inherently more noisy operation than mixing!
Sampling directly from the antenna signal is usually not
adequate.
The Ultimate SW Radio Architecture
Antenna
a bank of RF filters
and LNA’s for different
frequency bands
T/H
A/D
DSP
The needed technologies are not mature for
challenging radio system specifications in the
frequency bands used in mobile systems!
However, direct sampling is already an interesting
architecture in various applications
o For example, satellite-based positioning
(GPS/Galileo) where the dynamic range requirements
are greatly reduced comparing with wireless
communications.
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Direct Sampling & Analog Discrete-Time
Processing
Texas Instruments (TI) has introduced so-called digital
radio processor (DRP) concept that is based on direct
sampling, together with analog discrete-time processing to
implement main part of the channel selectivity, downconversion, and sampling rate reduction.
o For example, CIC/running-sum filters can be
implemented with switched-capacitor techniques with
analog processing.
o Then the ADC is operating at relatively low rate and
has reduced dynamic range requirements compared
to digital direct-sampling approach.
TI is marketing DRP-based transceiver chips for GPS,
Bluetooth, and GSM/GPRS, i.e., for systems with
relatively narrow bandwidth or reduced dynamic range,
together with low-order modulation.
In such architectures, also the sampling process may be
designed to provide frequency selectivity. Then the idea of
the sampling process is not anymore just taking
instantaneous sample values, but to
- Integrate the signal over a finite-length interval
- Weighting the input signal by a proper window
during the integration interval. Rectangular window
results in sinc-response, other kind of windows can
be designed for optimized performance.
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Multimode Receivers
In flexible multi-mode receivers, the target is to use
common blocks for different systems as much as
possible.
A long-term target is to make the transceiver configurable
for any system. However, presently a combination of a
few predetermined systems is more realistic, e.g.,
GSM/WCDMA/WLAN.
A realistic approach has the following elements:
- Separate RF stages for different systems.
- Common IF/baseband analog parts; bandwidth
according to the most wideband system.
- Common ADC at IF or baseband; fixed sampling rate.
- Especially in the terminal side: careful choice of IF
frequency & sampling rate to make the downconversion simple. Typically, fIF=(2k+1) fs/4.
- Digital channel selection filtering optimized for the
different systems.
I
LNA
IF1
filter
AGC
DSP
S&H
0,1,0,-1
ADC
IF2
LO
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Q
DSP
1,0,-1,0
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Rephrasing Critical Issues in Modern Receiver
Architectures:
SWOT Analysis on Flexible Receiver
Architectures with Wideband Analog
Front-End
Alternatives:
1. Multimode direct-conversion receiver
2. Multimode low IF receiver
3. Multimode IF-sampling receiver
4. Wideband IF sampling architecture
5. Wideband direct-conversion/low-IF architecture
6. Direct-sampling architecture
Common features for 1-3:
• Analog & A/D bandwidth according to the widest
channel bandwidth
Common features for 4 and 5:
• Tunable digital channel selection and down-conversion
• Interesting mostly for base-station applications
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1. Multimode direct-conversion receiver
Strengths
- Simple analog part
- Sampling jitter not critical
- Narrowband A/D-conversion can be used
Weaknesses
- DC-offset problems, especially difficult to handle in
flexible receiver
- 2nd-order intermodulation -> bigger demands for the
linearity of the analog parts
Oportunities
- Fast and flexible DC-offset compensation techniques,
facilitated by high resolution A/D-conversion techniques.
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2. Multimode low IF receiver
Strengths
-
Rather simple analog part
Sampling jitter not critical
Narrowband A/D-conversion can be used
DC-problems avoided
Weaknesses
- 2nd-order intermodulation -> bigger demands for the
linearity of the analog parts
- Higher demands for I/Q balance
- Multimode concept not very clear (different low-IF's for
different systems, or very hard demands for I/Q
balance)
Oportunities
- Adaptive I/Q imbalance compensation can be used to
loosen the requirements of the analog part.
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3. Multimode IF-sampling receiver
Strengths
- Well-known architecture, high-quality analog RF
possible
- 2nd-order intermodulation not a problem
- Narrowband A/D-conversion can be used
- DC-problems avoided
Weaknesses
- Challenging demands for sampling jitter and linearity
- IF filter difficult to integrate
Oportunities
- New technologies for flexible IF/RF filter implementation
(e.g., MEMS)
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4. Wideband IF sampling architecture
Strengths
-
Reduced IF filtering requirements
Simplified frequency synthesizer
Possibility to use common blocks for multiple channels
Facilitates fast frequency hopping/channel switching
DC-problems avoided
Weaknesses
- Very challenging demands for sampling jitter and
linearity
- Wideband A/D-conversion needed
- 2nd-order intermodulation may be a problem
- Lot of DSP power needed
- High power consumption
Oportunities
- Advances in ADC technologies and DSP HW
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5. Wideband direct-conversion/low-IF
architecture
Strengths
-
Simplified frequency synthesizer
Possibility to use common blocks for multiple channels
Facilitates fast frequency hopping/channel switching
Rather simple analog part
Sampling jitter not critical
Weaknesses
- Hard demands for I/Q balance
- Multimode concept not very clear (avoiding DC-offset
problems in all different systems)
- Wideband A/D-conversion needed
- 2nd-order intermodulation -> bigger demands for the
linearity of the analog parts
- High power consumption
Oportunities
- Adaptive I/Q imbalance compensation can be used to
loosen the requirements of the analog part.
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6. Direct-sampling receiver
Strengths
- Simplest possible analog part
- Highly flexible for multi-standard receivers.
Weaknesses
- Very hard jitter requirements.
- Currently not feasible for demanding system specs or
high-order modulation.
Oportunities
- Novel ideas for sampling and ADCs
- Analog discrete-time processing techniques.
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Case Study on Wideband IF Sampling in
GSM Receivers*
• Introduction
• Specifications and Selectivity Requirements for GSM
• Sampling and Quantization Requirements as
Functions of Analog Filter Bandwidth
• Requirements for Digital Filtering
* This part is based on the diploma thesis work of Juho
Pirskanen carried out at TUT/ICE during years 1999-2000.
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GSM Case: Introduction
Today’s receivers (like GSM) use narrowband ADconversion
– When only one system is to be implemented, this
is not a problem
– However, when several systems with different
bandwidths are desired to be used, we have the
choices
⇒ Several different analog front-ends in the
receiver
OR
⇒ Wideband analog front-end and ADconversion
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GSM Case: Wideband Receiver
Receiver with wideband front-end and wideband ADconversion
– Analog front-end can be simplified
– One AD-converter can be used for different
systems
– Performance requirements of the ADC are
increased
Channelization filtering must be done in digital domain to
obtain desired system characteristics
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GSM Case: Interference Mask
• Obtained from the GSM specifications
• Includes interference signals from
– Adjacent channel
– Out of band blocking
– Intermodulation test
GSM Interferer Mask
−20
−30
−40
Signal Power [dBm]
−50
−60
−70
−80
−90
← Desired Signal Level for the Blocking Test
← Reference Sensitivity Level
−100
−110
−120
−5000
−4000
−3000
−2000
−1000
0
1000
2000
3000
Frequency Offset from the Carrier Frequency [kHz]
–
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4000
5000
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GSM Case: Attenuation Requirement
• Attenuation requirements for GSM can be found by
As ( f ) = PI ( f ) − ( Psign − C / I c − Am )
•
•
•
•
PI is the interference signal
Psign is the desired signal
C/Ic is the carrier to interference ratio
Am is the extra noise margin
Channelization Filtering for GSM
0
−10
Magnitude Response [dB]
−20
−30
−40
−50
−60
−70
−80
−90
−5000
−4000
−3000
−2000
−1000
0
1000
2000
3000
Frequency Offset from the Carrier Frequency [kHz]
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4000
5000
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GSM Case: ADC Dynamic Requirements
ADC dynamic range requirement can be calculated as
SNRdynamic = max { As ( f ) + H ( f )}
f
• As is the attenuation requirement
• H(f) is the amplitude response of the analog filter
Fourth-order Chebyshev type two filters :
GSM Specifications and some 4th Order Bandpass Chebyshev Filters
0
−10
Magnitude Response [dB]
−20
−30
−40
−50
−60
−70
−80
−90
0
500
1000
1500
2000
2500
3000
3500
4000
4500
5000
Frequency Offset from the Carrier frequency [kHz]
The red squares mark the critical points where the
dynamic range requirement is maximized for each filter
bandwidth.
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GSM Case: ADC Dynamic Requirements
• By combining equations, the number of bits can be
found by
⎡
⎛ fs
⎞⎤
−
−
1.76
10log
SNR
⎜
dynamic
10
⎢
2 B ⎟⎠ ⎥
⎝
b=⎢
⎥
6.02
⎢
⎥
⎢
⎥
• Used sampling rates
– Multiples of GSM symbol rate 17.33 MHz, 34.66
MHz and 69.33 MHz
• Studied filter types
– Butterworth and Chebyshev type two filters
• Used filter orders
– Fourth and sixth order filters
• Filter bandwidth
– From 100 kHz to 2.5 MHz
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GSM Case: Number of Bits Required in ADC
AD−conventers Bits as a Function of Filter Bandwidth. Fs = 92.16MHz
Fourth-order
Butterworth filters:
Bits used in AD−converter
14
12
10
8
6
4
2
500
1000
1500
2000
2500
3000
3500
4000
4500
5000
500
1000
1500
2000
2500
3000
3500
4000
4500
5000
500
1000
1500
2000
2500
3000
3500
4000
4500
5000
AD−conventers Bits as a Function of Filter Bandwidth. Fs = 69.333MHz
14
12
10
8
6
4
2
AD−conventers Bits as a Function of Filter Bandwidth. Fs = 34.6666MHz
14
12
10
8
6
4
2
Filters bandwidth [kHz]
AD−conventers Bits as a Function of Filter Bandwidth. Fs = 92.16MHz
Bits used in AD−converter
Sixth-order
Chebyshev
type two
filters:
14
12
10
8
6
4
2
500
1000
1500
2000
2500
3000
3500
4000
4500
5000
500
1000
1500
2000
2500
3000
3500
4000
4500
5000
500
1000
1500
2000
2500
3000
3500
4000
4500
5000
AD−conventers Bits as a Function of Filter Bandwidth. Fs = 69.333MHz
14
12
10
8
6
4
2
AD−conventers Bits as a Function of Filter Bandwidth. Fs = 34.6666MHz
14
12
10
8
6
4
2
Filters bandwidth [kHz]
Notice that in practice the minimum number of bits is
higher than the lowest values indicated here, in order to
be able to carry out the channel equalization properly.
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GSM Case: Jitter Noise
The maximum signal power to be sampled is:
PADC = max { PI ( f ) + H ( f ) }
f
Using the standard white-noise model for the jitter effects,
the maximum allowed standard deviation of the timing
error is given by:
Fs
TA =
⋅ ⎛⎜ Psig − C − Am ⎞⎟
Ic
2B ⎝
⎠
2
PADC
4π 2 f max
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GSM Case: Jitter Requirements for fIF=156 MHz
The timing jitter requirements when using fourth-order
Butterworth filters:
Maximum Allowable Standart Deviation of The Timing Jitter
3
10
Fs=69.333 MHz
Fs=36.7 MHz
Fs=17.8 MHz
Standard Deviaton of Jitter [ps]
2
10
1
10
0
10
−1
10
0
500
1000
1500
2000
2500
3000
3500
4000
4500
5000
Filters Bandwidth [kHz]
The timing jitter requirements when using sixth-order
Chebyshev type two filters:
Maximum Allowable Standart Deviation of The Timing Jitter
3
10
Fs=69.333MHz
Fs=36.7MHz
Fs=17.8MHz
Standard Deviaton of Jitter [ps]
2
10
1
10
0
10
−1
10
0
500
1000
1500
2000
2500
3000
Filters Bandwidth [kHz]
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3500
4000
4500
5000
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GSM Case: Digital Filtering Requirements
Channelization and noise filtering requirements for DSP in
the GSM case.
• Sixth order Chebyshev type two analog filter
• Second order Sigma-delta modulator with 2
quantization bits
Attenuation Requirements for Noise Filtering and Interfering Channels
0
−10
Stopband Attenuation[dB]
−20
−30
↑ RF−Attenuation Requirements
−40
−50
−60
↑ Attenuation Requirements for Noise Power
at the Multiples of the Signal Band 2B
−70
↑ Attenuation Requirements
for Total Quantization Noise Power
−80
−90
0
0.5
1
1.5
2
2.5
3
Frequency [kHz]
4
x 10
• The total decimation factor can be divided to several
stages, e.g., 256 = 64 * 2*2
• First stage can be implemented by using CIC-filters
– Simple structure, no multipliers
– Good attenuation for aliasing signal bands
Filtering Requirements and CIC Decimation Filter
0
Magnitude Response [dB]
−20
−40
−60
−80
−100
0
0.5
1
1.5
2
2.5
3
3.5
Frequency Offset from Carrier Frequency [kHz]
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4
4.5
4
x 10
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GSM Case: Conclusions
• Dynamic requirement of the ADC
– Highly effected by the analog filter bandwidth
– Analog filter order and type has only one bit effect
on ADC requirement (together 2 bits in some
cases)
• Standard deviation of timing jitter
– Highly effected by the analog filter bandwidth and
used IF frequency (IF sampling)
– Analog filter order and type has only slight effect
• When considering GSM/WCDMA receivers
– The analog bandwidth should be about 2 MHz
– Fractional decimation has to be done
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DSP for Flexible Receivers
In advanced SW radio concepts, the selectivity filtering
and down-conversion are moved from analog continuoustime part to the discrete-time/DSP part.
=> Here efficient multirate filtering techniques
become very important.
It also helps to move as much as possible functionality
from the analog or digital front-end to baseband
processing.
=> All-digital synchronization concept becomes very
interesting in this context.
Some errors due to RF-front-end can be corrected by
DSP. Example: Adaptive I/Q imbalance compensation.
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All-Digital Synchronisation Concept
• Free-running local oscillators for demodulation and
frequency conversion.
• Free-running sampling clock.
• Errors are compensated in digital part.
=> All synchronisation functions can be
implemented using digital techniques
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Digital Channel Selection & Down-Conversion
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Digital Channel Selection & Down-Conversion
Digital Down-Conversion
1. Desired channel centered at fixed IF
=> Fixed down-conversion
Special choices of fIF and fs make things easy.
Especially when fIF=(2k+1) fs/4, the signal aliases to fs/4 and
down-conversion is very easy.
2. Wideband sampling case
=> Tunable down-conversion and NCO (numerically
controlled oscillator) needed.
3. Stepwise mixing and decimation
=> Tunable digital down-conversion is possible also without
NCO, as demonstrated in the later example. However, it is
not easy to find sufficiently efficient and flexible schemes.
Channel Selection Filtering
- After down-conversion, efficient lowpass decimator structure
is needed.
- CIC-filters are commonly used in the first decimation stages,
FIR-filters and the last stages. Nth-band IIR filters also an
efficient solution.
Adjusting Symbol Rates
- Different systems use different symbol/chip rates.
- Common sampling clock frequency is preferred.
=> Decimaton by a fractional factor is needed.
- This can be done at baseband or earlier in the decimation
chain.
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CIC-Filters
z-1
z-1
↓32
z-1
z-1
CIC = Cascaded Integrator - Comb
Transfer function:
⎛1 − z −R ⎞
⎟
H (z ) = ⎜
⎜ 1 − z −1 ⎟
⎝
⎠
N
⎞⎞
jπN ( R −1) f ⎛⎜ sin ⎛⎜ π Rf
⎛ j 2πf ⎞
Fs ⎟⎠ ⎟
⎜
Fs ⎟
Fs ⎜
⎝
⎟
=e
H⎜e
⎟
⎜
⎟
⎜⎜ R sin ⎛⎜ π f ⎞⎟ ⎟⎟
⎝
⎠
Fs ⎠ ⎠
⎝
⎝
Frequency response:
N
Here R is the decimation factor and N is the order of the
CIC-filter.
A first-order CIC-filter takes the avarage of R consequtive
input samples and decimates by R. It is also called moving
average or running sum filter.
It is important to use modulo arithmetic (like 2's
complement) in the implementation, because there will be
inevitable internal overflows.
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CIC-Filters
In CIC filter, those frequencies aliasing to 0-frequency are
heavily attenuated. For a relatively narrowband signal,
low-order CIC-filters are sufficient; more wideband signals
neede higher CIC-filter orders
Example (for a GSM application): N=2, R=32.
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NCO-Based Arbitrary Digital DownConversion
Dedicated processors implementing the following kind of
down-conversion and channel selection structure are
available for several vendors (like Harris).
Sampling rates in the 50 ... 100 MHz range are possible.
However, the power consumption is still too high for
terminal applications.
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Example
Using Harris HSP50214 for GSM channel selection
filtering.
- Input sample rate: 39 MHz
- CIC-filter: decimation by 18, order=5
- Two pre-designed FIR half-band filters are used for
the next decimation stages.
- The final filter stage is an FIR design.
- Output sample rate: 541.667 kHz
Frequency responses of the filter stages:
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Example (continued)
Overall frequency response and the effects of different
stages:
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Stepwise Decimation and Mixing Approach
With suitable choice of the key parameters (IF frequency,
channel spacing, sampling rate) it is possible to do
adjustable down-conversion also without NCO, just by
using the frequency translations of multirate DSP.
In the following, a special bandpass decimator structure is
described, which gives some more flexibility in this kind of
solutions.
The idea is to do stepwise down-conversion, with
decimation by 2 in each stage. Three different types of
stages are used:
1. Lowpass decimation when the desired signal is at the
lower frequencies.
2. Highpass decimation when the desired signal is at the
higher frequencies.
3. The special bandpass decimator when the desired
signal is in the mid-frequencies.
Note: This example should be taken as an example of the
possibilities of complex signal processing in specific designs, but
not as a generic technique for SDR.
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Bandpass Decimator
The structure includes:
- down-conversion by fs/8
- bandpass filtering
- decimation by 2
Complex filtering is needed in the basic model, but the
structure can be optimized to an efficient form, where
complex signal processing is not needed.
Basic model:
e-jπk/4
x
Magnitude Response
H4(ze-jπ/2)
Re[]
2
H4(ze-jπ/2)
π/2
π/4
3π/4
π
Magnitude Response
Angular Frequency
π/4reserved.
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π/2
3π/4
π
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Bandpass Decimator (continued)
Optimized form:
A1(z)
1,1,-1,-1,1,1,-1
+
A0(z)
A3(z)
-
-
x
+
A2(z)
- This is completely equivalent to the original form.
- No complex signal processing actually needed.
- All filtering operations running at quarter of the sampling
rate.
- Computational complexity roughly the same as for halfband decimators with the same selectivity.
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Basic Building Blocks for the SDM Approach
Magnitude responses of H2(z) and H2(-z)
Magnitude [dB]
0
-20
-40
-60
-80
-100
0
0.1
0.2
0.4
0.5
0.6
0.7
Normalized Frequency
Magnitude response of H4(ze-jπ/2)
0.8
0.9
1
0
0.1
0.2
0.3
0.8
0.9
1
Magnitude [dB]
0
0.3
-20
-40
-60
-80
-100
0.4
0.5
0.6
Normalized Frequency
A (z)
0
A (z)
1
0.7
+
LP out
- +
HP out
A1(z)
1,1,-1,-1,1,1,-1
+
A0(z)
A3(z)
A2(z)
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-
-
+
x
BP out