Performance of CMOS Ring Oscillator
K. B. K. Teo, Churchill College, Email: kbkt2@eng.cam.ac.uk
Abstract
This experiment investigates various methods of determining the delay in CMOS
gates. Direct measurement, ring oscillator and simulation methods are used and
compared. A stroboscopic pulse generator was also examined during the experiment.
Finally, the effects of supply voltage and output load on gate delay were examined.
1.
The output driver probably introduces the most
delay/error in the measurement as it has to drive the
output pin, coax cabling and oscilloscope input. All
these external factors make up a considerable load
which increases the delay in the output. Thus, the gate
delay measurement is limited by the output
loading/buffer and will be much greater than the actual
NOR gate
device
Square
wavedelay.
Introduction
Custom designed ring oscillator CMOS IC’s were
used in this experiment to determine gate delays under
various conditions. A schematic of one of these IC’s is
shown in Figure 1. This IC contains 2 ring oscillators
with 113 and 115 gates respectively. The input and
output pads of the IC also contain inverting
buffers/drivers which are not shown on this schematic.
input (pin 39)
Output (pin 5)
LOW Input (pin 3)
2.
Single Device Gate Delay Using an Oscilloscope
3V
The gate delay of a single device is first
determined by injecting a 1MHz square wave into the
input of the single NOR gate and observing the output
waveform. The second input of the NOR gate was held
low. The serial number of the chip used was “21-19”
and the power supply of the chip was set at 3V. This
produced an inverting output as shown in Figure 2.
Square wave input
1MHz, 3V p-p
0V
3V
Output is inverted
1MHz, 3V p-p
0V
Dual trace oscilloscope
Input trace
To measure the delay, the
time scale was expanded
and both traces were superimposed. The delay was
determined between the
midpoints of both traces.
3V
A gate delay of 50ns was measured by expanding
the oscilloscope time scale and measuring the time
between the midpoints of the rising/falling waveforms.
0V
Output trace is
inverted using
oscilloscope for
measurement
This direct method of determining gate delay can
Dual trace oscilloscope
be misleading and erroneous. This IC contains input
and output inverting buffers. And so we are in fact
Figure 2: Measuring the gate delay directly
measuring the total delay of 3 gates - the input buffer,
4
the NOR gate under test, and the output driver inverter.
Ring oscillator 113 gates
6
7
3
4
8
÷2
3
39
Single NOR
gate
Pulse generator
5
9
Pulse generator
4
Inputs to NOR
gates to control
ring oscillation
3
10
Ring oscillator 115 gates
Figure 1: Schematic of a ring oscillator IC
1
39
3.
measured between these gates, the gate delay per stage
is (0.1µs÷37) = 2.7ns. This corresponds well to the
gate delay obtained using the period of the ring
oscillator.
Testing the Ring Oscillator
In order to overcome the errors of direct
measurement, the ring oscillator is used. Using inputs
3 or 39 to the control NOR gates on the 115-gate ring
oscillator (see Figure 1), it is possible to start and stop
the ring oscillator.
Likewise, we could consider a waveform
emerging from output 7 before output 6, and there are
76 intervening gates between these outputs. For a total
delay of 0.175µs measured between these outputs, the
gate delay per stage is (0.175µs÷76) = 2.3ns. This also
corresponds well to the gate delay obtained using the
period of the ring oscillator.
With a ‘high’ input into either control NOR gate
(inputs 3 or 39), the output of the control NOR gate
will always be low. Thus, the ring cannot oscillate.
However, when a low is input into the control
NOR gates, the NOR gate will be able to transmit and
invert the signal from the previous stage, hence
allowing the ring to ‘run freely’ and oscillate.
The ring oscillator provides the most accurate
means of determining the gate delay. Unlike measuring
the gate delay directly as described in section 2, the
period of the ring oscillator is independent of the
output loading due to the oscilloscope/frequency
counter. The loading of the output buffer merely
introduces a phase shift to the entire oscillating
waveform, but does not alter its period.
To demonstrate how the ring can be ‘gated’ on and
off, a square wave of 100kHz is fed into the control
NOR gate, with the other control NOR gate set on low
(free-run). Whenever the square wave inputs a ‘low’
into the control NOR gate, the ring oscillates, as
illustrated in Figure 3.
3V
Furthermore, by using many series devices in the
ring to increase the oscillation period, we are able to
determine the delays of devices which are much faster
than the speed of our measurement system. The use of
many devices also averages out manufacturing
differences between the devices.
Input 39 - square wave
100kHz, 3V p-p
0V
3V
0V
Dual trace oscilloscope
(NB. Both traces have been inverted
on the display to compensate
for the inverting input and
output buffers on the IC.)
Output 10 - oscillations will
occur whenever the control
NOR gate is driven low via
input 39.
5.
Using a single ring oscillator, the power supply
voltage was varied from 1V to 6V and the frequency of
oscillation was measured. Below ~0.6V, we were
unable to obtain full amplitude oscillations from the
ring. The results are presented in Figure 4.
Figure 3: Gating the ring oscillator on and off
Determining the Gate Delay Using the Ring
Oscillator
Ring Oscillation
Frequency (Mhz)
4.
The 115-element ring was set oscillating and the
period of oscillation was measured to be about 0.5µs
using the oscilloscope. The accuracy of the period
measurement is limited to the shortest oscilloscope
timescale available and the grid markings on the
oscilloscope screen. Using the frequency counter, the
period of oscillation can be determined with greater
precision and it was measured to be 0.540µs.
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
Average gate delay (ns)
1
In one oscillation period, the signal is cycled low
and high. Thus, the signal has actually travelled twice
around the ring within one period. Hence, it is
necessary to divide the oscillation period by 2 when
determining the gate delay of each gate in the ring. The
gate delay of each gate in the ring is calculated to be:
gate delay =
Effect of Power Supply Voltage
2
3
4
5
2
3
4
5
100
10
1
0
1
6
Supply voltage (V)
oscillation period 0.54µs
=
= 2.3ns
no of gates × 2
115 × 2
Figure 4: Effect of supply voltage on oscillation
frequency and gate delay
With a higher supply voltage, each transistor
experiences a higher input gate voltage, which in turn
produces more output drain current (due to MOS
device gain β) to drive the capacitative gates of the
transistors in the next stage.
The gate delay can also be obtained by measuring
the delay between different outputs in the ring. If we
consider a waveform emerging from output 6 before
output 7 (as in Figure 1), there are 37 intervening gates
between the outputs. For a total delay of 0.1µs
2
The rise time (tr) and fall time (tf), from which
gate delay is determined, are approximated as [1]:
CL
β p VDD
CL
tf ≈ k ×
β n VDD
tr ≈ k ×
Thus, with greater gain, more current can be
supplied to charge the capacitative gate of the next
stage, allowing the devices to switch quicker (see Eqn
1). This threefold increase in p-channel width however
does not result in a threefold increase in circuit speed.
This is because the widening the p-channel devices
only improves/decreases the rise-time. The fall-times,
determined by n-channel devices, are not improved.
(Eqn 1)
(Eqn 2)
Where CL is the capacitative loading of the
output/next stage,
β is the MOS transistor gain factor for p
and n-channel devices, and,
VDD is the supply voltage.
Moreover, because of the wider gates in the pchannel devices, the capacitative gate load of the next
stage is increased which cancels some of the speed
gains obtained from a higher β. Thus, only a 24%
increase in performance is observed.
Increasing VDD will decrease the delay times. This
increases the frequency of oscillation linearly because
frequency α 1/gate delay.
Larger devices also reduce the density of devices
on an IC.
7.
However, as VDD is increased, the power
consumption of the circuit is also raised and this can
lead to IC failure due to excessive heat dissipation and
electromigration (high current density in metal lines).
In reality, the CMOS designer has to make a
compromise between circuit performance and power
consumption.
6.
The circuit shown in Figure 5 was simulated using
AccuSim using transistors of similar dimensions to chip
“28-46”. The input waveform (A) consists of a linear
ramp from 0 to 5V, a flat region and a linear ramp back
down to 0V.
A
Performance Comparison with Transistors of
Different Dimensions
Gate used in
chip design 28
A second ring oscillator IC (chip “28-46”),
designed with p-channel transistors 3 times wider than
those in the first ring oscillator (chip “21-19”), was
investigated. The frequency of oscillation and gate
delay of this IC compared with the original ring
oscillator IC are presented in the following table.
@ ~3V
Ring period
Ring frequency
Gate delay
Chip 21-19
0.566 µs
1.77 MHz
2.5 ns
Simulation of Device Performance
B
C
D
E
F
Chip 28-46
0.426 µs
2.35 MHz
1.9 ns
Table 1: Comparing IC’s with transistors of different
dimensions.
Chip design “28-46”, with wider p-channel
devices, is 24% faster when compared with chip design
“21-19”. By increasing the width (W) of the p-channel
devices by 3, the gain (βp) of the devices is also
increased threefold, as [2]:
βp =
µpε  W 
 
t ox  L 
Figure 5: AccuSim simulation of a 3-gate
pulse generator
The input pulse (A) is delayed and sequentially
inverted as it passes through the 4 series NOR gates,
which gives rise to waveforms B to E. The waveforms
B-E are different in shape to the original linear ramp.
This is because the simulator has taken into account
the drain conductance and the capacitance loading of
the gates in the next stage. And thus, waveforms B-E
exhibit similar gradual ‘charging’ ramps expected from
driving capacitative loads. It also appears that there is
some ringing/voltage overshoot at the start of each
waveform which could be due to some inductance.
(Eqn 3)
Where βp is the MOS transistor gain factor for
p-channel devices,
µp is the mobility of holes in the channel,
ε is the permittivity of the gate
insulator,
tox is the thickness of the gate insulator,
W is the width of the device, and
L is the channel length.
When both B and E are low, a high pulse is
produced at F.
3
Ring oscillator (113 gates)
From Figure 5, we can determine the simulated
gate delay per stage. 1ns is measured between the
midpoints of the transitions of the highlighted
waveforms C and E (going through 2 gates). The
average gate delay is 1ns ÷ 2 gates = 0.5ns.
7
8
÷2
Pulse generator
9
Pulse generator
We also determined the gate delay of chip “28-19”
using its 115 element ring oscillator running at 5V for
comparison with the simulated results. The period of
oscillation was 233ns, which gives us a gate delay of
(233/(115x2)) = 1ns per stage.
10
Ring oscillator (115 gates)
(From Figure 1)
NB. If both rings are running, a pulse is only observed
at output 9 when pulses from both rings arrive at the
final NOR gate simultaneously.
The simulation produced a gate delay which was
half the value obtained through experiment. This is
because the simulation did not take into account the
resistance of the polysilicon lines which connected the
various stages. This line resistance (RL) increases the
gate delay since the charging time of the capacitance
(CL) of the next stage depends on the RLCL time
constant.
Figure 7: Pulses when both rings are oscillating
8.
Oscilloscope
(NB. All traces have been inverted
on the display to compensate
for the inverting output buffers
on the IC.)
t1
t2
A pulse generator is also present in our ring
oscillator as shown in Figure 6. During each oscillation
of the ring, there will only be a short instance when
both the inputs (A and B) to the pulse generator NOR
gate are low. This instance spans the delay of 5 gates
and produces a short pulse at the output (C). This was
observed experimentally with one ring oscillating at a
supply voltage of 0.7V.
Output 8 - divide by 2 circuit,
period (t 3 ) = 6ms
Figure 8: Various outputs with one ring oscillating
at 0.7V supply (chip design 28-46)
From Figure 8, the average gate delay calculated
from output 10 (ring oscillation) is 3ms÷(115×2) =
13µ
µs. Assuming the pulses from output 9 are generated
from 5 gate delays, the gate average gate delay can
also be calculated by 0.275ms÷5 = 55µ
µs. This is 4
times the average gate delay obtained using the ring
oscillation. The increased delay is probably due to the
output loading of the pulse circuit (which cannot drive
the output effectively due to the low supply voltage
~0.7V).
Pulse generator
B
Output 9 - pulsed output,
pulse width (t 2 ) = 0.275ms
t3
Stroboscopic Pulse Generator
C
Output 10 - ring oscillation,
period (t 1 ) = 3ms
A
(From Figure 1)
A - oscillating waveform
As the supply voltage was increased, the gate
delay and pulse width decreased until the pulse was too
short to be observed on the oscilloscope (at ~1V
supply).
B - oscillating waveform,
inverted and delayed
by 5 gates.
C - pulses from the NOR gate
only when both A and B
are low, which occurs
once per oscillation.
9.
Figure 6: Generating pulses from the ring oscillator
Ring Oscillators with Realistic Loads on the
Devices in the ring
Ring oscillators consisting of devices with
different loads were tested at a fixed supply voltage
(5V). Figure 9, on the next page, shows how the gate
delay is affected by device loading for an inverter
(NOT) ring oscillator and a NAND ring oscillator.
In our IC, both ring oscillators have pulse
generators (see Figure 7). The outputs of both pulse
generators are inverted, and fed into another NOR
gate. The output of this final NOR gate will only be
high when both its inputs are low. As both rings are
oscillating asynchronously, low pulses from both
oscillators will only intermittently arrive at the NOR
gate simultaneously. Hence, with both rings
oscillating, we can only intermittently see a pulse at
output 9. This was observed experimentally using a
supply voltage of 0.7V.
The gate delay linearly increases with the number
of loads on each gate. This implies that in complex
logic circuits where gates have different loading, the
delay will depend on the loading of each gate. The
gate with the most load/delay would determine the
fastest speed that the logic could operate at.
Manufacturers of IC’s would specify in their
datasheets the maximum time delay before data is
valid on the output pins of an IC for a specific load.
With one ring oscillating, the operation of the
edge triggered divide by 2 circuit (“÷2” in Figure 7)
was also verified. This is illustrated in Figure 8.
4
Average gate delay (ns)
AccuSim’s simulated gate delays were found to be
half the value observed on the real device because the
simulation failed to account for the resistance of the
polysilicon interconnects in the IC.
1.2
1
0.8
0.6
We also verified the operation of the pulse
generator and divide by 2 circuits incorporated in the
ring oscillator IC.
0.4
Inverter ring
oscillator
0.2
0
0
1
2
3
4
5
The effect of output loading on gate delay was
also investigated. We found that the gate delay
increased linearly with the number of loads on each
gate.
Average gate delay (ns)
Gate load
1.6
1.4
1.2
1
0.8
0.6
0.4
References
NAND ring
oscillator
0.2
0
0
1
2
3
4
1. Weste, N. H. E. and Eshraghanm K., “Principles of
CMOS VLSI Design: A Systems Perspective”, 2nd
edition, Addison-Wesley, 1993, page 208-213.
5
Gate load
Figure 9: Effect of output loading on gate delay
2. Ibid, page 52.
Finally, the effect of supply voltage on the
performance of the inverter (single load) ring oscillator
was determined (Figure 10). The gate delays obtained
for the inverter were less than the gate delays for the
NOR gate. This is because the inverter, a 2 transistor
gate, is a simpler device with less interconnects
(smaller RL) and gate capacitance (smaller CL) per
stage than the 2-input NOR gate (4 transistors).
Ring oscillation
frequency (MHz)
7
6
5
4
3
2
1
Inverter
ring oscillation
Average gate delay (ns)
0
10
NOR gate delay,
chip “21-19”
1
Inverter
gate delay
0.1
0
1
2
3
4
5
Supply voltage (V)
Figure 10: Effect of voltage on oscillation frequency
and gate delay for the singly loaded inverter ring.
The delay of NOR gates in chip “21-19” is plotted
for comparison.
10. Conclusions
The ring oscillator provides the most accurate
means of determining the average gate delay. As its
supply voltage was increased, the gate delay decreased
and the ring oscillation frequency increased linearly.
We also found that the performance of a gate can
be sightly improved by increasing the width of its pchannel devices. This however results in larger gates
and smaller gate density on the IC.
5