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IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 11, NO. 5, SEPTEMBER 2012
Device Design Engineering for Optimum Analog/RF
Performance of Nanoscale DG MOSFETs
Rupendra Kumar Sharma, Member, IEEE, and Matthias Bucher, Member, IEEE
Abstract—Analog/RF performance of double-gate MOSFETs in
the sub-20-nm regime is investigated using ATLAS device simulator. It is shown that graded channel dual material double gate
(GCDMDG) achieves higher drain current, peak transconductance, and higher values of cutoff frequency at lower drain currents. This novel architecture also provides better intrinsic gain
for an amplifier. A new analog/RF figure of merit, gain transconductance frequency product (GTFP) is proposed that includes both
the switching speed and intrinsic gain of the device and is very useful for circuit design. The peak GTFP is observed at the higher end
of moderate inversion, slightly above threshold. The GCDMDG
device outperforms in terms of GTFP and is more favorable for
shorter channel length devices.
Index Terms—Analog circuit design, ATLAS device simulator,
double-gate MOSFET, dual material double gate (DMDG), graded
channel (GC).
I. INTRODUCTION
HE SCALING with improvement in the device performance is a vital goal of the microelectronics community.
In this context, a number of device engineering schemes such
as source/drain engineering [1], [2], dual material gate (DMG)
technology [3], channel engineering [4], [5], and gate stack
(GS) engineering [6] have been explored and employed during
the past decades. As the MOSFET dimensions are scaled down
to sub-50-nm regime, the threshold voltage Vth reduction with
decreasing channel length and drain induced barrier lowering
(DIBL) are important issues that should be addressed while providing immunity against short-channel effects (SCEs) [7]–[10].
These issues cause the CMOS community to focus on novel
concepts for technology, materials, and structures.
Channel engineering, i.e., graded channel (GC) has received
great attention for suppressing the SCEs and enhanced device
performance [11]–[13]. In the present analysis, low-high-low
doping profile is taken into consideration. First, the whole channel is doped with low doping, and after the gate formation,
center part is doped with high doping by tilted ion implanta-
T
Manuscript received April 8, 2012; accepted June 3, 2012. Date of publication August 1, 2012; date of current version September 1, 2012. This work
was supported in part by the European Community Project Compact Modeling
Network under Grant 218255, and by the Greek Secretariat for Research and
Technology Nano-Sympraxis under Contract 09ΣYN-42-998, and by the European Regional Development Fund and Greek national funds. The review of this
paper was arranged by Associate Editor M. M. DeSouza.
The authors are with the Department of Electronic and Computer Engineering, Technical University of Crete, Chania 73100, Greece (e-mail:
rupendra@electronics.tuc.gr; bucher@electronics.tuc.gr).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TNANO.2012.2204439
tion [14], [15]. In this process, dopant atoms are implanted into
a wafer at a tilt angle to minimize channeling. The angle of
ion implantation is influential on Vth nearby the mask edge.
In this architecture, high doping at the center maintains the
threshold voltage, while low doping near the source and drain
ends ensures high mobility, reduced peak electric field, and impact ionization. In addition, this low-high-low doping profile
reduces the gate misalignment effects on both the source and
drain sides [16], [17]. Furthermore, because of the reduction of
effective gate length, GC devices provide higher drain current
and peak transconductance.
The DMG technology was proposed to enhance the immunity
against SCEs [18], [19]. This DMG engineering has also been
implemented to DG MOSFET for its performance improvement [20], [21]. The dual metal gates are integrated into CMOS
flow by fully silicided metal gates (FuSi) [22], [23], metal wet
etch process [24], metal interdiffusion process [25], [26], and
single metal gate with selectively tuned work function by patterning and implanting a work function modifying species into
one of the electrodes [27], [28]. Kasturi et al., [29] have reported the dual material double-layer GS SON MOSFET for
enhanced analog performance and concluded that DMG device with LM 1 /L (length of high work-function metal gate/total
gate length of the device) ratio of 1/2 exhibits maximum early
voltage VEA and the highest efficiency to translate power into
transconductance.
Recently, the effect of GC, GS, and DMG design engineering
on the performance of nanoscale DG MOSFET is investigated
by Sharma et al., [30]. This work indicates that GC GS double
gate (GCGSDG) is suitable for high-speed switching applications and GS dual material double gate (GSDMDG) provides
superior performance as an amplifier. In the present study, a new
device architecture that includes the advantage of both GC and
DMG, i.e., GC dual material double gate (GCDMDG) is fully
explored with quantum effect. The important analog/RF figures
of merit like transconductance-to-drain current ratio gm /IDS , intrinsic gain gm /gds , early voltage VEA , terminal capacitances,
i.e., gate-to-source capacitance CGS and gate-to-drain capacitance CGD , and cutoff frequency fT are examined. A unique
figure of merit for analog/RF performance, gain transconductance frequency product (GTFP = gm /gd × gm /IDS × fT ) is
also proposed taking into account both the switching speed and
the intrinsic gain for circuit design.
II. DEVICE STRUCTURES AND SIMULATION
Extensive device simulations were performed using ATLAS
device simulator [31] for performance evaluation of DG,
DMDG, GCDG and GCDMDG MOSFETs, as shown in Fig. 1.
1536-125X/$31.00 © 2012 IEEE
SHARMA AND BUCHER: DEVICE DESIGN ENGINEERING FOR OPTIMUM ANALOG/RF PERFORMANCE OF NANOSCALE DG MOSFETS
993
Simulations have been performed using physical models accounting for the electric-field-dependent carrier mobility with velocity saturation, Shockley–Read–Hall recombination/generation with doping-dependent carrier lifetime, Auger
recombination along with Fermi–Dirac statistics, and band gap
narrowing. The mobility model used is the inversion layer
Lombardi CVT mobility model, wherein the phonon scattering model, concentration-dependent mobility, high-field saturation model, and mobility degradation at interfaces are all
included [31].
The local electric-field-dependent model calculates mobility
at every point in the inversion layer as a function of the net electric field at that point. Furthermore, inversion layer quantum
effects are taken into account by density gradient quantum correction model. Although proper calibration of the TCAD model
parameters is essential for more accurate results, however, this
will impact all the DG design configurations in a similar way.
Thus, default simulator coefficients for all parameters have been
employed.
III. RESULTS AND DISCUSSION
Fig. 1. Schematic structures of n-channel SOI MOSFETs with different device
engineering for channel length, L = 15 nm; silicon thickness, tsi = 6 nm;
effective oxide thickness, te ff = 1.0 nm; and gate height, H G = 30 nm. (a)
DG MOSFET. (b) DMDG MOSFET. (c) GCDG MOSFET. (d) GCDMDG
MOSFET.
All these architectures with gate length L = 15 nm, silicon film
thickness tsi = 6 nm, and effective gate oxide thickness teff =
1.0 m with high-k gate dielectric are optimized by tuning the
work function of the metal gate to have the same off current Ioff
at an applied drain bias of 1.0 V. The highly doped source/drain
regions with n-doping concentration N+ of 2 × 1020 cm−3 are
considered to be 15-nm long. In GC architectures, low-highlow abrupt doping profile having gate length L1 :L2 :L3 = 1:2:1
from source-to-drain is considered. For DMDG architectures,
the control gate M1 (toward the source side) and screening gate
M2 (toward the drain side) are the two gate electrodes with
lengths LM 1 and LM 2 (LM 1 :LM 2 = 1:1) and with metal work
functions qφM 1 and qφM 2 . The details of the structural parameters are shown in Table I.
Fig. 2 shows the surface potential and electric field profiles
along the normalized channel position at VDS = 50 mV and
VGS = 0.5 V. For DMDG architectures, the work-function difference (qϕM 1 − qϕM 2 ) between the two gate electrodes M1 and
M2 causes an abrupt change in the conduction band energy at the
silicon surface. This generates a step in the potential profile and
an electric field peak in the center of the channel. Thus, for the
DMDG MOSFETs, the electric field at the drain end is reduced,
and the source carrier injection into the channel is enhanced.
The insertion of GC with DMDG creates an additional step in
potential profile close to the drain (at the interface of high–low
doped region), thus enhancing the device performance. Furthermore, the GCDMDG reduces the electric field at the drain end.
This reduction in the electric field near the drain end also occurs
at higher drain voltage and therefore leads to a reduction in the
hot-carrier effects.
As far as analog circuits are concerned, the most important
parameters are the transconductance gm , output conductance
gds , early voltage VEA , transconductance-to-drain current ratio gm /IDS , intrinsic gain gm /gds , terminal capacitances, i.e.,
gate-to-source capacitance CGS and gate-to-drain capacitance
CGD , and cutoff frequency fT . In Fig. 3, the IDS –VGS and gm –
VGS characteristics have been compared at VDS = 1.0 V while
maintaining the same off current (Ioff = 5 × 10−7 A/μm).
It is interesting to note that GC architectures with low doping on both the source and drain ends exhibit higher IDS and
gm in comparison with other device configurations. To have
the identical Ioff , we have to increase the gate work function
of DMDG and hence decrease the drain current and transconductance. In GC devices, the higher doping in the center of
the channel maintains low Ioff , while low doping at the source
and drain ends ensures high mobility. Furthermore, in GC devices, the low-doped region accumulates inversion carriers until
the highly doped region is switched from OFF to ON. The
increased inversion charge density contributes to improving
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IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 11, NO. 5, SEPTEMBER 2012
TABLE I
PARAMETERS FOR VARIOUS DEVICE CONFIGURATIONS
Fig. 2. Variation of surface potential and electric field with normalized channel
position at V G S = 0.5 V and V D S = 50 mV.
Fig. 4. gm /Id s as a function of the drain current ID S for various DG SOI
MOSFETs at a drain voltage of V D S = 1.0 V.
Fig. 3. Variation of drain current ID S and transconductance gm with gate
voltage V G S for various DG SOI MOSFETs at a drain voltage of V D S = 1.0 V.
drain current and transconductance. The DMG along with GC
architecture, i.e., GCDMDG shows the highest IDS and gm .
This is due to the combined effect of GC and DMG design
engineering.
The gm /IDS ratio demonstrates how efficiently the current is
used to achieve a certain value of transconductance. The advantage of high transconductance-to-drain current ratio is the realization of circuits operating at low-supply voltage. As shown
in Fig. 4, the gm /IDS ratio is maximized in the subthreshold region of device operation. In this region, the gm /IDS ratio of DG
and GCDG is better than the DMDG and GCDMDG configurations. On the other hand, we observe that gm /IDS for GCDG
and GCDMDG is slightly improved at higher levels of current
over the other devices (inset).
Fig. 5(a) shows the output characteristics IDS –VDS and
gDS –VDS at a gate voltage of 0.5 V. The GCDG and GCDMDG
demonstrate higher drain current and perform much better at
higher drain voltage, due to higher DIBL effects. The reduced
effective gate length as well as the improved effective mobility
of inversion carriers for GC devices improves the device
performance. The DMDG exhibits the lowest value of output
conductance in saturation. The reduction of the length of the
velocity-saturated region in DMG architecture decreases the
output conductance of the device in saturation. The GC devices
demonstrate the highest value of output conductance due to
reduced effective drain bias. An enormous improvement is
observed in the VEA of DMDG as compared to DG device
as shown in Fig. 5(b). In DMG architecture, M1 controls
the current drive capability and M2 output conductance,
the improvement offered by DMG is because of a balanced
contribution from both gates (M1 and M2 ). Furthermore, in
DMDG, the reduction of the length of the velocity-saturated
region decreases the output conductance and thus increases the
VEA of DMDG devices. The GCDG device shows the lowest
VEA due to lowering of effective VDS . The VEA of GCDMDG
is much better than that of the GCDG MOSFET, because of the
inclusion of DMG engineering.
The DMDG devices provide a better gain as compared to
other device configurations as shown in Fig. 6. The improved
performance of DMG design is attributed to the fact that practically all VDS increase is dropped across the channel region
under gate M2 , and the electron concentration is unaffected in
the inversion layer under gate M1 . Even though the GCDG have
SHARMA AND BUCHER: DEVICE DESIGN ENGINEERING FOR OPTIMUM ANALOG/RF PERFORMANCE OF NANOSCALE DG MOSFETS
Fig. 5. Output characteristics as a function of drain voltage for V G S = 0.5 V.
(a) Drain current and Output conductance. (b) Early Voltage.
Fig. 6. gm /gd s as a function of the drain current ID S for various DG SOI
MOSFETs at a drain voltage of V D S = 1.0 V. Variation of gm /gd s with ID S
for GCDMDG with the variation of the length of M1 and M2 (inset).
worse gm /gds ratio, the GCDMDG configuration shows better
gain compared to DG MOSFET except at highest current levels.
This is due to the prominent DMG technology that compensates
the degradation caused by GC architecture. Furthermore, the
variation of length ratio of M1 and M2 for GCDMDG is shown
in Fig. 6 (inset). As M1 controls the current drive capability and
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Fig. 7. Variation of (a) fT and (b) fm a x with drain current ID S in linear scale
for various DG MOSFETs at V D S = 1.0 V. Variation of (a) fT and (b) fm a x
with drain current ID S in log scale (inset).
M2 output conductance, the increase in the length of the screening gate M2 reduces the output conductance and thus improves
the intrinsic gain. On the other hand, an increase in the length of
control gate M1 decreases the gm and consequently reduces the
gm /gds . The improvement offered by DMDG with an LM 1 /LM 2
ratio of one is because of a balanced contribution from both
gates M1 and M2 .
Cutoff frequency fT and maximum oscillation frequency
fm ax are two important parameters for evaluating the RF
performance of the device. Generally, fT is the frequency
when the current gain is unity, whereas fm ax is the frequency
at unity power gain. fT and fm ax are calculated as shown in
(1) and (2) [32], where gm and gds are the transconductance
and output conductance; CGG , CGS , and CGD are the total
gate capacitance, gate-to-source capacitance, and gate-to-drain
capacitance; RG , RS , and Ri are the gate, source, and channel
resistance, respectively,
gm
gm
=
(1)
fT ≈
2π(CGS + CGD )
2πCGG
gm /2πCGG
.
fm ax ≈ 2 (RG + RS + Ri )(gds + 2πfT CGD )
(2)
The GC architectures, i.e., GCDG and GCDMDG demonstrate
the higher fT due to their improved gm as shown in Fig. 7.
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Fig. 8.
IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 11, NO. 5, SEPTEMBER 2012
GTFP as a function of the drain current ID S for V D S = 1.0 V.
Fig. 10. Variation of cutoff frequency fT with source/drain parasitic resistance
at V G S = 0.5 V and V D S = 1.0 V.
Fig. 9. Variation of cutoff frequency fT with channel length L at V G S = 0.5 V
and V D S = 1.0 V.
Fig. 11. Abrupt and Gaussian doping profile in the channel region for lowhigh-low doped GC devices.
The higher values of gds for GC devices slightly decrease the
percentage improvement in fm ax as compared to DG. It is interesting that GCDG and GCDMDG achieve maximum fT and
fm ax for lower values of drain currents. The GCDMDG shows
10% improvement in fT when compared with DG MOSFET
and is thus a good candidate for high-speed switching applications. These simulated results may be slightly higher than
those of the experimental results, since some considered parasitic parameters may be smaller than those of the real case, such
as gate-to-source/drain capacitance, source/drain contact resistance. However, this will not impact the conclusion of this paper.
The product of gm /IDS and fT represents a tradeoff between
power and bandwidth and is utilized in moderate to high-speed
designs [33]. The intrinsic gain gm /gds is a valuable figure of
merit for operational transconductance amplifier [34]. To comprise these aspects of analog/RF circuit design, a unique figure
of merit, the GTFP (GTFP = gm /gds × gm /IDS × fT ) is proposed. The variation of GTFP with drain current is shown in
Fig. 8. It is interesting to note that the peak value of GTFP occurs at a quite low level of drain current, in the vicinity of IDS =
1.9 × 10−4 A/μm, corresponding to transition from moderate to
strong inversion (around VGS = 0.275 V as shown in inset). Note
that this corresponds to VGS just about 75 mV above the thresh-
old voltage of the device. This provides valuable information
for circuit designers, allowing them to determine the optimal
region achieving the best overall tradeoff among gain, transconductance, and speed. The GCDMDG devices exhibit the highest
GTFP for the same current level in comparison to other device
configurations. This is due to the reduction in peak electric field,
lower output conductance (or higher early voltage) of DMDG
devices along with higher transconductance of GC devices. The
reduction of the length of the velocity-saturated region in DMG
architecture decreases the output conductance of the device in
saturation. Thus, GCDMDG is an ultimate device architecture
for high-speed switching applications along with better intrinsic
gain for an amplifier.
The variation of cutoff frequency fT with channel length
L is shown in Fig. 9. We choose the gate voltage, which is
approximately 0.3 V above the threshold voltage, as well as onehalf of the supply voltage [35]. Thus, for all the comparisons,
fT is extracted at a particular gate voltage of VGS = 0.5 V
while VDS = 1.0 V. The GCDMDG shows the highest fT when
compared with other devices. The crucial advantage offered
by GCDMDG architecture is that this configuration is more
favorable for shorter channel length devices.
SHARMA AND BUCHER: DEVICE DESIGN ENGINEERING FOR OPTIMUM ANALOG/RF PERFORMANCE OF NANOSCALE DG MOSFETS
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TABLE II
ANALOG/RF FIGURES OF MERIT FOR VARIOUS DG MOSFETS SIMULATED IN THE WORK
The effect of the parasitic source/drain resistances RS /RD is
taken into consideration by lumping it in the intrinsic devices
[35]. These devices have an effective width of 1 μm and the
height of gate electrode is considered to be 30 nm. Fig. 10
shows the dependence of fT on contact resistance RS and RD
for VDS = 1.0 V and VGS = 0.5 V. It can clearly be seen
that GCDMDG shows the highest cutoff frequency irrespective
of the value of RS and RD . For constant resistivity of 1 ×
10−8 Ω·cm2 which corresponds to RS = Rd = 75 Ω, fT for
GCDMDG is deteriorated by approximately 20%.
The abrupt and Gaussian doping profile along the channel
direction is shown in Fig. 11. Note that gm for Gaussian doping
profile is slightly improved and consequently enhances the cutoff frequency of the device. This is due to the better movement
of inversion charge carriers inside the channel region.
Analog/RF figures of merit like transconductance gm ,
transconductance-to-drain-current ratio gm /IDS , intrinsic gain
gm /gds , early voltage VEA , cutoff frequency fT , maximum oscillation frequency fm ax , transconductance frequency product
TFP = gm /IDS × fT , and GTFP (GTFP = gm /gds × gm /IDS ×
fT ) are compared for various DG devices in Table II. The gate
voltage of VGS = 0.3 V is chosen at which TFP and GTFP attain
their maximum value. It is quite clear that at this particular value
of VGS , corresponding to the higher end of moderate inversion
or onset of strong inversion regime, GCDMDG outperforms
other devices in terms of overall analog/RF performance.
IV. CONCLUSION
The new device architecture with GCDMDG is proposed
for enhanced analog/RF device performance. This specific design configuration provides higher values of drain current, peak
transconductance, higher cutoff frequencies, and maximum oscillation frequency at lower drive currents. The GCDMDG devices also exhibit better intrinsic gain for an amplifier. A unique
figure of merit, GTFP is proposed to provide a quite complete
description for analog circuit design. The GCDMDG presents
an optimum GTFP, which occurs in moderate inversion, close
to the onset of strong inversion. Thus, GCDMDG is an ultimate device structure for both high-speed switching and for
amplification.
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Rupendra Kumar Sharma (M’12) received the
M.Sc. degree in physics from the Chaudhary
Charan Singh University, Meerut, India, and the
Ph.D. degree in electronics from the Department
of Electronic Science, University of Delhi, India.
His Ph.D. thesis was on the modeling, simulation,
and characterization of gate misalignment effect in
double-gate MOSFETs.
He was a Postdoctoral Researcher with the Advanced Research Center for Electronic Systems and
Department of Electronics, University of Bologna,
Bologna, Italy, where he was involved in numerical optimization and characterization of a dual N/P channel superjunction laterally diffused metal–oxide–
semiconductor for low-dropout voltage regulator applications. He is currently
working as a Postdoctoral Researcher with the Telecommunication Systems
Institute, Technical University of Crete, Chania, Greece in a European Funding Research Program Compact Modeling Network on compact modeling of
Nanoscale Multigate MOSFETs and of High-Voltage MOSFETs. He has authored or coauthored numerous scientific papers.
Matthias Bucher (M’01) received the Graduate degree in electrical engineering and the Ph.D. degree from the Swiss Federal Institute of Technology,
Lausanne, Switzerland, in 1993 and 1999, respectively. His Ph.D. dissertation was on the analytical
metal–oxide–semiconductor transistor modeling for
analog circuit simulation.
In 1997, he was an Invited Researcher with LSI
Logic, Milpitas, CA. From 2000 to 2003, he was a
Visiting Researcher with the National Technical University of Athens, Athens, Greece, and held numerous consulting mandates in microelectronics industry. In 2004, he joined the
Department of Electronic and Computer Engineering, Technical University of
Crete, Chania, Greece, as an Assistant Professor. He has also coordinated the
EKV3 MOS transistor compact model code development. He is the author or
coauthor of numerous scientific papers. His current research interests include
the design of ultralow voltage analog/RF integrated circuits, the characterization
and compact modeling of nanoscale CMOS devices including static to RF and
noise aspects.