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Comparison of commutation transients of inverters
with silicon carbide JFETs with and without body
diodes.
Björn Ållebrand and Hans-Peter Nee
Abstract— An inverter could be built by using silcon carbide power
switches only. This can be done by using SiC JFETs which can conduct
current in both directions. An interesting question is how an inverter using
SiC JFETs with a body diode compares with an inverter using SiC JFETs
without body diodes. This will be discussed in this paper.
SiC diode would have a far to high voltage drop compared to the
SiC JFETs.
I. I NTRODUCTION
M
Silicon carbide has been pointed out for long as the material
that will replace silicon as the dominating semiconductor material for switching power applications [4]. The reason for this is
that the drift resistance in SiC power devices can theoretically
be up to 700 times lower than in silicon power devices of equal
area while the drift region can sustain the same blocking voltage
[6]. Additionally, silicon carbide can withstand higher temperatures than silicon.
In inverters today the IGBT is the normally used component.
Since an IGBT cannot conduct current in the reverse direction,
an anti-parallell power diode is needed. However, a SiC JFET
can conduct current in both forward and reverse direction eliminating the need for a power diode as first suggested in [1].
II. I NVERTER TOPOLOGY
In Fig. 1, a conventional topology for a voltage-type inverter
is shown. This inverter utilizes IGBTs with anti-parallell diodes.
M
Fig. 1. A standard inverter with IGBTs and diodes.
In Fig. 2, it is shown how a voltage-type inverter can be designed utilizing SiC JFETs. Notice that no anti-parallell diodes
are used. Therefore only six components are needed compared
to twelve for the IGBT inverter. This also means that the hightemperature capabilities of the SiC JFETs can be utilized since
there are no Si components. Additinally, as explained in [1], a
B. Ållebrand is a Ph.D. Student at Electrical Machines and Power Electronics, Royal Institute of Technology (KTH), Stockholm, Sweden. E-mail:
bjorn.allebrand@ekc.kth.se .
H. Nee is Professor at Electrical Machines and Power Electronics, Royal Institute of Technology (KTH), Stockholm, Sweden.
Fig. 2. An inverter with SiC JFETs.
III. P ROPERTIES OF S I C JFET S
The properties of SiC JFETs are not very well known compared to MOSFETs and IGBTs. Therefore, in this section the
properties of SiC JFETs will be discussed.
The JFET is a normally-on device. This means that if no voltage
or zero voltage is applied to the gate the device is conducting.
A negative gate voltage is required to turn the device off. Additionally, the threshold voltage (the turn-off voltage) for SiC
JFETs is higher than compared to IGBTs and MOSFETs. It is
in the range of -15 to -30 V. As discussed in [3], the gate capacitances of SiC JFETs will probably be significantly higher than
comparable Si IGBTs. Together, the capacitance and the high
gate voltage contributes to put higher demands on the gate drive
circuit.
However, there are different designs of SiC JFETs and in this
section two different structures will be discussed, the buried gate
JFET [7] and the vertical JFET [8]. A normal structure of a SIC
buried gate JFET (bg-JFET)can be found in Fig. 3 and a SiC vertical JFET structure (VJFET) can be seen in Fig. 4. The main
difference between a SiC bg-JFET and a SiC VJFET is the existence of the body diode in the VJFET. This body diode can be
seen in Fig. 4. It is a bipolar diode and it is quite fast because
it is a SiC diode, [9]. But due to the high bandgap of silicon
carbide (around 3 eV) it has a forward voltage drop of approximately 3V, causing losses when conducting high currents. However, this diode can be used during the commutation procedure
as shown in [5].
IV. C OMMUTATION PROCEDURE
Compared to a normal inverter the main difference is that
there are no anti-parallell silicon diodes. This means that a
different commutation strategy has to be used. How blanking
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SOURCE
DRAIN
source voltage that controls the current through the JFET, but the
gate-drain voltage. This applied negative gate voltage cannot
change the current. Instead, the JFET has to operate in the saturation region. This situation will remain until JFET Q1 is turned
on. At this stage the commutation process is initiated. The current through JFET Q1 increases, while the current through JFET
Q2 decreases. When the current through JFET Q2 reaches zero,
JFET Q2 will stop conducting immediately due to the negative
gate voltage applied and the fact that it is now the gate-source
voltage that determines if JFET Q2 is on or off.
N
P
GATE
Fig. 3. A buried gate JFET (bg-JFET) structure.
Source
n+
p+
Gate
n
p+
n+
Drain
Fig. 4. A vertical JFET (VJFET) structure.
times affect the commutation procedure for SiC JFETs without body diodes was investigated in [2]. It was shown that a
strategy involving temporary short-circuits increases the switching losses. Therefore, postive blanking times should be used.
This means that the commutation procedure for inverters utilizing SiC JFETs with body diodes will not be the same as for
inverters utilizing SiC JFETs without body diodes. The commutation procedure is for SiC JFETs with body diodes is described
completely in [5]. Below the two commutation procedures are
described briefly.
A. Commutation procedue for SiC JFET without internal SiC
body diodes
To understand the principle of operation the simple chopper
circuit in Fig. 5 is studied. Assume that JFET Q1 is conducting
and JFET Q2 is not conducting, i.e. turned off. When JFET Q1
is given a negative gate voltage in an attempt to turn it off, the
current through JFET Q1 has no place to commutate. Therefore
Q1 cannot be turned off and will continue to conduct in the saturation region, which means that there will be large losses during
this time. This continues until JFET Q2 is turned on. Now,
the current can begin to commutate through JFET Q2. As soon
as the current through JFET Q2 reaches the load current, JFET
Q1 will turn off as the gate-source voltage across Q1 is close to
the threshold voltage. At this stage the commutation process is
completed.
For the commutation process when JFET Q2 is turned off, JFET
Q2 recieves a negative gate voltage. However, due to the reverse direction of the current through the JFET, it is not the gate-
B. Commutation procedue for SiC JFET with internal SiC body
diodes
For a circuit utilizing SiC JFETs with internal SiC diodes
there is not much difference in the commutation procedure from
switches with anti-parallell diodes. The main difference is that
the internal diodes are silicon carbide diodes, which means that
there will be nearly no reverse recovery and that the voltage drop
will be approximately 3 Volts due to the high bandgap of SiC
JFETs, [9]. See [5] for a more detailed description of the commutation procedure.
C. Main differences
The main difference compared to circuits utilizing swicthes
with anti-parallell diodes is that the JFET with no internal diode
will operate for a short time period in the saturation region.
V. S IMULATIONS
Simulations have been performed using Capture/PSpice. A
simple stepdown converter as shown in Fig. 5 was investigated.
This could represent one bridge leg of a three-phase inverter.
The dc-link voltage was 500 V and the load current was 2 A.
The PSpice parameters used in the simulations were based on
SiC JFETs obtained from SiCED and from [7]. The internal
body-diode of the SiC JFET was modelled as an ideal diode
with a forward voltage drop of 3V. In these simulations a positive blanking time was used both in the turn-on of JFET Q1 and
turn-off of JFET Q1.
Lsigma
Q1
Q2
I
Fig. 5. One bridge leg of a threephase inverter.
In Fig. 6 the currents can be seen for both cases, for SiC JFETs
with body diodes and for SiC JFETs without body diodes. They
are very simular. The switching losses for a SiC JFET without
body diode will be slightly higher than compared to a SiC JFET
with a body diode, as seen in Tables I and II, assuming a switching frequency of 10 kHz.
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JFET
VJFET
bg-JFET
Case
turn-on Q1
turn-off Q2
turn-on Q1
turn-off Q2
Losses (W)
2,66
2,16
3,21
2,33
switching transients for an inverter with SiC JFETs with internal body diodes as these switching transients are more simpler
than inverters utilizing bg-JFETs. In Figures 7 - 9 the switching
transients can be seen.
TABLE I
L OSSES AT TURN - ON OF JFET Q1 AND TURN - OFF OF JFET Q2.
JFET
VJFET
bg-JFET
Case
turn-off Q1
turn-on Q2
turn-off Q1
turn-on Q2
Losses (W)
0,58
0,08
0,58
0,08
A. Phase I
A negative voltage is applied to the gate of JFET Q1 and it
turns off, meanwhile the current commutates over to the SiC
body diode. Now both JFETs are blocking.
B. Phase II
TABLE II
L OSSES AT TURN - ON OF JFET Q2 AND TURN - OFF OF JFET Q1.
Zero Volts is applied to the gate of JFET Q1 and the gatesource voltage rapidly drops towards the threshold voltage and
JFET Q1 turns on. Now the JFET will enter the saturation region
and the drain current will slowly increase and the body diode
current will decrease towards zero. As soon as the body diode
current reaches zero this phase ends.
C. Phase III
The losses when JFET Q1 turns off and JFET Q2 turns on
are in the two cases almost equal. When JFET Q1 turns on and
JFET Q2 turns off, however, the JFET with body diode will have
slightly lower switching losses.
Unfortunately, despite using a positive blanking time, a shortcircuit occurs causing excessive losses. The explanation to this
is given in the next section.
16
Since the current through the body diode is zero, JFET Q2
can start to block voltage. The gate-drain capacitance starts to
charge. For this to happen a current is required and part of this
current discharges the gate-source capacitance. Due to the high
gate-drain capacitance of these JFETs, the gate-source capacitance of JFET Q2 discharges and the gate-source voltage quickly
reaches the threshold voltage, and the JFET turns on. Now both
JFETs are conducting and there is a short-circuit in main circuit.
At the end of phase III JFET Q2 is blocking the dc-link voltage.
14
12
D. Phase IV
10
In this phase, JFET Q2 is in the off-state and JFET Q1 has
been turned on. However, there will be oscillations in the circuit
due to the stray inductance and the gate capacitances. Depending on these parameters, JFET Q2 may turn on again for a very
short time as these oscillations are dampened.
Current (A)
8
6
4
2
E. Phase V
0
At the start of phase V the switching transients have decayed
and steady state conditons applies.
−2
−4
0
50
100
150
200
250
300
350
400
450
500
Time (ns)
VII. H OW TO REDUCE THE SHORT- CIRCUIT CURRENT
Fig. 6. Currents during turn-off of Q2. The solid line is the drain current through
JFET Q2 with body diode. The dashdotted line is the drain current through
JFET Q1 without body diode, and the dashed line is the current through the
body diode of JFET Q2.
VI. S HORT- CIRCUIT CURRENT
As shown in the simulations and in [5], a short-circuit occurs when Q1 turns on and Q2 turns off. This is because the
lower JFET turns on unintentionally during the switching transient. Creating a short-circuit in the bridge leg as seen for the
drain currents in Fig. 6.
Why this phenomenon occurs can be explained by studying the
The short circuit which occurs in phase III has to be reduced
or the low on-state losses of the SiC JFET cannot be properly
utilized.
The most obviuos choice would be to reduce the the gate-drain
capacitance. This can be arranged by redesigning the structure
of the SiC JFETs. But this will probably lead to a higher onstate resistance, which is not desired.
Another way would be to increase the gate-source voltage from
for instance -35 V to -70 V. A higher voltage, however puts
higher demands on the gate drive circuit and the JFETs may
be designed for a lower gate-source voltage, such as -40 V. This
may lead to that the SiC JFET structure must be changed. But
this is an effective way of reducing these short circuits currents.
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A. New simulations with reduced gate-drain capacitance
16
New simulations were performed with the gate-drain capacitance reduced to half. The results from these simulations can be
found in tables III and IV. Assuming a switching frequency of
10 kHz.
14
12
Drain currents (A)
10
8
JFET
VJFET
6
4
2
bg-JFET
0
Case
turn-on Q1
turn-off Q2
turn-on Q1
turn-off Q2
Losses (W)
0,64
1,16
0,82
1,38
−2
I
−4
0
II
100
200
III
300
IV
400
V
500
TABLE III
L OSSES AT TURN - ON OF JFET Q1 AND TURN - OFF OF JFET Q2 FOR
LOWER GATE - DRAIN CAPACITANCE .
600
Time (ns)
Fig. 7. Drain currents for the turn-off of JFET Q2 and turn-on of JFET Q1. The
solid line is the drain current through JFET Q1. The dotted line is the drain
current through JFET Q2
JFET
VFFET
600
500
Drain−source voltages (V)
bg-JFET
400
Case
turn-off Q1
turn-on Q2
turn-off Q1
turn-on Q2
Losses (W)
0,2
0,02
0,21
0,08
TABLE IV
L OSSES AT TURN - ON OF JFET Q2 AND TURN - OFF OF JFET Q1 FOR
LOWER GATE - DRAIN CAPACITANCE .
300
200
100
0
I
−100
0
II
100
200
III
300
IV
400
V
500
600
Time (ns)
Fig. 8. Drain-source voltages for the turn-off of JFET Q2 and turn-on of JFET
Q1. The solid line is the drain-source voltage over JFET Q1. The dotted line
is the drain-source voltage over JFET Q2
5
Now the losses are approxiamtely four times lower and this is
because the short-circuit current is lower. With these capacitance values, the switching losses are lower that the on-state
losses.
B. New simulations with increased turn off voltage
In these simulations the turn off voltage was increased from
-35 V to -70 V. As seen in Fig 10 the short-circuit current is
nearly neglible.
0
VIII. C ONCLUSION
Gate−source voltages (V)
−5
−10
−15
−20
−25
−30
−35
−40
I
−45
0
II
100
200
III
300
Time (ns)
V
IV
400
500
600
Fig. 9. Gate-source voltages for the turn-off of JFET Q2 and turn-on of JFET
Q1. The solid line is the gate-source voltage over JFET Q1. The dotted line
is the gate-source voltage over JFET Q2
Using an inverter with only SiC JFETs is possible. The different SiC JFET structures should not change the principle of
operation much. The only difference is a small difference in
the switching losses. SiC JFETs with internal body diodes are
slightly better.
A drawback is that short-circuit currents will occur and this
increases the switching losses. The short-circuit currents are
hard to reduce and must probably be dealt with by redesigning
the structures of the SiC JFETs or increasing the turn off voltage. These problems are likely to be less significant with larger
JFETs than those discussed in this paper.
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[1]
[2]
B. Ållebrand and H.-P. Nee, “On the possibility to use SiC JFETs in Power
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B. Ållebrand and H.-P. Nee, “On the choice of blanking times at turn-on
and turn-off for the diode-less SiC-JFET inverter bridge,” in Proceedings
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4
3.5
3
drain currents (A)
2.5
2
1.5
1
0.5
0
−0.5
−1
0
100
200
300
time (s)
400
500
600
Fig. 10. Drain currents for the turn-off of JFET Q2 and turn-on of JFET Q1.
The dotted line is the drain current through JFET Q1. The solid line is the
drain current through JFET Q2.
[3]
[4]
[5]
[6]
[7]
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