3.125Gbps x4 Parallel Transceiver
Macro for XAUI (0.11µm)
Transmitter
Receiver
n=3
…
…
n=3
n=1
781MHz
PRBS
Gen
4
CLK
Gen
TXPIn[15:0]
+ TXPCLK
RX &
1:4DEMUX
3.125Gbp
RX &
1:4DEMUX
(Boundary)
4
4:16DEMUX
& Sync
4
TXODCNT[1:0]
PNGEN
RXPOn[15:0]
RXPCLK (Recovered Clock)
16
4:16DEMUX
& Sync
4 4
TXCHPDn
781MHz
…
TMR
TMR
RXIPn
RXINn
16
…
…
…
17
16:4MUX
& Sync
n=0
Receiver Unit
(Data)
CDR loop
8
PNERRn
PNBITCNTn[3:0]
PRBS
Comp
D/F
Phase
Detect
P/I
…
3.125Gbps
17
17
4
4:1
MUX
RXVTT
n=0
Transmitter Unit
…
TXOPn
TXONn
TMR
TMR
…
n=1
RXCHPDn
RXPD
RXRST
781MHz
4
PLL Unit
4
PLL Unit
156MHz for
logic circuit
156MHz for
logic circuit
CLK
Div
PLL
1.56GHz
REF_CLK
1.56GHz
PLL
156MHz
REF_CLK
156MHz
▲
Features
• 3.125Gbps x 4 channel unidirectional data transfer rate
for 10G Ethernet physical layer
• 1:16 SERDES with 16:20 gearbox, 8B/10B coding and
lane lane alignment provided as RTL/netlist
• IEE802.3ae physical layer compliant
• On chip integrated 50-ohm termination resistors
• 156MHz input reference clock and parallel interface
• Independent dual loop PLL based CDR on each Rx
channel
• 4-channel CDR Rx and 4-channel Tx arrays
• Differential PCML (Vterm=1.2V and 1.8V)
• AC coupled differential interface
• Built-in PRBS (2^23-1) generators and comparators for
loopback testing
• 1.2V and 2.5V power supply, 0.11µm standard CMOS
process
▲
Benefits
• Available as library cell for ASIC designs
• Programmable Tx voltage swing and amount of
pre-emphasis
• Pre-emphasis based Tx equalization allows up to 12dB
high frequency loss
• Meet XAUI jitter specifications (IEEE 802.3)
3.125Gbps x4 Parallel Transceiver
▲
Description
The Fujitsu’s XAUI macro is for ASICs that perform at
high bandwidth data communication.
The macro is fabricated in Fujitsu’s standard 0.11µm
CMOS technology.
The macro meets XAUI jitter specifications as follows:
The macro can be used in a variety of applications:
• jitter generation < 0.35UI (without pre-emphasis)
• 10G Ethernet
• jitter tolerance > 0.60UI (peak to peak total jitter)
• WAN router or switch backplanes and line card to
switch fabric interface
• meets sinusoidal jitter tolerance mask requirement
The macro has 100mW/ch power dissipation(including
Rx, Tx, CDR, bias circuit and PLL, maximum preemphasis) and runs under power supply of 1.2V±0.10V,
2.5V±0.20V and junction temperature of 0°C~125°C.
• Any backplane line for 3.125Gbps x4 data rate
▲
Deliverables
The Fujitsu value-added XAUI Transceiver Macro enables
customers to design a variety of complex ASIC designs
for high-end networking applications.
• Verilog Model
A Fujitsu application engineer works with the customer to
identify the customer’s specific IP requirements. Fujitsu
will provide the customer with the following information
to support the 3.125Gbps x4 XAUI Transceiver macro:
• Design Compiler Model
– Front-end simulation
– C model with Verilog wrapper
– Timing analysis
• Library Exchange Format (LEF)
– Floorplanning
– Place and Route
FUJITSU MICROELECTRONICS AMERICA, INC.
Corporate Headquarters
1250 East Arques Avenue, Sunnyvale, California 94088-3470
Tel: (800) 866-8608 Fax: (408) 737-5999
E-mail: inquiry@fma.fujitsu.com Web Site: http://www.fma.fujitsu.com
©2002 Fujitsu Microelectronics America, Inc.
All company and product names are trademarks or
registered trademarks of their respective owners.
Printed in the U.S.A. ASIC-FS-20947-9/2002