HARDWARE IMPLEMENTATION OF A STIMULUS ARTIFACT REJECTION
ALGORITHM IN CLOSED-LOOP NEUROPROSTHESES
By
CHIA-WEI SOONG
Submitted in partial fulfillment of the requirements
For the degree of Master of Science
Thesis Advisor: Dr. Pedram Mohseni
Department of Electrical Engineering and Computer Science
CASE WESTERN RESERVE UNIVERSITY
August, 2008
CASE WESTERN RESERVE UNIVERSITY
SCHOOL OF GRADUATE STUDIES
We hereby approve the thesis/dissertation of
Chia-Wei Soong
_____________________________________________________
M.S.
candidate for the ______________________degree
*.
Dr. Pedram Mohseni
(signed)_______________________________________________
(chair of the committee)
Dr. Frank Merat
________________________________________________
Dr. Marc Buchner
________________________________________________
________________________________________________
________________________________________________
________________________________________________
July 10, 2008
(date) _______________________
*We also certify that written approval has been obtained for any
proprietary material contained therein.
Table of Contents
1. INTRODUCTION .........................................................................................1
1.1
MOTIVATION ....................................................................................................... 1
1.2
BACKGROUND ..................................................................................................... 3
1.2.1 SA Rejection with Blanking Techniques .......................................................... 3
1.2.2 SA Rejection with Subtraction Techniques...................................................... 4
1.3
RESEARCH OBJECTIVES ..................................................................................... 7
2. SYSTEM DESIGN AND IMPLEMENTATION .................................................8
2.1
SYSTEM STRUCTURE .......................................................................................... 8
2.2
DESIGN OF SAR BLOCK ..................................................................................... 9
2.2.1 Basic Methodology.......................................................................................... 9
2.2.2 SAR Block Architecture ..................................................................................11
2.2.3 SAR Algorithm Parameters........................................................................... 14
2.2.4 Averaging Method......................................................................................... 16
2.3
SYSTEM SIMULATION AND HARDWARE IMPLEMENTATION............................. 18
2.3.1 System Simulation of SAR Algorithm............................................................ 18
2.3.2 Hardware Implementation of SAR Algorithm ............................................... 20
2.3.3 Hardware Implementation of SAR System .................................................... 24
3. PROTOTYPE SYSTEM MEASUREMENT RESULTS ....................................27
3.1
3.2
OVERVIEW ........................................................................................................ 27
MEASUREMENT RESULTS ................................................................................. 28
4. CONCLUSION AND FUTURE WORK .........................................................38
5. APPENDICES ............................................................................................39
APPENDIX A .................................................................................................................. 39
APPENDIX B .................................................................................................................. 41
6. BIBLIOGRAPHY .......................................................................................51
I
List of Tables
Table
3.1: System Features and Measured Performance Characteristics ......................28
II
List of Figures
Figure 1.1: The characteristics of a stimulus artifact (top) and a neural action potential
(bottom)..................................................................................................................2
Figure 2.1: (a) Traditional neural recording system with offline implementation of the
SAR block in software. (b) The proposed system implementation with the
SAR block placed after the first amplification stage. ............................................9
Figure 2.2: a) Input signal containing both a large-amplitude SA and a small neural
spike. b) Estimated SA reference signal for subtraction. c) Recovered neural
spike after SA subtraction. ...................................................................................10
Figure 2.3: Architecture of the proposed stimulus artifact rejection block. ....................11
Figure 2.4: Flow chart diagram of the proposed stimulus artifact rejection algorithm. ..13
Figure 2.5: Simplified illustration of sampling rate effect on the SAR algorithm
performance. Sampling rates are set to 50 and 25 Hz in the top and bottom
plots, respectively.................................................................................................15
Figure 2.6: System-level simulation results for the SAR block. .....................................19
Figure 2.7: An expanded view of the simulated data in Fig. 2.6. ....................................20
Figure 2.8: Data flow chart and memory arrangement for the implementation of the
SAR algorithm in the microcontroller..................................................................23
Figure 2.9: Schematic diagram of the hardware implementation for the SAR system. ..24
Figure 2.10: Schematic block diagram of the front-end neural recording circuitry,
comprising an instrumentation amplifier and two cascaded filtering stages. ......25
Figure 2.11: Simulated frequency response of the front-end neural recording circuitry.
..............................................................................................................................26
Figure 2.12: Simulated ac response of the front-end neural recording circuitry. ............26
Figure 3.1: Photograph of the custom-designed hardware implementation of the SAR
block.....................................................................................................................27
Figure 3.2: Two different stimulus artifact waveforms used in generating the input
signal for the SAR block......................................................................................29
Figure 3.3: System measurement results with Test Signal 1. The top trace depicts the
amplified signal fed to the SAR block that contains five stimulus artifacts
III
(occurring at 10 Hz) and randomly positioned neural spikes. The middle trace
depicts the estimated stimulus artifact template signal. The bottom trace
shows the SAR block output after subtraction where neural spikes are
recovered in between the artifacts........................................................................32
Figure 3.4: An expanded view of the three signals in Fig. 3.3, depicting on the bottom
trace the two residual stimulus artifacts as well as a neural spike recovered
from the decaying tail of the artifact....................................................................32
Figure 3.5: System measurement results with Test Signal 2. The top trace depicts the
amplified signal fed to the SAR block that contains five stimulus artifacts
(occurring at 10 Hz) and randomly positioned neural spikes. The middle trace
depicts the estimated stimulus artifact template signal. The bottom trace
shows the SAR block output after subtraction where neural spikes are
recovered in between the artifacts........................................................................33
Figure 3.6: An expanded view of the three signals in Fig. 3.5, depicting on the bottom
trace the two residual stimulus artifacts as well as a neural spike recovered
from the decaying tail of the artifact....................................................................33
Figure 3.7: System measurement results with Test Signal 3. The top trace depicts the
amplified signal fed to the SAR block that contains five stimulus artifacts
(occurring at 10 Hz) and randomly positioned neural spikes. The middle trace
depicts the estimated stimulus artifact template signal. The bottom trace
shows the SAR block output after subtraction where neural spikes are
recovered in between the artifacts........................................................................34
Figure 3.8: An expanded view of the three signals in Fig. 3.7, depicting on the bottom
trace the two residual stimulus artifacts as well as a neural spike recovered
shortly after the decaying tail of the artifact. .......................................................34
Figure 3.9: System measurement results with Test Signal 4. The top trace depicts the
amplified signal fed to the SAR block that contains five stimulus artifacts
(occurring at 2.5 Hz) and randomly occurring neural spikes. The middle trace
depicts the estimated stimulus artifact template signal. The bottom trace
shows the SAR block output after subtraction where neural spikes are
recovered in between the artifacts........................................................................35
Figure 3.10: An expanded view of the three signals in Fig. 3.9, depicting on the
bottom trace the two residual stimulus artifacts as well as a neural spike
recovered from the decaying tail of the artifact. ..................................................35
Figure 3.11: Measured waveforms of the SAR block with Test Signal 1 as the input at
4 different timestamps during the operation. It takes ~9 seconds to reach
steady state in plot D............................................................................................36
IV
Figure 3.12: Stimulus artifact rejection results (with Test Signal 2) with a) the original
SAR algorithm and b) the proposed SAR algorithm in hardware
implementation using the pseudo-higher sampling rate concept. Additional
suppression of ~5.5 dB is achieved......................................................................37
V
Hardware Implementation of a Stimulus Artifact Rejection Algorithm in
Closed-Loop Neuroprostheses
Abstract
by
CHIA-WEI SOONG
Due to their large amplitudes, stimulus artifacts can easily saturate neural
recording amplifiers and hamper neural signal analysis during recording. In this work, we
present a prototype stimulus artifact rejection (SAR) system, which is based on the
template subtraction technique. A reference template signal of the stimulus artifact is
generated by a pseudo-higher sampling rate averaging method, which is then subtracted
from the original contaminated signal to reveal the desired neural activity. Measurement
results from a proof-of-concept discrete implementation of the SAR system indicate that
it is highly effective in reducing the amplitude of the stimulus artifacts. The system
exhibits a stimulus artifact rejection of ~10-15 dB at the rising and falling edges of the
artifact (where it is changing rapidly with time) and successfully recovers
microvolt-range neural action potentials from the slowly decaying tail of the artifact.
Compared to the existing subtraction-based SAR algorithms, additional stimulus artifact
suppression of ~5.5 dB is achieved in this work.
VI
1. Introduction
1.1 Motivation
Recording electrical activity from the nervous system plays a significant role in
today’s neurophysiological studies. However, there are many technical challenges
involved in neuroelectrical recording, in particular when recording from and stimulating
the nervous system occur simultaneously and in close proximity in the same medium.
One of the most common problems in such a scenario is the presence of stimulus artifacts
(SA), interfering with extracellular neural recording. The extracellular electrodes record
the electric field induced by the ionic channel currents rather than measuring the
membrane potentials directly. Typically, the membrane potentials are in the millivolt
range, whereas the extracellular signals at the electrode sites are in the microvolt range
because the electric field decreases with distance away from the cell. Similarly, signal
loss also occurs in the reverse path. Therefore, extracellular stimulation requires voltages
at the electrode that are many orders of magnitude larger than those due to cellular
electrical activity [1]. The stimulation-induced voltages can overwhelm the sensitive
recording system, creating the stimulus artifact problem in closed-loop neuroprostheses.
The SA waveform is characterized by a large spike followed by a slowly decaying
tail whose amplitude, shape and time constant depend on the type of stimulator used,
stimulating and recording electrode characteristics, and the filtering characteristics of the
pre-amplification stages in the recording system [2]. Generally, the amplitude of SA is in
the millivolt range. On the other hand, the amplitude of neural action potentials is in the
microvolt range, so that there are many orders of magnitude difference between these two
signals, as illustrated in Fig. 1.1. Due to the large amplitude of the SA, it either saturates
1
the recording preamplifiers, or contaminates the recorded neural activity. This problem is
further exacerbated in high-frequency stimulation (HFS) applications such as deep brain
stimulation, because more of the recording becomes hampered by the SA and the
duration of the usable signal between successive stimulations becomes smaller. Therefore,
it is important to eliminate or heavily suppress the stimulus artifacts in neural recording.
Figure 1.1: The characteristics of a stimulus artifact (top) and a neural action potential
(bottom).
2
1.2 Background
Many techniques for eliminating or suppressing the stimulus artifacts in neural
recording have been reported in the literature, and the methods applied are highly
dependent on the particular biopotential being recorded and the conditions under which
the recordings are taking place. Many of these techniques use the same fundamental
principles for SA rejection or suppression. The two major categories of stimulus artifact
rejection methods are blanking and subtraction techniques.
1.2.1
SA Rejection with Blanking Techniques
Blanking techniques essentially disconnect the input terminal of the preamplifiers
from the recording interface during the stimulation period. Stimulation-synchronized
blanking of recording can be achieved by several methods. With a simple circuit design,
the amplifier input can be switched to ground whenever the SA appears [3]-[5], or can be
connected to the output of a sample-and-hold circuit to hold the data at a past value in the
duration of stimulation [6], [7]. Another method is to use a grounding “auto-zero” switch
to bleed off charge during the stimulation period, attempting to maintain some viable
recording during the stimulation period [8].
In general, these techniques are relatively simple, effectively reject the large SA
from the recorded signal, and are particularly useful in preventing amplifier saturation.
Unfortunately, these techniques also eliminate the useful information during the
stimulation
period
because
no
recording
can
be
performed
during
the
stimulation-synchronized blanking time, rendering blanking techniques quite ineffective
in HFS applications. Analog filtering is also used to eliminate high-frequency
3
components of the SA [9]. However, there typically exists a significant overlap in
frequency components between the desired neural signal and the interfering SA, reducing
the efficacy of a simple filtering technique for SA suppression. Digitally-controlled
implementation of the amplifier gain is suggested by [10] to suppress the SA. However, it
is also pointed out by the authors that this method is not always sufficient to effectively
remove artifacts. Amplifier slew rate limiting is a simple method that allows recording
during the stimulation period and keeps the residual SA level lower than the background
noise level, but can result in significant signal distortion as well [11]. Other methods
based on the recording electrode configuration, such as quasi- and true-tripolar cuff
electrode recording, have also been shown to reduce stimulation artifacts in peripheral
nerve recordings [12], [13]. Since blanking techniques do not allow recording of useful
neural activity during the stimulation period, many researchers have focused on
subtraction techniques for stimulus artifact rejection, as described below.
1.2.2
SA Rejection with Subtraction Techniques
The basic principle involved in most subtraction techniques requires subtracting a
reference SA template signal from the contaminated recorded data. Generating an
accurate reference waveform, faithfully representing the SA, is thus the main focus of
research in subtraction techniques and can be accomplished by various methods. An
uncontaminated SA as the reference signal can be obtained by simply recording from a
stimulation isopotential line that does not contain biopotential activity [14], or by
recording a subthreshold artifact where the stimulus intensity is reduced below the
threshold for nerve excitation [15].
These techniques occasionally suffer from the residual SA due to not taking into
4
account the time-varying nature and the nonlinearity of the SA. In order to solve the
problem of the SA nonlinearity, a method has been employed using Volterra series
expansion to model the nonlinearity of the recorded signal, and has been shown to
achieve a better SA suppression compared to other techniques [16], [17].
Digital averaging of multiple stimulation cycles also provides a representative SA
template signal, based on the assumption that the shape of the SA remains the same over
repeated stimulation periods [18], [19]. Some researchers have used a temporal average
of a train of pulses to account for gradual changes in artifact shape, in conjunction with
border extrapolation to alleviate reference contamination by stimulation-correlated
activity [20]. Other researchers have modified a poor reference estimate using an
adaptive filter or neural network in frequency or wavelet domain [21], [22].
In other works, a two-stage peak detection algorithm has been developed to
identify, isolate, and remove the SA by setting high and low threshold levels. However,
the limitation of this technique is that it is only applicable when the artifact signal and the
biopotential are non-overlapping [23]. A multichannel real-time SA suppression
technique is also proposed in which the SA is modeled by fitting polynomial or
exponential curves to the recorded data. This method is shown to perform well on a wide
range of artifact shapes [24]. Finally, a method of digitally replacing the artifact window
with an average of the uncontaminated signal is also proposed [25].
In conclusion, blanking techniques in most cases can entirely reject the SA in real
time and prevent amplifier saturation. However, they are incapable of retaining the useful
information during the stimulation period, which is especially problematic in HFS
applications. On the contrary, the primary advantage of most subtraction techniques is
that they retain useful information during the stimulation period. Unfortunately, these
5
techniques by themselves do not prevent amplifier saturation and tend to be more
complicated than blanking techniques, often requiring substantial digital signal
processing (DSP). Therefore, the majority of the subtraction techniques are currently
applied offline in software after the contaminated signal has already been recorded.
6
1.3 Research Objectives
The overall objective in this research project is to design and implement a
prototype stimulus artifact rejection (SAR) system in mixed-signal hardware that can
suppress the SA amplitude as much as possible, not only recovering the useful
biopotential information during stimulation periods but also functioning in real time to
prevent preamplifier saturation. Moreover, the SAR system should be functional with a
variety of biopotential recording systems without having to make significant hardware
modifications.
Specifically, the first goal of this project is to design the SAR block and
implement the algorithm in hardware, as described in detail in Chapter 2. The second
goal of this work is to integrate the SAR block with a simple neural recording front-end
and test the prototype system performance with neural biopotentials. Details of the
measurement results are described in Chapter 3.
7
2. System Design and Implementation
2.1 System Architecture
Figure 2.1 illustrates the traditional as well as the proposed neural recording
system architectures incorporating a SAR block. As shown in Fig. 2.1(a), for the
traditional implementation, the recorded neural signal is amplified, filtered, sampled,
digitized and stored. Once the data is fully recorded, it is further processed for offline
analysis with a SAR algorithm implemented on a PC [19], [20]. The performance of the
SAR algorithm in this case is limited by the sampling rate of the recorded data and the
ADC number of resolution bits. Furthermore, the front-end amplification stages should
be able to handle the large-amplitude SA without being saturated and the ADC needs to
have adequate number of resolution bits to quantize large amplitude levels of the SA as
well as small neural signal amplitudes.
In order to alleviate the aforementioned drawbacks, the neural recording system
shown in Fig. 2.1(b) is proposed in this work, where the SAR block is placed after the
first amplification stage. In this manner, the stimulus artifact is suppressed before being
fed to the second amplifier stage and the following ADC. Consequently, these stages only
need to handle the desired neural activity superimposed on much smaller residual
stimulus artifacts, not a combination of high-amplitude SA and low-amplitude neural
signal. Moreover, the neural spikes can be amplified to the full dynamic range of the
ADC, and recorded or transmitted through a wireless link to the PC for additional signal
processing. The SAR block should be modular and not limited by various experimental
system parameters (e.g., ADC sampling frequency or number of resolutions bits). The
SAR block parameters can be selected independently to optimize SA rejection results.
8
Figure 2.1: (a) Traditional neural recording system with offline implementation of the
SAR block in software. (b) The proposed system implementation with the SAR block
placed after the first amplification stage.
2.2 Design of SAR block
2.2.1
Basic Methodology
As described in the previous chapter, the main problem with neural recording and
stimulation within the same medium is the presence of large-amplitude stimulus artifacts
that can easily hamper recording during the stimulation periods. Therefore, the proposed
SAR algorithm is envisioned to execute during each stimulation period only, rather than
throughout the whole recording period. In a system incorporating both stimulation and
recording units, the occurrence time instances of stimulus pulses are typically controlled
by a certain trigger signal, which can be used to indicate the start time for the execution
of the SAR algorithm.
Given the fact that the shape of the stimulus artifact does not change rapidly with
time from one stimulus period to another, a reference signal for faithful representation of
the SA can be estimated by sampling the input signal (i.e., signal containing both the SA
and the randomly superimposed neural activity) during multiple stimulation cycles
9
followed by averaging. This basic SAR methodology is illustrated in Fig. 2.2 below,
where the desired neural activity (trace C) is fully recovered after subtracting the
estimated SA reference signal (trace B) from the contaminated input signal (trace A) that
contains a large-amplitude SA as well as a small neural action potential at t = 80 ms.
Figure 2.2: a) Input signal containing both a large-amplitude SA and a small neural spike.
b) Estimated SA reference signal for subtraction. c) Recovered neural spike after SA
subtraction.
10
2.2.2
SAR Block Architecture
Figure 2.3 depicts the system architecture of the proposed SAR block, containing
an ADC, memory, digital control unit, averaging circuitry, DAC, and an analog adder.
The digital control unit generates the clock signals for the SAR block and is controlled by
the stimulus trigger signal, as described previously.
During each stimulation period when the trigger signal is high, the input signal is
sampled and digitized by the ADC. The SA template signal is then generated by the
averaging method and sent to the DAC. This signal is then subtracted from the input
signal by the adder to obtain the output signal that contains the desired neural activity as
well as some low-amplitude residual stimulus artifacts.
Figure 2.3: Architecture of the proposed stimulus artifact rejection block.
11
Figure 2.4 shows the flow chart diagram of the proposed SAR algorithm. For each
stimulation cycle, the SAR algorithm executes when the trigger signal to the control unit
is high. The data analysis steps are listed as follows.
1. Read the input signal.
2. Convert the analog input signal to digital data for further processing.
3. Send the averaged data of previous cycle out by DAC while waiting for ADC.
4. Check operation of ADC.
5. If ADC work is done, then obtain a SA template signal by averaging.
6. Subtract the estimated template signal from the input signal by adder.
7. Obtain the output signal.
In step 2, it is rather inefficient if the rest of the commands are executed only after
the ADC conversion is completed. Therefore, in order to minimize the data processing
time, the stored averaged data of the previous cycle is sent out by the DAC while waiting
for the digitization of the current sampled data by the ADC.
12
Figure 2.4: Flow chart diagram of the proposed stimulus artifact rejection algorithm.
13
2.2.3
SAR Algorithm Parameters
As shown in Fig. 2.3, there are several important parameters in the present work that
can affect the performance of the SAR algorithm once implemented in hardware, namely,
the sampling frequency and the number of resolution bits in the ADC and DAC as well as
the size and word length of the memory.
The stimulus artifact typically has a large slope during the rise and fall time
instances, which makes the choice of the ADC sampling rate crucial to faithfully
represent the SA during these transitional periods in each stimulation cycle. Figure 2.5
illustrates a simplified example of how the ADC sampling rate can affect the overall
performance of the SAR algorithm. In this case, the input signal is a 1-Hz sinusoidal
waveform plotted as the dashed green trace. The blue trace is the digitized signal and the
red trace is the output signal obtained after subtracting the blue trace from the green trace.
The sampling rates of the input signal in the top and bottom plots are 50 and 25 Hz,
respectively. As clearly seen, the resulting output signal with a 25-Hz sampling rate
exhibits residual amplitudes that are nearly three times larger than those obtained with
higher sampling rate. It is therefore expected that higher sampling rates will lead to a
more faithful representation of the stimulus artifact especially during the rapidly varying
portions of the waveform and thus better overall performance in the SAR algorithm.
From a practical point of view, however, higher sampling rates also lead into larger
memory size and higher power consumption in hardware implementation of the system.
14
Figure 2.5: Simplified illustration of sampling rate effect on the SAR algorithm
performance. Sampling rates are set to 50 and 25 Hz in the top and bottom plots,
respectively.
The number of bits in the ADC affects the resolution of the data. Higher number
of resolution bits leads into more accurate estimation of the large-amplitude stimulus
artifacts. Nevertheless, the number of bits cannot be arbitrarily large due to practical
issues such as the resulting memory size in hardware implementation as well as on-chip
realization in the future.
The required memory size is affected by the sampling rate, the duration of the
stimulus artifact, and the number of resolution bits. Obviously, larger memory size allows
higher sampling rates, leading to better SA rejection results. Nonetheless, the area of the
memory block can also be a major challenge in future system-on-a-chip (SOC)
implementation of the proposed SAR algorithm.
15
2.2.4
Averaging Method
As described in Chapter 1, there are various methods for producing the stimulus
artifact template signal for subtraction purposes. The most common method is the
conventional direct averaging, which is based on calculating the mean value of multiple
cycles of data. Data recorded in each stimulation cycle for N consecutive cycles are
stored in the memory, and the mean value is calculated according to Equation 2.1, where
the superscript, k, identifies the kth data point in a cycle and the subscript, i, identifies the
number of cycles. The averaged value obtained in this manner is more precise as
compared to other methods. However, this method requires longer computational time to
produce the output.
N
∑X
X ik+1 =
k
i
i =1
Equation 2.1
N
Weighting is the procedure to modulate the distributions in the sample data to
approximate those of the population from which it is drawn. In this method, previously
averaged data have higher weighting factors, while the incoming SA data are weighted
lower. Finally, these weighted data are added together in order to generate an averaged
signal for the next cycle as shown by Equation 2.2. The resulting weighting effect
depends on the weighting factors, w, and the number of data points, N. Nevertheless,
some data bits have to be thrown away to perform division in this method, thereby some
meaningful data will be lost and it can lead to a high approximation error.
X ik+1 =
w
N −w k
( X ik ) +
( X i −1 )
N
N
Equation 2.2
Another method is based on comparison of each data point. As shown by
Equation 2.3, if the input signal is higher than the previous averaged value, the averaged
16
value is increased by an increment M . On the other hand, if the input signal is lower
than the previous averaged value, the latter is decreased by M . The value of M can be
used to control the averaging speed. Increasing M results in a faster response time for
the system at the expense of decreased resolution in the averaged value. Therefore, the
value of M cannot be arbitrarily high when resolution is considered. In order to get more
accurate estimates, one cannot achieve very fast response times using this method.
 X k + M ; X ik > X ik−1 
X ik+1 =  i −k1
k
k 
 X i −1 − M ; X i < X i −1 
Equation 2.3
For the implementation of the SAR algorithm in this work, the comparison method
is selected for simplicity in programming. However, in order to improve its performance,
a modified version of the method is developed and described later.
17
2.3 System Simulation and Hardware Implementation
2.3.1
System Simulation of SAR Algorithm
MATLABTM is used to verify the system-level functionality of the proposed SAR
algorithm with the “comparison” method for averaging as described previously. The
input data used for system simulation was previously recorded from a marine mollusk
Aplysia californica with a sampling frequency of 20 kHz after 10-Hz current-based
stimulation of the nervous system. A typical raw stimulus artifact and neural spike in the
recorded data had amplitude levels of ~4 mVpp and ~150 µVpp, respectively. A 15-s
portion of this raw input data is shown as the top trace in Fig. 2.6 (trace A). Prior to being
fed to the SAR algorithm for processing, the data were amplified in MATLABTM by a
gain of 60 dB, representing a typical gain for Amplifier 1 in Fig. 2.1. A 10-Hz trigger
signal was also generated as shown in the second trace in Fig. 2.6 (trace B). System
parameters such as the ADC number of resolution bits and sampling frequency were set
to 8 and 20 kHz, respectively. The memory length was selected to be 360 samples (8 bits),
given stimulus artifact duration of ~18 ms.
As shown in the third trace of Fig. 2.6 (trace C), the SA template signal achieved
steady-state status after ~10 s, and the output signal (trace D) was then obtained via
subtraction of the template. Figure 2.7 shows a 400-ms expanded portion of the simulated
data, revealing that the microvolt-range neural spikes could indeed be recovered in
between successive stimulus artifacts. The amplitude of the residual stimulus artifacts
were ~50 mVpp (50 µVpp when referred to the input, representing a suppression of more
than 38 dB). With 6 and 10 bits of resolution in the ADC, the resulting input-referred
residual stimulus artifacts were found to be 200 µVpp and <10 µVpp. Although the
18
residual stimulus artifacts are practically negligible with a 10-bit ADC, an 8-bit ADC is
selected in the hardware implementation of the system as will be described later. The
MATLABTM code for the system-level simulation is enclosed in Appendix A.
Figure 2.6: System-level simulation results for the SAR block.
19
Figure 2.7: An expanded view of the simulated data in Fig. 2.6.
2.3.2
Hardware Implementation of SAR Algorithm
Compared to the MATLABTM simulation running on a PC, the computational
resources in an implantable microcontroller are much more limited. Therefore, one would
expect to have residual stimulus artifact peaks with higher amplitudes compared to the
results obtained in MATLABTM simulation. The implementation of the SAR algorithm in
a microcontroller provides for real-time signal processing. However, it is necessary to
modify the algorithm in order to obtain satisfactory performance given the limited
computational resources available in a closed-loop implantable device.
In this work, the SAR algorithm is implemented using Assembly language in an
8-bit microcontroller with 10-bit built-in ADC (PIC16F688 from Microchip) that has 12
I/O pins, adequate for the operation of the algorithm. There are 256 8-bit registers
20
available in the memory block. The maximum clock frequency of this microcontroller is
20 MHz (i.e., 5 million instructions per second). The clock frequency, Fosc, is selected as
8 MHz and the ADC clock is set by Fosc/16.
As previously discussed in Section 2.2.3, the sampling rate is a crucial factor in
generating the SA template signal in order to suppress the residual peaks especially at the
rise and fall time instances of the artifact where it has a large slope. As a result, a
pseudo-higher sampling rate method is employed in hardware implementation in order to
increase the effective sampling rate without the requirement for a larger-size memory. In
this technique, the mean value of two consecutive estimated points is also calculated and
sent out by the DAC. As a result, the effective sampling rate is twice as higher.
Nonetheless, the memory size needed actually remains the same.
There are three memory banks in this microcontroller and a total of 256 bytes are
available as general-purpose registers. In this implementation of the SAR algorithm, 250
bytes are used in the memory with 6 bytes unused and available for other tasks. Each
register is accessed through file-select register (FSR). The indirect file (INDF) buffer is
not a physical register in the microcontroller. Any instruction using the INDF register
actually accesses the data pointed to by the FSR. Figure 2.8 shows the data flow chart and
memory arrangement for implementation of the SAR algorithm in the microcontroller.
The Assembly code programmed in the PIC16F688 microcontroller is enclosed in
Appendix B.
(a)
In the current cycle, FSR points to the first address while the first incoming
data, X i1 , is being sampled and converted to a digital number by the ADC. Also,
21
X i1−1 is loaded to Buffer 1 for calculating the middle estimated point.
(b)
Next, FSR is moved to the second register and loads X i2−1 for calculating the
mean value of X i1−1 and X i2−1 (i.e., X im−112 ) and saving it back in Buffer 1 to be
sent out by the DAC.
(c)
The DAC buffer sends X i1−1 out and loads X im−112 into its register and updates
the output.
(d)
This is followed by sending X im−112 out and loading X i2−1 into the DAC buffer.
(e)
The completion of ADC conversion is checked. If ADC work is not finished, then
it waits for the completion to occur. If ADC work is completed, then it starts to
calculate the estimated averaged data based on the comparison method (i.e.,
Equation 2.3). In order to simplify the programming, only the 8 most significant
bits (MSB) of the ADC buffer are read for averaging. Once the averaged data, X i1 ,
is calculated, it is saved to the first register to be sent out in the following
operation cycle.
(f)
FSR moves to the second address and the same process as described above is
repeated.
22
Figure 2.8: Data flow chart and memory arrangement for the implementation of the SAR
algorithm in the microcontroller.
23
2.3.3
Hardware Implementation of SAR System
Figure 2.9 shows the schematic diagram for the hardware implementation of the
SAR system. As described previously, An 8-bit microcontroller (PIC16F688 from
Microchip) is programmed to execute the SAR algorithm. The microcontroller is
interfaced with a 10-bit DAC (LTC1661 from Linear Technology) to convert the digitized
SA template signal into an analog waveform for subtraction. The double-buffered input
logic of the DAC provides simultaneous update capability.
An operational amplifier (OPA277 from Texas Instruments) is utilized for
subtraction. The op-amp gain is set by the ratio of R3/R1. The input signal applied to the
non-inverting terminal (Vin+) is essentially the output signal from the preceding
pre-amplification and filtering stages (see Fig. 2.1(b)). The estimated SA template signal
from the DAC output is fed to the inverting terminal of the op-amp (Vin-). Therefore, the
op-amp output signal can be derived from the following:
Vout =
R3
× (Vin + − Vin − )
R1
Equation 2.4
Figure 2.9: Schematic diagram of the hardware implementation for the SAR system.
24
Figure 2.10 shows the schematic block diagram of the front-end neural recording
and filtering circuitry. The amplified and filtered signal at the output of this block is fed
as the input signal to the SAR system depicted above. The front-end recording circuitry
utilizes an instrumentation amplifier (LT1167 from Linear Technology) for the INAmp
circuit block. This is a low-noise wideband amplifier with very low input bias current,
exhibiting very high input impedance. The filtering block consists of cascaded 2nd-order
lowpass and 2nd-order Sallen-Key highpass filter stages, exhibiting a bandpass response
from 0.2-10 kHz with unity gain. The values for all the passive components in the
front-end are listed below:
C1 = 0.33 µF , R1 = 2 kΩ , R2 = 2.74 kΩ , R3 = 19.6 kΩ , C 2 = 1 nF , C 3 = 4.7 nF
C 4 = 0.1 µF , C 5 = 47 nF , R4 = 15 kΩ , R5 = 5.1 kΩ .
Figure 2.10: Schematic block diagram of the front-end neural recording circuitry,
comprising an instrumentation amplifier and two cascaded filtering stages.
Figure 2.11 shows the simulated frequency response of the front-end recording
circuitry in HSPICETM. An ac gain of 60 dB is achieved at 1 kHz with a bandpass
frequency response from 0.25-7.8 kHz. The front-end successfully rejects dc components
in the input signal as well, as shown in the top trace of Fig. 2.12. A 1-kHz, 100-µVpp
sinusoidal signal on a dc level of 11 mV is applied to the input. The amplifier
25
successfully rejects the dc component in the input and amplifies only the ac component
with a gain of 60 dB (bottom trace).
Figure 2.11: Simulated frequency response of the front-end neural recording circuitry.
Figure 2.12: Simulated ac response of the front-end neural recording circuitry.
26
3. Prototype System Measurement Results
3.1 Overview
Figure 3.1 shows a photograph of the hardware implementation of the proposed
SAR block on a custom-designed printed-circuit board, operating from ±2.5-V power
supply. The input signal for the SAR block was generated in MATLABTM using one
stimulus artifact and one neural spike that were previously recorded in vivo. In order to
generate an analog input waveform from the data in MATLABTM, the data was first read
by LabVIEW from the PC into a data acquisition card (DAQ) and then fed to the SAR
hardware as an analog input waveform. In order to ensure that the low-amplitude data
would not be corrupted by noise during this transfer, it was read into the DAQ with a gain
of ~72 dB (4000) set in software. At the output of the DAQ and prior to feeding the data
into the SAR block, it was attenuated by the same factor to obtain the original amplitude
levels for the SA and neural spike. Some of the system features and measured
performance characteristics are listed in Table 3.1.
Figure 3.1: Photograph of the custom-designed hardware implementation of the SAR
block.
27
Table 3.1: System Features and Measured Performance Characteristics
Front-End Recording Circuitry
Gain @ 1 kHz
f-3dB
f+3dB
60.47 dB
260 Hz
7.9 kHz
SAR Block
ADC # of Bits
DAC # of Bits
Sampling Rate
Memory Size
8
8
20 kHz
250 bytes
Total System
Power Supply
Total Power Dissipation
±2.5 V
~35 mW
3.2 Measurement Results
Four test input signals are used in system measurement. Figures 3.2(a) and 3.2(b)
show two different stimulus artifact waveforms used in constructing the input signal,
which were previously recorded in vivo. Three different input signals were constructed
from these stimulus artifacts and a ~150-µVpp neural spike, which was also recorded in
vivo. The fourth test input signal is a snapshot of pre-recorded neural activity from
Aplysia californica. The four signals are described as follows:
Test Signal 1:
Generated with the SA in Fig. 3.1(a) with an amplitude level of 2.5
mVpp.
Test Signal 2:
Generated with the SA in Fig. 3.1(a) with an amplitude level of 4
mVpp.
Test Signal 3:
Generated with the SA in Fig. 3.1(b) with an amplitude level of 3.9
mVpp.
28
Test Signal 4:
A snapshot of pre-recorded neural activity from Aplysia californica
containing 0.4-mVpp stimulus artifacts
Figure 3.2: Two different stimulus artifact waveforms used in generating the input signal
for the SAR block.
Measured waveforms of the prototype system with Test Signal 1 as the input are
shown in Fig. 3.3. The top trace depicts the amplified analog input that is fed to the SAR
block. A 500-ms portion of the data, as shown, contains five stimulus artifacts occurring
every 100 ms (i.e., at 10 Hz) with much smaller neural action potentials randomly
superimposed on the artifact data. The middle trace depicts the SA reference signal
estimated by the SAR block, and the bottom trace shows the output data after subtracting
the SA reference signal.
Figure 3.4 shows an expanded view of a single stimulus artifact in this experiment.
As can be seen in the bottom trace, there are only two residual peaks left from the
stimulus artifact at its rise and fall time instances where it is rapidly varying with time.
29
The larger residual signal has amplitude of ~0.87 Vpp, exhibiting a stimulus artifact
rejection of ~9.6 dB at the edges. In the slowly varying portions of the artifact including
its decaying tail, the artifact is fully removed and the neural spike is recovered from the
tail.
Figures 3.5 and 3.6 show the same measurement results with Test Signal 2 as the
input waveform to the SAR block. The same performance as before is achieved with the
larger stimulus artifact residual spike having amplitude of ~1.3 Vpp, exhibiting a SA
rejection of ~10.2 dB at the edges. A neural action potential is again fully recovered from
the slowly decaying tail of the artifact.
Figures 3.7 and 3.8 show the same measurement results with Test Signal 3 as the
input waveform to the SAR block. The amplitude of the stimulus artifact residual signal
after subtraction is ~0.72 Vpp, exhibiting a suppression of ~15.1 dB at the edges. Given
that the stimulus artifact in Fig. 3.2(b) has much slower transitions with time compared to
its counterpart in Fig. 3.1(a), it is quite expected that better stimulus artifact rejection
would be achieved in this case.
Figures 3.9 and 3.10 show the same measurement results using Test Signal 4 as
the input waveform to the SAR block. A 2-s portion of the input data, containing five
stimulus artifacts at 2.5 Hz together with smaller neural action potentials randomly
occurring throughout the data, is shown in the top trace of Fig. 3.9. Due to slight
variations in the shape of the stimulus artifact waveforms and the timing of stimulation
occurrence from cycle to cycle, the system exhibits a suppression performance of only
~1.6-6 dB at the edges. However, despite the two residual peaks, the slowly varying
portions of the stimulus artifact are still successfully eliminated and the neural action
30
potentials superimposed on the decaying tail of the artifact are fully recovered as shown
in Fig. 3.10.
Figure 3.11 illustrates the measured waveforms from the SAR block with Test
Signal 2 as the input at four different time instances during the operation. The plots A
through D correspond to timestamps of 1, 3, 7, and 9 seconds after the operation starts. It
takes ~9 seconds to reach steady state and achieve a stable reliable stimulus artifact
template signal for subtraction purposes, as shown in plot D. Finally, Fig. 3.12 compares
the measured artifact suppression results, using Test Signal 2 as the input, of the original
SAR algorithm with that of the proposed SAR algorithm in hardware implementation
using the pseudo-higher sampling rate concept. From the peak-to-peak amplitude of the
larger stimulus artifact residual spike, it can be seen that the implemented algorithm
achieves ~5.5 dB higher suppression.
31
Figure 3.3: System measurement results with Test Signal 1. The top trace depicts the
amplified signal fed to the SAR block that contains five stimulus artifacts (occurring at
10 Hz) and randomly positioned neural spikes. The middle trace depicts the estimated
stimulus artifact template signal. The bottom trace shows the SAR block output after
subtraction where neural spikes are recovered in between the artifacts.
Recovered
Neural Spike
Residual SA
Figure 3.4: An expanded view of the three signals in Fig. 3.3, depicting on the bottom
trace the two residual stimulus artifacts as well as a neural spike recovered from the
decaying tail of the artifact.
32
Figure 3.5: System measurement results with Test Signal 2. The top trace depicts the
amplified signal fed to the SAR block that contains five stimulus artifacts (occurring at
10 Hz) and randomly positioned neural spikes. The middle trace depicts the estimated
stimulus artifact template signal. The bottom trace shows the SAR block output after
subtraction where neural spikes are recovered in between the artifacts.
Figure 3.6: An expanded view of the three signals in Fig. 3.5, depicting on the bottom
trace the two residual stimulus artifacts as well as a neural spike recovered from the
decaying tail of the artifact.
33
Figure 3.7: System measurement results with Test Signal 3. The top trace depicts the
amplified signal fed to the SAR block that contains five stimulus artifacts (occurring at
10 Hz) and randomly positioned neural spikes. The middle trace depicts the estimated
stimulus artifact template signal. The bottom trace shows the SAR block output after
subtraction where neural spikes are recovered in between the artifacts.
Figure 3.8: An expanded view of the three signals in Fig. 3.7, depicting on the bottom
trace the two residual stimulus artifacts as well as a neural spike recovered shortly after
the decaying tail of the artifact.
34
Figure 3.9: System measurement results with Test Signal 4. The top trace depicts the
amplified signal fed to the SAR block that contains five stimulus artifacts (occurring at
2.5 Hz) and randomly occurring neural spikes. The middle trace depicts the estimated
stimulus artifact template signal. The bottom trace shows the SAR block output after
subtraction where neural spikes are recovered in between the artifacts.
Figure 3.10: An expanded view of the three signals in Fig. 3.9, depicting on the bottom
trace the two residual stimulus artifacts as well as a neural spike recovered from the
decaying tail of the artifact.
35
(a =1 second)
(b = 3 seconds)
(c = 7 seconds)
(d = 9 seconds)
Figure 3.11: Measured waveforms of the SAR block with Test Signal 1 as the input at 4
different timestamps during the operation. It takes ~9 seconds to reach steady state in plot
D.
36
(a) Suppression with original SAR algorithm
(b) Suppression with proposed SAR algorithm
Figure 3.12: Stimulus artifact rejection results (with Test Signal 2) with a) the original
SAR algorithm and b) the proposed SAR algorithm in hardware implementation using the
pseudo-higher sampling rate concept. Additional suppression of ~5.5 dB is achieved.
37
4. Conclusion and Future Work
In this work, a stimulus artifact rejection algorithm based on the subtraction
technique is first simulated using the MATLABTM program to determine the appropriate
design parameters, and is next successfully implemented in an 8-bit microcontroller using
the Assembly language. The microcontroller has been interfaced with a front-end neural
recording amplifier on a custom-designed printed-circuit board. The performance of the
entire SAR block has been verified and characterized with input signals, containing
actual stimulus artifact waveforms with various shapes and amplitudes.
Compared with the existing template subtraction methods for artifact rejection
[19], [20], the work proposed herein can suppress large-amplitude stimulus artifact
signals in real time (online) and recover useful neural information that might be
superimposed on the slowly varying portions of the artifact.
In general, subtraction-based techniques by themselves do not alleviate the
amplifier saturation problem. However, the amplifier gain or stimulus intensity is
typically adjusted to permit non-saturated recording of the full-scale stimulus artifact and
the superimposed neural spikes.
From the test results, it is apparent that some residual stimulus artifact signal will
still remain after subtraction, primarily at the rise and fall time instances of the artifact
where it is rapidly changing with time. In future work, a possible solution for this
problem could be to implement an adaptive sampling rate, which means to have a high
sampling rate for the rapidly varying portions of the artifact for a more faithful
representation in the template, and a lower sampling rate for the rest of the artifact
(slowly varying portions) to decrease the required memory size.
38
5. Appendices
Appendix A
% MATLABTM Code for Simulation of the SAR Algorithm
close all;
clear all;
%load signal_1202.mat;
%load signal_0218_4mV.mat;
load signal_onepeak_4mV.mat;
%------------------system parameters----------------------gain=1000;
% Define gain
num_bits=8;
% Define ADC number of bit
num_reg=250;
% Define memory length
smp_skip=0.5;
% Define sample frequency
%num_reg=1200
%----------------------------------------------------------%------------------initial condition-----------------------trig=-2.5;
%Initial trigger signal
cnt=0;
signal_record=zeros(1,num_reg);
signal_record1=zeros(1,num_reg);
signal_template=zeros(1,num_reg);
signal_tem0=[];
signal_out=[];
signal_out1=[];
signal_out_add=[];
signal_tem=[];
signal_tem_add=[];
cnd=1;
signal_tem0(1:1005000)=0;
signal=signal(1:smp_skip:length(signal));
sc_signal=sc_signal(1:smp_skip:length(sc_signal));
signal_tem0=signal_tem0(1:smp_skip:length(signal_tem0));
%------------------------------------------------------------
%------------------SAR algorithm----------------------------while cnd==1
cnt=cnt+1;
signal_out_add=[signal_out_add signal(cnt)*gain];
signal_tem_add=[signal_tem_add signal_tem0(cnt)];
new_trig=sc_signal(cnt);
if and(trig==-2.5,new_trig==2.5),
%Record input signal in non-stimulation periods
%When trigger signal is high, starts SAR algorithm
signal_out=[signal_out signal_out_add];
signal_tem=[signal_tem signal_tem_add];
signal_out_add=[];
signal_tem_add=[];
for cnt2=1:num_reg;
adc_out1=(round((1+gain*signal(cnt+cnt2))*2^((num_bits-1)))); %Get the digitized data from ADC
adc_out=(adc_out1/2^(num_bits-1))-1;
39
if (adc_out>signal_record(cnt2))
% Averaged methods
signal_record(cnt2)=signal_record(cnt2)+(5/2^(num_bits-1));
elseif
(adc_out<signal_record(cnt2))
signal_record(cnt2)=signal_record(cnt2)-(5/2^(num_bits-1));
else
signal_record(cnt2)=signal_record(cnt2);
end;
% signal_record(cnt2)=(adc_out+31*signal_record(cnt2))/32;
signal_record1(cnt2)=(signal(cnt+cnt2))*gain;
signal_tem(cnt2)=[signal_record(cnt2)];
%Record input signal in stimulation period
%Record template signal in stimulation period
end;
cnt=cnt+num_reg;
signal_out=[signal_out signal_record1-signal_record];
signal_tem=[signal_tem signal_record];
%signal_out1=[ signal_out1 signal_record];
(cnt/length(signal))*100
if ((cnt/length(signal))*100)>80,
cnd=0;
end;
end;
trig=new_trig;
end;
signal_out=[signal_out zeros(1,length(signal)-length(signal_out))];
signal_tem=[signal_tem zeros(1,length(signal)-length(signal_tem))]
%-------------------------------------------------------------
%------------------Plot Results------------------------------%signal=signal(400000:440000);
%sc_signal=sc_signal(400000:440000);
%signal_tem=signal_tem(400000:440000);
%signal_out=signal_out(400000:440000);
timestep=(1:length(signal))/40000;
figure(1);
subplot (4,1,1);
plot (timestep,signal);
subplot (4,1,2);
plot (timestep,sc_signal);
subplot (4,1,3);
plot (timestep,signal_tem);
subplot (4,1,4);
plot(timestep,signal_out);
40
%Output signal = input signal - template
Appendix B
; Implementation of the SAR Algorithm in a PIC Microcontroller using Assembly
; Definitions
STATUS
INDF
FSR
OSCCON
IRP
equ
equ
equ
equ
equ
0x03
0x00
0x04
0x8F
0x07
;General Definitions
ADCON0
ADCON1
ANSEL
TRISA
ADRESH
ADRESL
GO
PORTA
equ
equ
equ
equ
equ
equ
equ
equ
0x1F
0x9F
0x91
0x85
0x1E
0x9E
0x01
0x05
;Port Definitions
TMR0
OPTION_REG
INTCON
T0CS
PSA
T0IF
equ
equ
equ
equ
equ
equ
0x01
0x81
0x0B
0x05
0x03
0x02
;Timer0
SCK
DIN
LD
equ
equ
equ
0x05
0x01
0x04
;DAC Ports
DAC_Data
ADC_Data
Action_Cnt
Buffer1
Delaycnt
Trig_Pin
equ
equ
equ
equ
equ
equ
0x20
0x21
0x22
0x23
0x24
0x02
;----------------------------------------------------------------------------------------; Initializing
;
ORG
0x00
CLRF
STATUS
BANKSEL
BSF
BSF
BSF
OSCCON
OSCCON,6
OSCCON,5
OSCCON,4
BANKSEL
MOVLW
MOVWF
ADCON1
B'01010000'
ADCON1
; ADC Clock Settings
;ADC, clock: Frc(111), Fosc/16(101), Fosc/32(010)
;
BANKSEL
BSF
BSF
TRISA
TRISA,0
TRISA,2
; Port Settings
;Set RA0 as input
;Set RA2 as Trig input
BCF
BCF
BCF
BCF
TRISA,4
TRISA,5
TRISA,1
TRISA,3
;Set DAC Ports as Output
;
;
;
;Initializing Status Reg.
;Initializing Oscillator. (8MHz)
41
;
BANKSEL
BSF
BCF
ANSEL
ANSEL,0
ANSEL,2
;Set Analog/Digital Inputs
;Set RA0 as analog input
;Set RA2 as digital input
BCF
BCF
BCF
BCF
ANSEL,3
ANSEL,4
ANSEL,5
ANSEL,1
;Digital for others
;
;
;
BANKSEL
MOVLW
MOVWF
ADCON0
B'00000001'
ADCON0
; DAC
;Left justify,
;Vdd Vref, AN0, On
BANKSEL
BCF
BSF
OPTION_REG
OPTION_REG,
OPTION_REG,
T0CS
PSA
BCF
BCF
BCF
OPTION_REG,
OPTION_REG,
OPTION_REG,
0x00
0x01
0x02
; Timer
Main:
BANKSEL
Wait_Loop:
BTFSC
GOTO
PORTA, Trig_Pin
Wait_Loop
;Positive Edge Trig Detect
;
;
Wait_Loop1:
BTFSS
GOTO
PORTA, Trig_Pin
Wait_Loop1
;
;
;
0x59
Action_Cnt
0x26
FSR
; Initialize Action Counter (Bank0)
; and FSR
;
;
MOVLW
MOVWF
MOVLW
MOVWF
PORTA
Action_Loop0:
; Bank0 Loop
BANKSEL
MOVLW
MOVWF
BCF
TMR0
0x38
TMR0
INTCON,T0IF
; Set The Timer
;
;
;
BANKSEL
BSF
PORTA
PORTA, LD
; Send out DAC Data (load)
;
nop
nop
nop
; Phase delay adjustment
;
;
BANKSEL
BSF
ADCON0
ADCON0,GO
;Start ADC conversion
;
BANKSEL
MOVF
MOVWF
Buffer1
INDF, 0
Buffer1
;
;
BANKSEL
INCF
MOVF
DAC_Data
FSR,1
INDF,0
; Get the Next Data
;
;
42
;------------------------ADDWF
;
INCF
;
BCF
RRF
Buffer1, 1
Buffer1, 1
STATUS, 0x00
Buffer1
; clear carry bit
; Averaged by 2
MOVF
MOVWF
Call
;------------------------;
MOVLW
;
MOVWF
;Delay1:
;
DECFSZ Delaycnt
;
goto Delay1
Buffer1, 0
DAC_Data
DAC_Out
;
;
;
BSF
MOVF
MOVWF
DECF
Call
PORTA, LD
INDF, 0
DAC_Data
FSR,
1
DAC_Out
MOVLW
MOVWF
0x35
Delaycnt
DECFSZ
goto
Delaycnt
Delay2
BANKSEL
BTFSC
GOTO
ADCON0
ADCON0,GO
$-1
;ADC Conversion Check
;Is conversion done?
;No, test again
BANKSEL
MOVF
MOVWF
ADRESH
ADRESH,W
ADC_Data
;Read Higher 8 bits of ADC
;
;
MOVF
SUBWF
BTFSC
DECF
BTFSS
INCF
ADC_Data,W
INDF, 0
STATUS, 0
INDF, 1
STATUS, 0
INDF, 1
; Averaging Code
;
;
;
;
;
MOVF
SUBWF
BTFSC
DECF
BTFSS
INCF
ADC_Data,W
INDF, 0
STATUS, 0
INDF, 1
STATUS, 0
INDF, 1
; Averaging Code
;
;
;
;
;
MOVF
SUBWF
BTFSC
DECF
BTFSS
INCF
ADC_Data,W
INDF, 0
STATUS, 0
INDF, 1
STATUS, 0
INDF, 1
; Averaging Code
;
;
;
;
;
MOVF
SUBWF
BTFSC
DECF
BTFSS
ADC_Data,W
INDF, 0
STATUS, 0
INDF, 1
STATUS, 0
; Averaging Code
;
;
;
;
;
;
;Delay2:
;
;
; buffer1=buffer1+DAC_Data
0x35
Delaycnt
;
;
;
;
;and Send DAC Data Out (Without load)
43
INCF
INDF, 1
;
MOVF
SUBWF
BTFSC
DECF
BTFSS
INCF
;---------------------------------BANKSEL
BTFSS
GOTO
ADC_Data,W
INDF, 0
STATUS, 0
INDF, 1
STATUS, 0
INDF, 1
; Averaging Code
;
;
;
;
;
INTCON
INTCON,T0IF
$-1
; Check The Timer
;
;
INCF
DECFSZ
GOTO
;-------------------------MOVLW
MOVWF
MOVLW
MOVWF
;--------------------------
FSR,1
Action_Cnt
Action_Loop0
; Change Counter and Memory
;
; and go back to Action Loop
0x4F
Action_Cnt
0xA0
FSR
;Initialize Action Counter (Bank1)
;and FSR
;
;
Action_Loop1:
; Bank1 Loop
BANKSEL
MOVLW
MOVWF
BCF
TMR0
0x38
TMR0
INTCON,T0IF
; Set The Timer
;
;
;
BANKSEL
BSF
PORTA
PORTA, LD
;Send out DAC Data (load)
;
nop
nop
nop
;Phase delay adjustment
;
;
BANKSEL
ADCON0
BSF
ADCON0,GO
BANKSEL
0x0A
MOVF
INDF, 0
BANKSEL
ADCON0
MOVWF
Buffer1
;----------------------------------------------------------------BANKSEL
0xA0
INCF
FSR,
1
MOVF
INDF, 0
;------------------------BANKSEL
Buffer1
ADDWF
Buffer1,1
;
BCF
STATUS, 0x00
RRF
Buffer1,1
MOVF
MOVWF
Call
;------------------------BANKSEL
MOVF
BANKSEL
MOVWF
BSF
; Start ADC conversion
;
; Select Bank1
;
; Select Bank0
;
; Select Bank1
; Get the Next Data
;
;
; buffer1=buffer1+DAC_Data
; clear carry bit
; Averaged by 2
Buffer1, 0
DAC_Data
DAC_Out
;
;
;
0x0A
INDF, 0
DAC_Data
DAC_Data
PORTA, LD
; Select Bank1
;
; Select Bank0
;
;
44
BANKSEL
0xA0
DECF
FSR,
1
BANKSEL
DAC_Data
Call
DAC_Out
;--------------------------------------------------------------BANKSEL
ADCON0
BTFSC
ADCON0,GO
GOTO
$-1
; Select Bank1
;
; Select Bank0
;and Send DAC Data Out (Without load)
;ADC Conversion Check
;Is conversion done?
;No, test again
BANKSEL
MOVF
MOVWF
ADRESH
ADRESH,W
ADC_Data
;Read Higher 8 bits of ADC
;
;
MOVF
BANKSEL
SUBWF
BTFSC
DECF
BTFSS
INCF
BANKSEL
ADC_Data,W
0xA0
INDF, 0
STATUS, 0
INDF, 1
STATUS, 0
INDF, 1
0x20
; Averaging Code
; Select Bank1
;
;
;
;
;
MOVF
BANKSEL
SUBWF
BTFSC
DECF
BTFSS
INCF
BANKSEL
ADC_Data,W
0xA0
INDF, 0
STATUS, 0
INDF, 1
STATUS, 0
INDF, 1
0x20
; Averaging Code
; Select Bank1
;
;
;
;
;
MOVF
BANKSEL
SUBWF
BTFSC
DECF
BTFSS
INCF
BANKSEL
ADC_Data,W
0xA0
INDF, 0
STATUS, 0
INDF, 1
STATUS, 0
INDF, 1
0x20
; Averaging Code
; Select Bank1
;
;
;
;
;
MOVF
BANKSEL
SUBWF
BTFSC
DECF
BTFSS
INCF
BANKSEL
ADC_Data,W
0xA0
INDF, 0
STATUS, 0
INDF, 1
STATUS, 0
INDF, 1
0x20
; Averaging Code
; Select Bank1
;
;
;
;
;
MOVF
BANKSEL
SUBWF
BTFSC
DECF
BTFSS
INCF
BANKSEL
ADC_Data,W
0xA0
INDF, 0
STATUS, 0
INDF, 1
STATUS, 0
INDF, 1
0x20
; Averaging Code
; Select Bank1
;
;
;
;
;
BANKSEL
BTFSS
GOTO
INTCON
INTCON,T0IF
$-1
; Check The Timer
;
;
45
INCF
DECFSZ
GOTO
;-------------------------MOVLW
MOVWF
MOVLW
MOVWF
;--------------------------
FSR,
1
Action_Cnt
Action_Loop1
; Change Counter and Memory
;
; and go back to Action Loop
0x4F
Action_Cnt
0x120
FSR
;Initialize Action Counter (Bank2)
;and FSR
;
;
Action_Loop2:
; Bank2 Loop
BANKSEL
MOVLW
MOVWF
BCF
TMR0
0x38
TMR0
INTCON,T0IF
; Set The Timer
;
;
;
BANKSEL
BSF
PORTA
PORTA, LD
;Send out DAC Data (load)
;
nop
nop
nop
;Phase delay adjustment
;
;
BANKSEL
ADCON0
BSF
ADCON0,GO
BANKSEL
0x120
MOVF
INDF, 0
BANKSEL
ADCON0
MOVWF
Buffer1
;----------------------------------------------------------------BANKSEL
0x120
BSF
STATUS, IRP
INCF
FSR,
1
MOVF
INDF, 0
;------------------------BANKSEL
Buffer1
BCF
STATUS, IRP
;
BCF
ADDWF
BCF
RRF
; Start ADC conversion
;
; Select Bank2
;
; Select Bank0
;
; Select Bank2
; Get the Next Data
;
;
STATUS, 0x00
Buffer1,1
STATUS, 0x00
Buffer1,1
; clear carry bit
; buffer1=buffer1+DAC_Data
; clear carry bit
; Averaged by 2
Buffer1, 0
DAC_Data
DAC_Out
;
;
;
BANKSEL
BSF
MOVF
BANKSEL
BCF
MOVWF
BANKSEL
BSF
DECF
BANKSEL
BCF
0x120
STATUS, IRP
INDF, 0
DAC_Data
STATUS, IRP
DAC_Data
0x120
STATUS, IRP
FSR,
1
DAC_Data
STATUS, IRP
; Select Bank2
BANKSEL
PORTA
MOVF
MOVWF
Call
;-------------------------
;
; Select Bank0
;
;
; Select Bank2
;
; Select Bank0
;
46
BSF
PORTA, LD
Call
DAC_Out
;--------------------------------------------------------------BANKSEL ADCON0
BTFSC ADCON0,GO
GOTO $-1
;
;and Send DAC Data Out (Without load)
;ADC Conversion Check
;Is conversion done?
;No, test again
BANKSEL
MOVF
MOVWF
ADRESH
ADRESH,W
ADC_Data
;Read Higher 8 bits of ADC
;
;
MOVF
BANKSEL
BSF
SUBWF
BTFSC
DECF
BTFSS
INCF
BCF
BANKSEL
ADC_Data,W
0x120
STATUS, IRP
INDF, 0
STATUS, 0
INDF, 1
STATUS, 0
INDF, 1
STATUS, IRP
0x20
; Averaging Code
; Select Bank2
MOVF
BANKSEL
BSF
SUBWF
BTFSC
DECF
BTFSS
INCF
BCF
BANKSEL
ADC_Data,W
0x120
STATUS, IRP
INDF, 0
STATUS, 0
INDF, 1
STATUS, 0
INDF, 1
STATUS, IRP
0x20
MOVF
BANKSEL
BSF
SUBWF
BTFSC
DECF
BTFSS
INCF
BCF
BANKSEL
ADC_Data,W
0x120
STATUS, IRP
INDF, 0
STATUS, 0
INDF, 1
STATUS, 0
INDF, 1
STATUS, IRP
0x20
MOVF
BANKSEL
BSF
SUBWF
BTFSC
DECF
BTFSS
INCF
BCF
BANKSEL
ADC_Data,W
0x120
STATUS, IRP
INDF, 0
STATUS, 0
INDF, 1
STATUS, 0
INDF, 1
STATUS, IRP
0x20
MOVF
BANKSEL
BSF
SUBWF
BTFSC
DECF
ADC_Data,W
0x120
STATUS, IRP
INDF, 0
STATUS, 0
INDF, 1
;
;
;
;
;
; Averaging Code
; Select Bank2
;
;
;
;
;
; Averaging Code
; Select Bank2
;
;
;
;
;
; Averaging Code
; Select Bank2
;
;
;
;
;
; Averaging Code
; Select Bank2
;
;
;
47
BTFSS
INCF
BCF
BANKSEL
STATUS, 0
INDF, 1
STATUS, IRP
0x20
;
;
BANKSEL
BTFSS
GOTO
INTCON
INTCON,T0IF
$-1
; Check The Timer
;
;
FSR,1
Action_Cnt
Action_Loop2
; Change Counter and Memory
;
; and go back to Action Loop
0xA0
0xA0,
0x7F
0x7F
; Taking Care of last data of the Bank0
;
;
;
INCF
DECFSZ
GOTO
;-------------------------;-------------------------BANKSEL
MOVF
BANKSEL
MOVWF
BANKSEL
BSF
MOVF
BANKSEL
BCF
MOVWF
;--------------------------
0
0x120
STATUS, IRP
0x20,
0
0xEF
STATUS, IRP
0xEF
; Taking Care of last data of the Bank1
;
;
BANKSEL
MOVLW
MOVWF
BANKSEL
Call
BSF
DAC_Data
0x80
DAC_Data
PORTA
DAC_Out
PORTA, LD
; For Last Point
; Send 0(mid point) at the end
;
; Send out DAC Data (load)
;
;
MOVLW
MOVWF
MOVF
BANKSEL
MOVWF
Call
0x26
FSR
INDF, 0
DAC_Data
DAC_Data
DAC_Out
; Prepare First Data
;
;
;
;
;
INDF, 0
Buffer1
; Move First data to buffer1
; For getting the mid point
Main
; Go to Wait for Next trig
;
;-------------------------;
MOVF
;
MOVWF
;-------------------------GOTO
DAC_Out:
BANKSEL
BCF
BCF
PORTA
PORTA, SCK
PORTA, LD
NOP
;------------------BSF
PORTA, DIN
;DAC A3 Bit (1)
48
BSF
BCF
;------------------BCF
BSF
BCF
;------------------BCF
BSF
BCF
;------------------BSF
BSF
BCF
;------------------BCF
BTFSC
BSF
BSF
BCF
;------------------BCF
BTFSC
BSF
BSF
BCF
;------------------BCF
BTFSC
BSF
BSF
BCF
;------------------BCF
BTFSC
BSF
BSF
BCF
;------------------BCF
BTFSC
BSF
BSF
BCF
;------------------BCF
BTFSC
BSF
BSF
BCF
;------------------BCF
BTFSC
BSF
PORTA, SCK
PORTA, SCK
PORTA, DIN
PORTA, SCK
PORTA, SCK
;DAC A2 Bit (0)
PORTA, DIN
PORTA, SCK
PORTA, SCK
;DAC A1 Bit (0)
PORTA, DIN
PORTA, SCK
PORTA, SCK
;DAC A0 Bit (1)
PORTA, DIN
DAC_Data,0x07
PORTA, DIN
PORTA, SCK
PORTA, SCK
PORTA, DIN
DAC_Data, 0x06
PORTA, DIN
PORTA, SCK
PORTA, SCK
PORTA, DIN
DAC_Data, 0x05
PORTA, DIN
PORTA, SCK
PORTA, SCK
PORTA, DIN
DAC_Data, 0x04
PORTA, DIN
PORTA, SCK
PORTA, SCK
PORTA, DIN
DAC_Data, 0x03
PORTA, DIN
PORTA, SCK
PORTA, SCK
PORTA, DIN
DAC_Data, 0x02
PORTA, DIN
PORTA, SCK
PORTA, SCK
PORTA, DIN
DAC_Data, 0x01
PORTA, DIN
49
BSF
BCF
;------------------BCF
BTFSC
BSF
BSF
BCF
;------------------;------------------BCF
BSF
BCF
PORTA, SCK
PORTA, SCK
PORTA, DIN
DAC_Data, 0x00
PORTA, DIN
PORTA, SCK
PORTA, SCK
PORTA, DIN
;Send zero for 2 Low bits
PORTA, SCK
PORTA, SCK
BSF
BCF
;------------------;------------------BSF
BCF
PORTA, SCK
PORTA, SCK
BSF
BCF
;-------------------
PORTA, SCK
PORTA, SCK
PORTA, SCK
PORTA, SCK
; DAC Don't Cares
RETURN
END
50
6. Bibliography
[1]
J. Pine, “Recording action potentials from cultured neurons with extracellular
microcircuit electrodes,” J. Neurosci. Meth., vol. 2, pp. 19-31, 1980.
[2]
R. A. Blum, J. D. Ross, S. K. Das, E. A. Brown, and S. P. DeWeerth, “Models of
stimulation artifacts applied to integrated circuit design,” Int. IEEE Conf. EMBS, vol. 6,
pp. 4075-4078, 2004.
[3]
C. Andrews, B. Kermani, W. Cascio, and H. Nagle, “Controlling electrical side effects of
cardiac stimulus pulses due to high-impedance electrodes,” Intl IEEE Conf. EMBS, vol. 2,
pp. 960-961, 1994.
[4]
Z. Nikolic, D. Popovic, R. Stein, and Z. Kenwell, “Instrumentation for ENG and EMG
recording in FES system,” IEEE Trans. Biomed. Eng., vol. 41, pp. 703-706, 1994.
[5]
K. Strange and J. Hoffer, “Restoration of use of paralyzed limb muscles using sensory
nerve signals for state control of FES-assisted walking,” IEEE Trans. Rehab. Eng., vol. 7,
pp. 289-300, 1999.
[6]
H. Jadvar and D. Benson, “A stimulus artifact suppressor for esophageal pacing studies:
design and clinical testing,” Int. IEEE Conf. EMBS, vol. 5, pp. 1401-1402, 1989.
[7]
T. L. Babb, E. Mariani, G. M. Strain, J. P. Lieb, H. V. Soper, and P. H. Crandall, “A
sampled and hold amplifier system for SA suppression,” Electroenceph. Clin.
Neurophysiol., vol. 44, pp. 528-531, 1978.
[8]
G. DeMichele and P. Troyk, “Stimulus-resistant neural recording amplifier,” Int. IEEE
Conf. EMBS, vol. 4, pp. 3329-3332, 2003.
[9]
M. Solomonow, R. Baratta, T. Miwa, H. Shoji, and R. D’Ambrosia, “A technique for
recording the EMG of electrically stimulated skeletal muscle,” J. Orthoped., vol. 8, pp.
493-495, 1985.
[10]
E. Roskar and A. Roskar, “Microcomputer based electromyographic recording system
with SA suppression,” 3rd Conf. Biomedical Engineering, 1983.
[11]
M. Knaflitz, and R. Merletti, “Suppression of stimulation artifacts from
myoelectric-evoked potential recordings,” IEEE Trans. Biomed. Eng., vol. 35, pp.
758-763, 1988.
[12]
M. Thomsen, J. Struijk and, T. Sinkjaer, “Artifact reduction with monopolar nerve cuff
recording electrodes,” Int. IEEE Conf. EMBS, vol. 1, pp. 367-368, 1996.
[13]
I. Triantis, A. Demosthenous, and N. Donaldson, “Comparison of three ENG tripolar cuff
recording configurations,” IEEE EMBS Conf. Neural Engineering, pp. 364-367, 2003.
[14]
K. C. McGill, K. L. Cummins, L. J. Dorfman, B. B. Berlizot, K. Luetkemeyer, and D. G.
Nishmura, “On the nature and elimination of SA in nerve signals evoked and recorded
51
using surface electrodes,” IEEE Trans. Biomed. Eng., vol. 29, pp. 129-135, 1982.
[15]
T. Blogg and W. D. Reid, “A digital technique for stimulus artifact reduction,”
Electroenceph. Clin. Neurophysiol., vol. 76, pp. 557–561, 1990.
[16]
V. Parsa, P. Parker, and R. Scott, “Convergence characteristics of two algorithms in
non-linear SA cancellation for electrically evoked potential enhancement,” Med. Biol.
Eng. Comp., vol. 36, pp. 202-214, 1998.
[17]
V. Parsa and P. Parker, “Adaptive SA reduction in non-cortical somatosensory evoked
potential studies,” IEEE Trans. Biomed. Eng., vol. 45, pp. 165-179, 1998.
[18]
T. Wichmann, “A digital averaging method for removal of SA in neurophysiologic
experiments,” J. Neurosci. Meth., vol. 98, pp. 57-62, 2000.
[19]
T. Hashimoto, C. Elder, and J. Vitek, “A template subtraction method for reduction of SA
removal in high-frequency deep brain stimulation,” J. Neurosci. Meth., vol. 113, pp.
181-186, 2002.
[20]
I. Bar-Gad and S. Elias, “Complex locking rather than complete cessation of neural
activity in
the
Globus
Pallidus of
a 1-methyl-4-phenyl-1,
2,
3,
6-tetrahydropyridine-treated primate in response to pallidal microstimulation,” J.
Neurosci., vol. 24, pp. 410-419, 2004.
[21]
R. Grieve and P. Parker, “Adaptive SA cancellation in biological signals using neural
networks,” Int. IEEE Conf. EMBS, vol. 1, pp. 801-802, 1995.
[22]
B. Boudrea and K. Englehart, “Reduction of SA in somatosensory evoked potentials:
segmented versus subthreshold training,” IEEE Trans. Biomed. Eng., vol. 51, pp.
1187-1195, 2004.
[23]
D. T. O’Keeffe, G. M. Lyons, A. E. Donnelly, and C. A. Byrne, “SA removal using a
software-based two-stage peak detection algorithm,” J. Neurosci., vol. 109, pp. 137-145,
2001.
[24]
D. A. Wagenaar and S. M. Potter, “Real-time multichannel stimulus artifact suppression
by local curve fitting,” J. Neurosci. Meth., vol. 120, pp. 113-120, 2002.
[25]
A. Hines and P. Crago, “SA removal in EMG from muscles adjacent to stimulated
muscles,” J. Neurosci. Meth., vol. 64, pp. 52-62, 1996.
52