2016 COMP4601 LAB FAMILIARIZATION
AIMS
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Familiarize yourself with the ZedBoard and its operation
Gain familiarity with Vivado 2015.4 by completing a sequence of recommended lab
exercises from the XUP “Advanced Embedded Systems Design using Vivado” course
Practice creating and interfacing your own hardware designs by completing the “Creating
AXI-LITE ‘Custom IP’ in Vivado” lab exercises
Gain experience installing Linux on the ZedBoard with reference to the guide “Linux on the
ZedBoard” and the XUP workshop “Embedded Linux on Zynq using Vivado”.
Learn where you can obtain help in your use of the board and the Vivado design software
Install Vivado on your home computer in order to work on your project. It is recommended
that you use the CSE OpenVPN network (see http://taggi.cse.unsw.edu.au/FAQ/OpenVPN)
and the floating license server (27000@louie.cse.unsw.edu.au) to run the software.
PROCEDURE
1. Lab kits & forms will be distributed for your signature in Week 1.
• Please don’t lose items from the kit and please take care not to damage the kit as
these cannot be replaced; they are in short supply this year. In particular, never
forget your power adapter when you pack away your kit to leave the lab.
2. If you are provided with a shrink-wrapped ZedBoard box, follow the lab demonstrator’s
directions to unpack the ZedBoard box, otherwise go on to Step 3.
• Hand in included papers and disks, as these will not be used
• Obtain a power adapter, a second USB-micro USB cable and two jumper
connectors to complete the lab kit for COMP4601
3. Login to your CSE account on the Lyre lab machine and enter the command “vm
COMP4601_16s1” in a terminal window to start the vmware machine containing Vivado
2015.4
• NOTE: The virtual machine is configured to be non-persistent; this means you need
to save any files you have created to removable memory or your UNIX home
(accessible via Z:\) before shutting down Windows or closing the virtual machine,
otherwise it will be lost.
• Also please ensure that you close (shut down) the virtual machine and logoff your
CSE account before leaving the lab.
4. Check out folders C:\zedboard and
C:\xup\adv_embedded\2015_2_zynq_labdocs_pdf. Note that the C:\xup\2015
Xilinx workshops folder contains an archive of all current Xilinx Professor Workshops
for Vivado 2015. These courses range in difficulty from Introductory to Intermediate as
indicated in Overview.pdf and provide a valuable resource for getting you started on
most aspects of the lab environment.
5. Go through the ZedBoard Getting Started Guide C:\zedboard\GS-…
• If you have trouble loading the default configuration off the SD card, it is possible
that the SD card needs to be re-initialized with the original image – follow the
instructions in C:\zedboard\README-restore_SD_image.txt
• Refer to the ZedBoard Hardware User’s Guide C:\zedboard\ZedBoard_HW_
UG_...to understand details of the board’s configuration
Refer to www.zedboard.org and www.xilinx.com → Products for lots of user
resources including video tutorials, datasheets, forums, etc.
• Demos 4 through 7 cannot be performed in the CSE labs, but please try to complete
these exercises at home
Commence the XUP “Advanced Embedded Systems Design using Vivado” course by
reading the PDFs in C:\xup\adv_embedded\2015_2_zynq_labdocs_pdf in order
• After you have read
C:\xup\adv_embedded\2015_2_zynq_labdocs_pdf\11a_Lab1_
Intro.pdf, jump to
C:\xup\adv_embedded\2015_2_zynq_labdocs_pdf\lab1.pdf and carry
out the exercises.
• Carry on with
C:\xup\adv_embedded\2015_2_zynq_labdocs_pdf\12_Advanced_Zynq_
Architecture.pdf and carry out each lab after reading its introduction
• It is recommended that you complete labs 1, 2, 3 and 6 as a minimum. These
should be completed before Easter (end of Week 4), when you are required to
hand in a report comprising your written responses to the reflective questions
set out below on Lab 1, Lab 6 and the Custom IP Lab (see next step).
Complete the Creating AXI-LITE ‘Custom IP’ in Vivado lab. Carry out the implementation
exercises in Section 6. Please note that the lab was designed for Vivado 2013.4 and that
the arrangement of the screenshots and which options appear on which screens may have
changed in the meantime. Please note any divergence and inform the Tutor, who will
maintain a list of significant changes. Submit written responses to the reflective
questions below and a printout of the VHDL code for each IP block you created by
Friday 25 March (Week 4).
[OPTIONAL] If you are interested in installing Linux on the ZedBoard in order to facilitate
communications, file transfer, and configuring the programmable logic from within a
program running on one of the ARM cores, follow the “Linux on the ZedBoard” guide and
consult the XUP workshop “Embedded Linux on Zynq using Vivado”.
[OPTIONAL] You are invited to improve the lab materials that have been provided for any
of the exercises described above, as well as for any of the other 2015 Xilinx workshop
courses you have completed. In this case, your suggestions will be considered for the
award of bonus marks to be added to the Lab report and Individual project contribution
components of your course grade. Contact Oliver to discuss your ideas and to obtain
access to the sources of the exercises/documentation that you intend to modify.
Improvements must be submitted by Friday 13 May (Week 10) to be considered.
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ADVANCED EMBEDDED SYSTEMS LAB SYNOPSES
LAB1 AIM: A simple exercise to familiarise students with the Vivado work flow
METHOD: Students are guided through the process of adding GPIO IP to the programmable
logic of the Zedboard. Students then create a standalone application for testing the custom
system. The application uses the serial port for debug output and Switches/Leds on the
Zedboard to demonstrate the operation of the custom system.
LAB2 AIM: A simple exercise to familiarise students with hardware debugging in Vivado.
METHOD: Students are shown how to import trivial 3rd party IP into their Vivado PL system
design. Students are then shown how to examine the signal levels and transitions on the AXI
bus when communicating with this IP. Finally, students are shown how debug input signals can
be used to manually insert signals onto busses which reside in the programmable logic.
LAB3 AIM: To demonstrate the use of BRAM in the system
METHOD: Students create an FPGA system design for the Zedboard which includes BRAM.
Students then create a standalone test application for this lab. The linker script is to be
modified such that the .data section of their application resides in BRAM rather than DDR
RAM. Modification of the linker script is done through the Vivado SDK GUI via combo boxes
rather than modifying a textual representation of the linker script.
LAB4 AIM: Demonstrate the integration of DMA engines and IRQs
METHOD: This lab builds on LAB3. A DMA engine is added in the programmable logic and and
IRQ is configured to fire when the DMA engine becomes idle. Students then benchmark
different methods of copying data to/from different locations with different transfer mechanisms.
LAB5 AIM: To demonstrate the various boot options of the Zedboard and how to install the
bootloader.
METHOD: Create a boot image and boot the system from various sources (SD card, QSPI
flash, JTAG). This lab is long, tedious and does not offer much when you consider that
students will generally boot only from JTAG, or SD with a boot image that they get from the
web.
LAB6 AIM: To learn about system profiling and the strategic selection of candidate software
functions for acceleration in the FPGA hardware.
METHOD: Students import a DSP based project. An FIR filter is provided as both software and
hardware implementations. Students use gprof to obtain performance metrics for the software
implementation. Students then switch to the hardware implementation and re-evaluate system
performance to observe an incredible performance improvement.
CUSTOM IP LAB AIM: Introduces a design flow that will allow you to create your own Custom
Intellectual Property (Custom IP) targeted at a Zynq device using Xilinx’s Vivado 2013.4
METHOD: The lab explains how to modify a generated component, by focusing on how the
AXI-LITE protocol works and how it can be utilised to establish a two-way data flow between
the Processing System (PS) and the hardware component implemented in programmable logic
(PL). This lab concludes on methods for maintaining and integrating this IP as part of a larger
design.
REFLECTIVE QUESTIONS
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Submit written answers to the following questions for each lab you completed. As a
minimum, these should include labs 1 and 6 of the Advanced Embedded Systems course
as well as the in-house developed Custom IP lab. You should be able to write about one
page per lab
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What did you learn while completing this lab?
In which design situations could you apply the knowledge/skills you gained in this lab?
What did you like/dislike about the lab?
Are there any ways in which the lab exercises or documentation could be improved?
How would you implement your suggestions?