Signal processing for High Granularity Calorimeter:
Amplification, Filtering, Memorization and Digitalization
Laurent ROYER, Samuel MANEN, Pascal GAY
LPC Clermont-Ferrand
L.Royer– TWEPP – 22 Sept. 2010
International Linear Collider
ILC "could be the next big adventure
in particle physics"
The possible discoveries scientists could make with the ILC
[http://www.linearcollider.org/]
[http://www.linearcollider.org/]
(Credit: Greg Stewart, SLAC)
ILC BEAM STRUCTURE:
ILC BEAM STRUCTURE




about 300ns between collisions
duration of train of collisions: 1ms
no beam during 199 ms
with 1ms to convert signals and
output data  99% of the time with
no activity for electronics on
detectors
L.Royer– TWEPP – 22 Sept. 2010
2
Challenges for next generation of Ecal

Sandwich structure of: thin wafers of silicon diodes
& tungsten layers
 Embedded Very Front End (VFE) electronics
 Deeply integrated electronics

High granularity : diode pad size of 5x5 mm2

High segmentation : ~30 layers

Large dynamic range of the input signal (15 bits)


0.1 MIP (noise level) -> ~3 000 MIPs
Minimal cooling available and > 100.106 channels
 Ultra-low power : 25 µW per VFE channel
 power pulsing required (1% duty cycle)
« Tracker electronics with
calorimetric performance »
Analog electronics busy
1ms (.5%)
A/D conv.
DAQ
.5ms (.25%)
.5ms (.25%)
L.Royer– TWEPP – 22 Sept. 2010
IDLE MODE
198ms (99%)
3
Architecture of the VFE designed
1 2 b its
CSA
I d e te c t o r
A n alog
m em ory
S h aper
V
V
C SA
R eset
ADC
G I
R eset
C2
Cf
C1 R1
A m p l.
1 2 b its
A m p l.
ADC
G a te d Integrato r
 Charge Preamplifier
–
The amplification of the charge delivered by the detector is performed with a low-noise
Charge Sensitive Amplifier (CSA)
 Shaper and Analog Memory
–
The bandpass filter is based on a gated integrator which includes an intrinsic analog
memory thanks to the integration capacitor
 Analog to Digital Converter
–
The converter is a customized low power 12-bit cyclic ADC
 External digital block to control the G.I. and the ADC (in a FPGA)
 Technology: AMS CMOS 0.35µm
L.Royer– TWEPP – 22 Sept. 2010
4
The Charge Sensitive Amplifier (CSA)
• The amplifier is based on a boosted folded cascode, followed by
a source follower
 Boosted Cascode : High gain performance
 Source follower : Low output impedance
Q, the charge delivered by the detector.
Cf, the feedback capacitor.
Cf
V out
A (p )
i
Cd
50% for masters of the current sources
 can be shared by several channels
VDD
IN
M1
I2
-A
I3
OUT
M2
M3
I1
GND
L.Royer– TWEPP – 22 Sept. 2010
5
The charge preamplifier
• The spectral density of the noise at the output of the CSA is
mainly composed of two terms: parallel and serial noises
Parallel Noise
Serial Noise
–
in corresponds to the gate leakage current of the detector and the current noise
contribution of Rf
–
en is the thermal noise introduced by the input transistor
–
Af is the process dependant flicker noise parameter
L.Royer– TWEPP – 22 Sept. 2010
6
CRRC Shaper vs Gated Integrator (GI)
CRRC
O ut_C RR C
CR RC
Shaper
M em o ry
cell
G.I.
IN
M em o ry
cell
G.I.
Gated
Integrator
O ut_G ated_Integrator
Bunch interval
337ns
•
•
The integration capacitor of the G.I. can be used as an analog memory cell
(switch opened at the end of the integration)
– no extra analog-memory stage required
The fast switched reset of the capacitor of the G.I. allows a time of integration
near to the bunch interval
– no pile up
– improved noise filtering (see next slides)
L.Royer– TWEPP – 22 Sept. 2010
7
Comparative noise filtering performances of
Gated Integrator and CRRC filtering
• CRRC shaper is time invariant filter
• Gated integrator is time variant filter
 To compare performances, weighting functions R(t) in time domain
MUST BE USED (see publications of V.Radeka & Goulding)
• The weighting function is the measurement of influence of a noise
step generated before the measuring time on the amplitude at the
measuring time
Obtained by simulation with Virtuoso from Cadence
CRRC
CRRC
G.I.
G.I.
L.Royer– TWEPP – 22 Sept. 2010
8
Comparative performances of
Gated Integrator and CRRC filtering
• R(t) is used to calculate noise indexes:
– Parallel Noise index
CRRC
– Serial Noise index
G.I.
A: gain of the system
• The parallel and serial noises can be evaluated for any case of
shaper to compare filtering performance
L.Royer– TWEPP – 22 Sept. 2010
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Comparative performances of
Gated Integrator and CRRC filtering
•
Noise indices have been simulated with Analog Artist (Cadence) Software
for several peaking times (CRRC) and durations of integration (G.I.)
CRRC
CRRC
Serial Noise
Parallel Noise
G.I.
~30%
•
~30%
G.I.
The peaking time of the CRRC shaper is limited due to pile-up consideration
 200ns with a bunch crossing of 337ns (ILC).
•
For the Gated Integrator, fast reset of integration capacitor allows duration of
integration near to the bunch crossing interval
 300ns with bunch crossing of 337ns
 both serial and parallel noise indexes can be reduced by about 30% with the
G.I. filtering.
L.Royer– TWEPP – 22 Sept. 2010
10
Architecture of the 12 bits cyclic ADC
1 µs for recovery time included after power ON
 The cyclic architecture is well
adapted to compact-low-power
converter
 1.5 bit per stage architecture
 Clock frequency: 1MHz
 Power pulsed
L.Royer– TWEPP – 22 Sept. 2010
11
Conventional 2-stage Cyclic architecture
S C N etw ork s
A1
V in < -V ref ... +V ref >
A2
x2
+
x2
+
 one cycle 
DAC1
V in
b0
DAC
-
A2
A1
V in
b0
0
DAC2
MSB
MSB-1
L ogic
V in
D igital d ata
p rocessin g
+
b0
-V ref
0
F in al ou tp u t
 One cycle = two phases of amplification and sampling
 At each cycle (one clock period), 2 bits are delivered  MSB then MSB-1, …..until LSB
 For an n-bit ADC, n/2 cycles are required
 The key block: gain-2 amplifier (switched capacitors amplifier)
 The precision of the gain-2 amplification gives the precision of the ADC
L.Royer– TWEPP – 22 Sept. 2010
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1,5 bit/stage Cyclic architecture
S C N etw ork s
V in < -V ref ... + V ref >
x2
x2
+
DAC1
+
DAC2
V in
V in
b0, b1
b0, b1
2
V ref/4
DAC
-
D igital d ata
p rocessin g
+
V in
2
L ogic
+
-V ref/4
+ V ref
-V ref
b0
b1
0
F in al ou tp u t
+ 1 redundant bit at each cycle
 Precision of the ADC becomes insensitive to the offset
of the comparators up to ± 1/8 of the dynamic range (± 125mV for 2 V)
 Number of comparators is doubled
L.Royer– TWEPP – 22 Sept. 2010
13
Enhanced architecture: "Flip-around amplifier "
S C N etw o rk s
V in
S C N etw o rk s
V in
x2
+
+
x2
+
A
DAC1
DAC2
V in
DAC1
V in
b0, b1
DAC2
V in
V in
b0, b1
b0, b1
2
Phase 1
+
A
b0, b1
2
D ig ita l d a ta
p r o c e s s in g
Phase 2
D ig ita l d a ta
p r o c e s s in g
 one cycle 
A
MSB
A
 A single amplifier shared by the two stages
 As main of the power is consumed by amplifier
 reduction of power up to 40%
MSB-1
L.Royer– TWEPP – 22 Sept. 2010
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Enhanced architecture: "Flip-around amplifier "
PH A SE 1
V T H _H
C2
A m plification
bit1_H
V T H _L
V REF1
clk+
V REF2
DAC
A M P L IF IE R
bit1_L
C4
V T H _H
1 MHz clock
S am pling
V T H _L
clk-
"Start conversion " signal
DAC
Two phases of conversion with a single amplifier
PH A SE 2
V T H _H
11
1 2 3
9
7
4
12
C2
5
S am pling
V T H _L
clk+
6
DAC
8
10
Output signal of the amplifier
A m plification
C4
V T H _H
bit2_H
V REF2
A M P L IF IE R
V T H _L
clk-
V REF1
DAC
bit2_L
L.Royer– TWEPP – 22 Sept. 2010
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Results of measurements of the VFE (1)
1 2 b its
CSA
I d e te c t o r
A n alog
m em ory
S h aper
V
V
C SA
R eset
ADC
G I
R eset
Global linearity of 10 bits (0.1%)
C2
Cf
C1 R1
A m p l.
Input pulse
1 2 b its
A m p l.
ADC
G a te d Integrato r
Control
signals
Output data
The standard deviation of the noise at the output of
the channel is 0.76 LSB (370 μV rms).
The Equivalent Noise Charge (ENC) at the input of
the channel is then lower to 2 fC.
The power consumption of the channel is 6.5mW,
estimated to 25µW with duty cycle of each block.
L.Royer– TWEPP – 22 Sept. 2010
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Results of measurements of the VFE (2)
Dispersion of the gain of the 9 chips (in %)
2,00
1,50
1,00
0,50
0,00
1
2
3
4
5
6
7
8
9
-0,50
Dispersion of the offset of the 9 chips (in mV)
-1,00
1,80
-1,50
1,60
-2,00
1,40
1,20
1,00
Série1
0,80
0,60
0,40
0,20
0,00
1
9/22/2010
2
3
L.Royer– TWEPP – 22 Sept. 2010
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5
6
7
8
9
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Summary
 A VFE channel performing the amplification, the filtering, the memorization and the
digitalization of the charge from Si detector has been designed and tested.

Global Linearity better than 0.1 % (10 bits) up to 9.5 pC (2375 MIP).

ENC = 1.8 fC (0.5 MIP) with a single gain stage

Power consumption with power pulsing (ILC timing) estimated to 25µW
L.Royer– TWEPP – 22 Sept. 2010
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Present road map

Next step 1: improved and more complete channel

Improvement of the dynamic range

Reduction of the output noise of the amplifier of the Gated Integrator

Bi-Gain shaping

Fast shaping channel for auto-trigger

Integration of the digital block, of the bandgap (ADC references)

Implementation of the power pulsing
channel n

C

S haper
SCA
A M P L I.
C ha rg e
p r e - a m p lif ie r
1
A
N
A
L
O
G
S haper
10
filte red sig n al
S haper
p re- am p lified sig na l
S haper
ADC
A
N
A
L
O
G
M
E
M
O
R
Y
Next step 2: multi-channels chip
pin compatible with SKIROC chip
from LAL with same DAQ
1 2 b its
T
O
D
I
G
I
T
A
L

comparative performances (synchro
or asynchronous filtering, pure
CMOS or SiGe techno., common or
multi ADC, …)
D is c r i.
T R IG G E R
F ast
channel n+ 1
SCA
ADC
L.Royer– TWEPP – 22 Sept. 2010
1 2 b its
19
The workshop is devoted to the design of GHz microelectronic components for signal processing in high energy physics,
astronomy and astroparticle physics, spatial and medical applications, as well as high rate networks.
It will be held October 28th to October 29th, 2010 at Laboratoire de Physique Corpusculaire (LPC) de Clermont
Ferrand (FRANCE). It aims to review the state of the art of the technique and to bring together in an informal way
design experts and potential users.
Workshop topics :
 Needs and requirements in high energy physics, astrophysics, nuclear medical imaging,..
 Performance and limitations of the VLSI (Very Large Scale Integration) Technologies
 Wide Band Analogue Front End Electronics
 High rate SCA (Switched Capacitor Array)
 High rate ADC (Analog to Digital Converter)
High rate networks
For information:
http://clrwww.in2p3.fr/www2008/giga/
L.Royer– TWEPP – 22 Sept. 2010
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