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Subthreshold and gate leakage current analysis and
reduction in VLSI circuits
Vinay Chinta
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Subthreshold and Gate Leakage Current Analysis and
Reduction in VLSI Circuits
by
Vinay Chinta
A Thesis Submitted in Partial Fulfillment of the Requirements for the Degree of
Master of Science in Computer Engineering
Supervised by
Dr. Dhireesha Kudithipudi
Department of Computer Engineering
Kate Gleason College of Engineering
Rochester Institute of Technology
Rochester, NY
April 2007
Approved By:
Dhireesha K.
Dr. D. Kudithipudi
Primary Advisor - R.I. T. Dept. of Computer Engineering
Kenneth Hsu
Dr. K. Hsu
Secondary Advisor - R.I. T. Dept. of Computer Enginee ring
Marcin Lukowiak
Dr. M. Lukowiak
Secondary Advisor - R.1. T. Dept. of Computer Engineering
Thesis Release Permission Form
Rochester Institute of Technology
Kate Gleason College of Engineering
Title: Subthreshold and Gate Leakage Current Analysis and Reduction in
VLSI Circuits
I, VINAY CHINTA, HEREBY GRANT PERMISSION TO THE WALLACE MEMORIAL
LIBRARY TO REPRODUCE MY THESIS IN WHOLE OR PART.
(h. Vinay
Vinay Chinta
Date
11
Dedication
To Father
and
in
Mother
Acknowledgements
I
offer
my
throughout
persistent
sincerest
my thesis
help
gratitude
to my advisor, Dr.
work with patience
this thesis
would
not
and
Kudithipudi
who
has
knowledge. Without her
have been
possible.
I
wish
guided
guidance
me
and
to thank my thesis
committee
members, Dr. Hsu and Dr. Lukowiak for providing insights that guided and
challenged
my thinking
and
thereby improving my
Mr. Mezzanini for providing
all
the
thesis
work.
I
would also
like to thank
required applications and software needed
thesis.
IV
for this
Abstract
CMOS technology has
to enhance
functionality,
scaling down to
becoming
speed and
the dominant component
currents.
deep
The leakage
faster
In this
and
analysis
provides
subthreshold
technique is
leakage
leakage
proposed
currents.
for
analysis
Based
leakage
state
their position in the stack.
compared
on
to
most of
the
ISCAS89 benchmark
The
reducing
combined
proposed
gate
with
subthreshold
subthreshold
mainstream
leakage
of
the
on
on
leakage
and
is
contributors
to
significantly
were
and
mostly devoted
leakage
gate
characteristics
32nm feature
interdependency
the
tunneling
current.
level
circuit
45nm
performed at
far
so
are
of
of
sizes.
The
gate
and
these observations, a new leakage reduction
based
The
currents.
on
the number of transistors
effectiveness
leakage
reduction
This technique identifies
of the
techniques
proposed
in OFF
technique is
by implementing
them
circuits.
reduction
current
dual-threshold
leakage
is
a given circuit
leakage
leakage
sizes
feature sizes,
sub-65nm
both the leakage
minimum
and
at
observations
that optimizes
vectors
As the feature
increasing
techniques developed
However,
currents
key
an effort
the total power dissipation. Major
reduction
extensive
several
leakage
of
is
power
few decades in
past
per chip.
expected to surpass subthreshold
an
work,
subthreshold and gate
is
density
packing
the
over
submicron regime are subthreshold and gate
to reducing subthreshold leakage.
current grows
aggressively
sub-lOOnm regime,
the total leakage current in
leakage
scaled
than
and
technique
subthreshold
leakage
variable-threshold
current reduction was also
current and
proved
26% for
gate
v
be
more
current.
A total
effective
However,
CMOS techniques,
achieved.
leakage
to
when
substantial
savings of
current are reported.
in
53% for
Table
of
Contents
THESIS RELEASE PERMISSION FORM
II
DEDICATION
Ill
ACKNOWLEDGEMENTS
IV
V
ABSTRACT
VI
TABLE OF CONTENTS
VIII
LIST OF FIGURES
X
LIST OF TABLES
XI
GLOSSARY
CHAPTER 1
INTRODUCTION
1
CHAPTER 2
SOURCES OF POWER DISSIPATION
5
2.1.
5
Active Power
2.1.1
Switching Power
5
2.1.2
Short-circuit Power
6
2.2.
7
Static Power
2.2.1
Subthreshold Leakage
7
2.2.2
Gate Leakage
8
CHAPTER 3
LEAKAGE REDUCTION TECHNIQUES
10
3.1.
Introduction
10
3.2.
Low Power Logic Family
10
3.2.1
Leakage Current
13
3.2.2
Short-Circuit Current
15
3.2.3
Switching
3.3.
Current
17
Transistor Stacks
19
vi
3.4.
Dual Threshold CMOS
3.5.
Variable Threshold CMOS (VTCMOS)
CHAPTER 4
4.1.
(DTCMOS)
SUBTHRESHOLD AND GATE LEAKAGE CHARACTERISTICS
4-Input CMOS NAND Leakage Analysis
21
22
23
24
4.1.1
Case
Study
-1
25
4.1.2
Case
Study
-2
28
4.2.
4-Input CMOS NOR Leakage Analysis
33
4.3.
New Leakage Reduction Algorithm
34
CHAPTER 5
RESULTS
38
5.1.
Transistor Stacks
39
5.2.
Dtcmos
42
5.3.
Vtcmos
43
5.4.
New Leakage Reduction Technique
45
5.5.
Input-Pin Reordering Combined With Dtcmos/Vtcmos
47
5.6.
Comparison of Leakage Reduction Techniques
50
CHAPTER 6
52
CONCLUSION
55
BIBLIOGRAPHY
vn
List
of
Figures
FIGURE 1.
LEAKAGE POWER TRENDS
FIGURE 2.
SWITCHING CURRENT FLOW
6
FIGURE 3.
SHORT-CIRCUIT CURRENT
6
FIGURE 4.
NAND GATE IMPLEMENTATIONS IN DIFFERENT LOGIC FAMILIES
11
FIGURE 5.
LEAKAGE CURRENT COMPARISON
13
FIGURE 6.
XOR IMPLEMENTATIONS
14
FIGURE 7.
SHORT-CIRCUIT CURRENT COMPARISON
15
FIGURE 8.
SHORT-CIRCUIT CURRENT IN LEAP
16
FIGURE 9.
SWITCHING CURRENT COMPARISON
17
-
2
ITRS
FIGURE 10. INVERTER AND TRANSMISSION GATES SIZING
18
FIGURE 11. CAPACITANCE CALCULATIONS AT OUTPUT NODE
18
FIGURE 12. VOLTAGE DEVELOPED AT INTERMEDIATE NODE DUE TO SUBTHRESHOLD
CURRENT
FIGURE 14. DUAL
19
VT CMOS CIRCUIT
22
FIGURE 15. SCHEMATIC OF VTCMOS CIRCUIT
22
FIGURE 16. TYPICAL SUBTHRESHOLD AND GATE LEAKAGE CURRENTS
24
FIGURE 17. SCHEMATIC OF A 4-INPUT CMOS NAND PULL-DOWN NETWORK
25
FIGURE 18. INTERMEDIATE NODE VOLTAGES BASED ON NUMBER OF OFF TRANSISTORS
FIGURE 19. SUBTHRESHOLD LEAKAGE DEPENDENCE ON
.26
V DROP AND ON CHANNEL
27
RESISTIVE DROP
FIGURE 20. TRANSISITOR SIZING FOR 4-INPUT NAND GATE
28
FIGURE 21. GATE CURRENT DRAWN BY TOP-MOST TRANSISTOR IN A STACK
28
FIGURE 22. GATE LEAKAGE CURRENT INCREASES THE NODE VOLTAGE
29
FIGURE 23. SUBTHRESHOLD LEAKAGE CURRENT ADDED TO GATE LEAKAGE CURRENT... 30
FIGURE 24. COMPARISON OF SUBTHRESHOLD AND TOTAL LEAKAGE CURRENTS
FIGURE 25.
ISUB
DEPENDENCE ON STATE OF BOTTOM TRANSISTOR IN THE STACK
Vlll
32
(T3)
34
FIGURE 26. MINIMUM LEAKAGE VECTORS
35
FIGURE 27. TRANSISTOR STACKS
41
FIGURE 28. DTCMOS
43
FIGURE 29. LEAKAGE CURRENT AS A FUNCTION OF BODY BIAS
44
FIGURE 30. LEAKAGE CURRENT REDUCTION ACHIEVED BY VTCMOS
44
FIGURE 31. LEAKAGE CURRENT REDUCTION ACHIEVED BY INPUT PIN REORDERING
46
FIGURE 32. TOTAL LEAKAGE REDUCTION ACHIEVED BY INPUT PIN REORDERING
47
FIGURE 33. INPUT PIN REORDERING COMBINED WITH DTCMOS
48
FIGURE 34. INPUT PIN REORDERING COMBINED WITH VTCMOS
49
FIGURE 35. LEAKAGE REDUCTION ACHIEVED FOR ALL THE TECHNIQUES
50
IX
List
Tables
of
TABLE 1.
SUBTHRESHOLD LEAKAGE FOR 2-INPUT NAND GATE
TABLE 2.
SUBTHRESHOLD LEAKAGE CURRENTS FOR A 4-INPUT CMOS NAND GATE AT
20
45NMNODE
TABLE 3
26
TOTAL LEAKAGE CURRENTS CATEGORIZED FOR 4-INPUT CMOS NAND GATE 3 1
.
.
TABLE 4.
TOTAL LEAKAGE CURRENTS FOR 4-INPUT CMOS NOR GATE
33
TABLE 5.
INPUT PIN REORDERING
36
TABLE 6.
STATISTICS FOR ISCAS89 BENCHMARK CIRCUITS
38
TABLE 7.
LEAKAGE CURRENT REDUCTION ACHIEVED BY TRANSISTOR STACKS
40
TABLE 8
VARIATIONS IN LEAKAGE REDUCTION IN TRANSISTOR STACKS
41
TABLE 9.
LEAKAGE CURRENT REDUCTION ACHIEVED BY DTCMOS
43
TABLE 10.
LEAKAGE CURRENT REDUCTION ACHIEVE BY VTCMOS
44
TABLE 1 1
SUBTHRESHOLD AND GATE LEAKAGE CURRENTS BEFORE AND AFTER INPUT
.
.
PIN REORDERING
45
Glossary
Isub
Subthreshold leakage
Igate
Gate-oxide leakage
Vth
Threshold
VgS
Gate-to-source
vds
Drain-to-source
vDD
Supply
CMOS
Complementary Metal
LEAP
Single
CPL
Complementary pass
CMOS+
Single
DPL
Dual
MTCMOS
Multiple threshold CMOS
DTCMOS
Dual threshold CMOS
VTCMOS
Variable threshold CMOS
PUN
Pull-up
PDN
Pull-down
current
current
voltage
voltage
voltage
voltage
rail pass
rail
rail
Oxide Semiconductor
transistor logic
logic
transmission gate
transmission
gate
logic
logic
network
network
XI
Chapter 1
Introduction
Minimum feature
reduce
delay
gate
technology
and
dissipation
in the
is scaling
Scaling
since
following
a
voltage
dynamic
power
per
increase transistor
and
generation
technology
[1]. With
density
voltage
to
maintain
way
of
dependence
on
most effective
a quadratic
reducing dynamic
power
voltage as shown
supply
equation
Pdyn
where
/is the
system clock
that the
shown
generation
supply
voltage
[3]. Therefore, to
transistor threshold voltage
T
where
is the device
fl
reduced
threshold
inversion
state.
section
thicknesses
mean
maintain
high drive
scaled
studies
the rate of 30% per
current
and
delay
have
technology
performance, the
~
load
\
Qty
(2)
V,i, is
on
as
current
the subthreshold
threshold voltage is
demand scaling
of oxide
fields
across
it
and
due to
leakage
further
a weak
current.
of
in
maintain
[4,5,6]. Lower
higher probability
the
explained
thickness to
strength and reduce short channel effects
electric
However,
the threshold voltage.
increase in leakage
is known
leakage
also
load
_y
mechanism
voltages
higher
Semiconductors)
~
of subthreshold
drive
at
Vbois the supply
accordingly (Eq. 2).
voltage causes a substantial
sufficient transistor
for
is approximately scaling
transconductance and
2.2.1. Reduced
the load capacitance and
Technology Roadmap
has to be
This leakage
The dependence
(D
frequency, Cioad is
ITRS (International
voltage.
to
normal mode of operation and to control power
is the
has
30%
corresponding scaling in supply
fields ensuring
supply
at a rate of
dissipation
power
scaling, there has been
proportionate electric
dissipation.
size
oxide
electrons
tunneling
through the oxide
mechanism called gate
Semiconductors)
by
2008
leakage
while
it is
each
oxy-nitride
subthreshold
namely,
technology
comparable
dissipation
silicon
current mechanisms
anticipated that
power
(International
tunneling leakage. ITRS
utilizing
dominant leakage
has become
of electrons gives
projects that the oxide thickness will
mechanisms
With
layer. This tunneling
as
gate
and
deep
2003
Therefore, understanding
voltages.
currents.
power
2005
2007
the
as
1.6nm
the
has increased significantly
and
emerged
component
in the total
design. Leakage
reduction
analysis
of
leakage
divided in to the
leakage
can
circuit
currents
following
-
be
steps.
22nm
ITRS [31]
current and
achieved
level
level
and
2017
32nm
45nm
mechanisms of
This thesis is entirely devoted to
techniques was
low
as
2015
2013
2011
2009
65nm
various process parameters or at circuit
The
leakage have
become the dominant
power will
as
dielectric. Therefore, these two
gate
Figure 1. Leakage Power Trends
controlling
down to
With the ongoing trend in technology scaling,
power.
90nm
130nm
power
scaled
for
depicted in Figure 1.
2001
for low
Technology Roadmap
sub-micron arena.
generation, leakage
to dynamic
leakage
in
for
be
rise to the leakage
by
at
its
reduction
either
is
critical
device level
by
controlling device terminal
analysis and reduction of
investigation
of
leakage
leakage
reduction
Firstly,
dissipation
number of
impact
and
circuit
are
level
Parameters
made.
transistors
choices such as topologies and
are
such
as
strongly influenced
node
dual
rail pass-transistor
(LEAP, CPL),
(CMOP+, DPL). Standard
cells such as
families
for
were
Secondly,
compared
static
subthreshold
implemented
and
leakage
gate
benchmark
on
dynamic
sizes
due to increased leakage
techniques may
new algorithm
leakage
input
However the leakage
.18pm.
not remain
based
currents
[7]
was
45nm
at
rate of gate
input
flowing
leakage
through
intermediate
reduce
data
voltages
may
current
The
affect
making
Isub
simulations, it could be inferred that this
leakage
of
thus making it
an
32nm feature
may
this thesis
current
by
interdependency
single
the chosen
logic
logic
dissipation).
techniques
Previously,
sizes.
feature
change at
of
sizes
leakage
developing
a
of subthreshold and gate
application of appropriate
is
a result of
high
growth
Significant Igate (gate leakage current)
the
Igate interdependent. From preliminary
interdependency
important
only
lower feature
some
consists of
were
Isub (subthreshold current) by changing
and
the
techniques that target
These
interdependency
the total leakage
pin reordering.
circuit
reduction
technologies with
part of
current at sub-lOOnm regime.
the
node
The final
understand
power
Therefore the efficiency
currents.
same.
on
(total
performed.
and
currents,
rail transmission gate
power
current characteristics
on the statistical
that will
vectors and
the
short-circuit
power
logic families: CMOS,
dual
prevailing leakage
these reduction techniques were implemented
down to
following
single and
currents
circuits
capacitances,
that impact
NAND, NOR, XOR, FA for
and
an evaluation of most of the
styles
the chosen logic style. To
by
these parameters, we have chosen the
of
logic
property.
can
be
exploited to reduce total
This newly developed leakage
reduction
measure
technique was compared against the existing
its
effectiveness.
leakage
reduction techniques
to
Chapter 2
There
Sources
are
2) Static
power and
2) Short-circuit
nodes.
Short-circuit
Active
power.
discharging
and
Power Dissipation
two sources of power dissipation in digital CMOS
power and
charging
of
Switching
power.
dissipation
the ground terminal. This happens
conduct
simultaneously due to
when
non-zero
The third
active mode of operation.
dissipation
stable.
which
is
comprised of
the
input
into
basically
1) Active
1) Switching
occurs
a result of signal transitions
rise and
is
a
direct
due to
at
those
from supply to
network
fall times. Together, switching
because they only
currents
path
network and pull-down
pull-up
source of power
leakage
In this chapter, the different
as
classified
dissipation
occurs when there
short-circuit power comprise of active power
in
power
of capacitive nodes
power
be further
power can
circuits:
dissipation is
that
sources of power
occur when
flow
when
the
and
circuit
is
called static power
the input signals are
dissipation in CMOS
circuits are
discussed in detail.
2. 1.
Active Power
2.1.1
Switching
Switching
Consider
power
an
input
dissipation
inverter
capacitance of
input, CL
Power
stage
occurs
with
the transistors and
gets charged through
switches
to
T,
the
ground
a cycle of
for the
current
load
input
'1'
and
capacitance
and
Ci
discharging
which
is
discharges
and
via
5
voltage
of
intrinsic
(Figure 2). With
'0'
a
rises to VDD. When the
the NMOS transistor to the ground.
inputs effectively
to flow.
its
of capacitive nodes.
composed
capacitance of next stage
PMOS transistor
capacitor
'0'
Therefore
due to charging
creates a path
from supply to the
vDD
i\Z^
00
V0Ut
(a)
Figure 2.
Switching
frequency
of
depends
incurs higher
frequency. It is
circuit
I
switching frequency. A
on
power
dissipation than
to the square
Higher
capacitance
Switching power dissipation
is
Vqut
p
=
0
(c)
Schematic of inverter (b) Charging
also proportional
nodes.
1
=
(b)
Switching current flow (a)
power
p V0UT
when
of
the
circuit
circuit
(b) Discharging
high
with
circuit
switching
the circuit with lower switching
supply
voltage and
leads to higher switching
the
capacitances
dissipation.
power
given as
(3)
Poc=aCoulVDD2f
where a represents
period,
Cout is
the
output
probability that
capacitance,
an output
Vdd is supply
0 to 1 transition takes
voltage and/is
place
during
one
the switching frequency.
2.1.2 Short-circuit Power
Short-circuit
input
waves
power
driving
this
both PMOS
shown
to
short period of
and
occurs
due to
non-zero rise and
the gate. There always exists a slope
transitioning from high
During
dissipation
low
and vice-versa
time, there
NMOS devices
exists a
in the input
due to the input
direct
path
conduct simultaneously.
fall times
wave
between the supply
Consider
an
-v
/
vDD-vUl
\
V.
tpeak
Figure 3. Short-circuit
6
current
when
rails when
inverter
v
I,
the
capacitance of a gate.
in Figure 3.
v
of
stage as
NMOS transistor turns ON
ON
it's
when
it's Vgs
when
is
Vsg (=VDD-Vin)
greater
(=Vin)
therefore dependent
on rise and
frequency
switching
transitions.
since
Short-circuit
Vth. PMOS transistor turns
than
short-circuit current
.
fall times
short-circuit
Vth
of
VDD-Vth. The
and
the input
It is
signal.
dissipation
power
dissipation is
power
greater
than|vj Therefore,
the input signal voltage is between
when
is
flows
also
occurs
dependent
on the
during
signal
only
given as
Psc=tSCVDDIpeakf
where
circuit current and/is
2.2.
However, it
circuits.
This
power
can
are
conducting,
Ipeak is
the
short-
occurs
in
active
occur
static power
is
in
static mode of operation as mentioned earlier.
mode of operation
smaller when compared
due to the
presence of
idle
to that in static mode.
Subthreshold Leakage
is less than
current
is the leakage
threshold voltage.
inversion
state exists
depletion
region.
by
dependent
There is
diffusion
on
Vgs
as
When the
between
the drain and source terminals
move
both devices
switching frequency.
dissipation
also
Subthreshold
weak
the
which
(4)
Static Power
Static
2.2.1
for
represents the time
tsc
is
short-circuit power
current
gate voltage
source and
manifests as
barely
opposed
any
to
that exists
drain.
drop
drift. The
(gate-to-source voltage),
is less than the threshold voltage,
the voltage
potential
when gate-to-source voltage
Any
drop
potential
across
along the
difference between
the
drain-to-substrate
channel and so
subthreshold
a
current
Vds (drain-to-source voltage)
the carriers
is exponentially
and
V!h (threshold
as
voltage)
BSIM4
shown
by
the
following
for
equation
according to
current
subthreshold
model
K-v,)
fW\
{m-l){vTfe
Mo^o
hub
^
v,,\
VT
l-e
(5)
\LjJ
where
p0 is the carrier mobility,
length
of
the gate,
Subthreshold
the oxide capacitance, W
is the body-effect
m
current
Cox is
with
L
are width
vT is the thermal
coefficient and
increases exponentially
and
increasing
Vgs
or
and
coefficient.
decreasing
Vth-
2.2.2 Gate Leakage
Gate
current
fields
oxide
drive
shown
layer
oxide
through the oxide
This tunneling
tunneling
reduced
along
with
of
electrons
The
current.
and
to
maintain sufficient
This leads to higher
therefore an increase in the probability
layer from the
gives
equation
voltage
supply
strength and reduce short channel effects.
across the
tunneling
thickness has
rise to
for
gate
into the
channel region
a
leakage
tunneling
current
current
electrical
of electrons
gate and vice-versa.
mechanism
called
according BSLM4
gate
model
is
below
-i\
v
v
DD
i
B.
0
To.
v
Iga,e=WLSDEAs
DD
T
(6)
exp
V DD
V
where
LSDe is
electron/hole,
thickness.
thickness
It
the
Ag
can
source-drain-extension
and
be
Bg
seen
decreases. It is
are process
J
length,
related
<pox is the barrier height of
physical
parameters and
that the gate leakage current increases
also
Tox is
exponentially
exponentially dependent on the supply voltage.
8
as
tunneling
the oxide
the oxide
As described in
significant components
chapter
of static
1,
subthreshold
power
remainder of this thesis concentrates on
currents.
and
gate
leakage
dissipation in CMOS
analyzing
and
are
the
Therefore,
the
currents
circuits.
optimizing these two leakage
Chapter 3
3. 1.
Leakage Reduction Techniques
Introduction
The total
power
dissipation. When the
static power only.
dissipation in CMOS
circuit
However,
reduce
Static
thickness and
transistor
doping
terminals,
This thesis
size of
The leakage
capacitances,
logic
have
be
a
parameters
At
choice of
style.
and
the
CPL),
To
currents,
cells such as
and
power
as
channel
level, factors
logic
family
currents
to
dissipation.
of
design
length,
oxide
such as voltages at
can
be
only in
controlled.
static mode
techniques considered are circuit level techniques.
static
understand
single
dissipated in
different levels
at
leakage
a result of
Family
and
following
static power
in total
such
circuit
dissipation is
Therefore, it is necessary
overall savings
controlled.
logic function,
logic
too.
be implemented
process
reduction
short-circuit
chosen
Standard
can
power
technology,
increasing
the transistors and
Low Power Logic
transistor vs. CMOS
(LEAP
level,
profile can
To implement
we
is
of
concentrates on analysis and reduction of
of operation.
chosen
scaling
circuits
techniques
At the device
abstraction.
3.2.
with rapid
the static power dissipation to achieve
power reduction
a sum of active and static power
is in standby mode, the total
from idle
active mode of operation
is
circuits
a number of
vs.
topologies are
dynamic
number of
the impact
circuits.
transistors,
of
rail
such
NAND, NOR, XOR, FA for
the
gate
dual
node
by
the
dissipation,
rail pass-transistor
logic (CMOS+
chosen
as
strongly influenced
single and
transmission
10
Parameters
these parameters on power
logic families: CMOS,
dual
are
available such as pass
and
logic families is
DPL).
compared
for
static and
switching
implementations for
power
(total
logic families
all
power
dissipation). As
are shown
an
example, NAND gate
in Figure 4.
(a)
A
A
^H
S\.
J~~l
>
-i>-o
^
b-TL
_TL
J~L
i^L
o
_r
n
a
-D>-o
(b)
(c)
^H
4n
-r>-o
"H>i
-t>-0
-O-o
-Bja
(d)
(e)
Figure 4. NAND gate implementations in different logic families
(a) CMOS (b) CPL (c) LEAP (d) DPL (e) CMOS+
CMOS
circuits
implement the pull-up
network.
supply
In steady
or ground.
state
have both NMOS
network
while
there always
Thus the
output
is
and
PMOS devices. The PMOS devices
the NMOS
exists a
direct
devices implement the
path
from
always a well-defined
11
pull-down
output to either the power
high
or
low
voltage.
Output
logic levels
independent
are
logic. Figure 4(a)
logic families
transistor
NAND
shows a
use
of
and
transmission gates
power
Single
uses
(NMOS
or
PMOS)
transistors
pass
PMOS for the
they
exhibit
Inverters
are preferred
same width.
from
an
Dual-rail
two MOS
annulling the
ratioed
Single
and
pass
dual
rail
an output
is
(to
avoid
fewer
output
4(b))
rail-to-rail swing.
and
No level
by
a
driving
is
produce
LEAP
on
restoration
12
than that of
added
at
the
shorted).
requiring the
4(d,e))
circuits
must exist
only
Complementary
use of
inverters.
output signals
sizing
the
transistors.
to pass
transistors. Since
in parallel,
needed.
of
thus
under
are equivalent
of pass
connected
circuitry is
to
in complementary form.
the relative
instead
as
output
These
CPL logic families fall
logic families (Figure
device
strong logic T
complementary
and
PMOS devices
smaller
time, there
being
therefore
type of
pull-up PMOS transistor.
provides all signals
to
is
capabilities.
given
inputs
use transmission gates
NMOS
resistance
circuit
any
levels depend
transmission gate
made of
the
structures
transistors.
voltage
at
one
only
cannot pass a
realized
because
networks are required
logic families but
transistor
have full
where
structure
logic (Figure
advantage of
logic
transistor
like
to implement these
pass transistor
However,
is
restoration
the output to achieve better
input to
signals are required
restoration
lines in CMOS logic.
fewer transistors). NMOS
(requiring
However, NMOS devices
This
a multiplexer
4(c))
to PMOS since NMOS ON
Vth drop. Therefore, level
a
are added at
have
one path
to perform the logic operation
this problem.
overcome
must
transistor logic NAND gate (Figure
the
rest of
the source of the
wherein
transistors are connected to input signals as opposed to
rail pass
called ratioless
implemented using CMOS logic. The
gate
transistors
pass
hence this logic is
sizes and
a
output signals
The
next
three sections show the active and
NAND, NOR, XOR
full
and
simulations were performed
Leakage
total
implemented in
using BSLM4 technology
currents were measured
power
3.2.1
adder gates
static power simulation results
using Nanosim
dissipation thus making it
a suitable
the five logic families. All
all
for 45nm feature
model
which provides a
tool
for
probability
leakage
for CPL
of occurring.
Therefore
current over all possible
currents of
NAND, NOR, XOR
and
CMOS
DPL (logic families
average
input
and
with
assumed
leakage
current
combinations.
full
adder gates
is
calculated
Figure 5
for
all
shows
the
of
LEAP
CPL
have
by
an equal
averaging the
the average leakage
logic families. The bars
complementary outputs) have
a
different
color.
NOR
DPL
CPL
CMOS
CMOSP
LEAP
DPL
CMOSP
DPL
CMOSP
Full Adder
0.35
0.08
0.3
0.07
?0.06
<
0.25
3. 0.05
r
0.2
|
0.04
I
0.15
|
0.03
0
detailed distribution
that all inputs
XOR
0.01
[24].
power analysis.
NAND
0.02
size
Leakage Current
While measuring leakage currents, it is
O
for
M
CMOS
CPL
LEAP
O
0
DPL
case of
are applied since
CPL
CMOS
CMOSP
Figure 5. Leakage
In
IzE
0.1
0.05
LEAP
current comparison
CMOS NAND gate, highest leakage
the PMOS transistors leak in
13
parallel.
current occurs when
If
"Is"
is the
inputs (1,1)
subthreshold
leakage
in
current
OFF transistor, then leakage
a stack of single
Least leakage
current occurs
for the
case of
current
inputs due to
(0,0)
for (1,1) inputs is 2%.
stack effect.
Stack
is
effect
a phenomenon where a stack of
two series connected OFF transistors show significantly
less
in
subthreshold current than
explained
in
and
lowest leakage
NAND gate, highest leakage
2*IS
occurs
for
OFF transistor [8]. Stack
of
6*IS
3*IS
of
occurs
occurs
for
effect
of
5*7,
is further
for
occurs
for (0,0)/(l,l) inputs. For DPL
(1,0)/(0,1)
inputs
and
lowest leakage
of
inputs.
(l,l)/(0,0)
CMOS logic
single
3.3. For CPL NAND gate, highest leakage
section
(1,0)/(0,1) inputs
a
gates
have lower
average
leakage
currents compared
to the rest of
the logic families. This is because only CMOS logic gates have transistor stacks resulting
in
reduced
through
leakage
currents
level-restoring
implementing
due to
and
complementary outputs, it
output-driving
logic
gates
draw
circuitry.
equal or
exhibits
currents than
However, in
lower leakage
MUX like implementations. LEAP
and
transistors respectively while CMOS
Leap
and
circuitry.
output-driving
CMOS+ draw higher leakage
and
stack effect.
CPL draw
extra
leakage
Since CPL has two
current
networks
higher leakage than LEAP. DPL
CMOS due to higher
number of
and
transistors
the case of XOR gates, LEAP and CMOS+
currents
than
CMOS+ XOR
logic is
CMOS logic due to their
gates are constructed
constructed
?
hC^El
C^o
bHI
s
HrinP
(b)
Figure 6. Xor implementations
14
from 5
and
from 12 transistors (Figure 6).
->-
(a)
efficient
(a) CMOS (b) CMOS+
8
Average leakage
5. CMOS full
the same
adder
reason
was chosen
currents
for
for full
adder gate
draws least leakage
in different logic families is
current compared to other
that it has transistor stacks present in it.
characterization and optimization of
that leakage currents for CMOS+ is higher that that
number of
on
the
transistors than CMOS+.
number of
CPL
Therefore, leakage
in Figure
logic families due to
Therefore, CMOS logic family
leakage
of
shown
currents.
It
do
be
noted
CPL has higher
even when
currents
must
entirely depend
not
transistors present in the circuit.
3.2.2 Short-Circuit Current
Short-circuit
currents
adder gates are shown
for
all
the logic families in
NAND, NOR, XOR
NOR
0.12
0.07
0.06
0.1
0.08
0<M
fl-ln
0.02
CMOS
DPL
LEAP
CPL
<
0.05
^
0.04
|
0.03
O
0.02
0.01
0
CMOSP
LLLLI
CPL
CMOS
0.16
0.6
0.14
0.5
0.12
3.
0.1
|
0.08
g
0.06
O
f
In
0.04
0.02
0
DPL
LEAP
CPL
CMOS
|
I
currents are obtained
outlined
input
in the
section
signals which
CMOS logic
shows
DPL
CMOSP
from
2.1.2,
0.3
0.2
0.1
CPL
CMOS
CMOSP
:QJ
LEAP
DPL
short-circuit current
depends
on the capacitance of
short-circuit current compared
15
CMOSP
current comparison
a transient analysis over an exhaustive set of
in turn depends
least
0.4
O
Figure 7. Short-circuit
These
LEAP
Full Adder
XOR
?
full
in Figure 7.
NAND
3
and
on
rise
and
inputs. As
fall times
of
the
the gate. As seen from Figure
to the
rest of
7,
the logic families.
In CMOS logic there
state.
The
never exists a
output node
single time.
The
is
the
highest
short-circuit
the swing restoration circuitry
ground simultaneously.
Consider
a
currents
to
pull
up
switching
of rise or
because there
LEAP NAND
to
gate
exists
with
when
both pull-up
and
competing
(1,1)
as
LEAP
signals
voltage and pull
inputs
steady
ground at a
fall times. CPL
to supply
a node
during
ground
voltage or pulled
during
the short period
leakage
trying
from supply to the
is drawn only
short-circuit current
during
path
up to the supply
either pulled
and pull-down paths conduct
show
direct
in
down to
shown
in
Figure 8(a).
B(l)
B(0)
A(l)
B(l)
B(0)
>
_L
_L
a(d
_r~L
J~L
-T~L
x
(b)
(a)
Node X is
at
time,
signals
With
and
This
DPL
LEAP. Since
number of
required
and
results
charge
since
there exists a direct path
sizing, node X can
exhibit
circuits
higher
and ground.
be brought to
short-circuit current
implemented in CMOS+
capacitive nodes
capacitive nodes
short-circuit currents.
16
at node
X
high to low transition then there
is drawn
up these high
in higher
logic high (b) Contention
X to VDD
transistors, they include high
to
makes a
at
node
proper transistor
CMOS+
CPL
in LEAP (a) Node X is
to pull
trying
short-circuit current
ground.
current
logic high. Now if input B
be competing
>*-
X
X(l)
Figure 8. Short-circuit
t
rr
0^-
a
During
would
this period
of
from supply to the
logic low.
than CMOS and lower than
and
DPL logic have higher
in them. Therefore
resulting in higher rise
more
and
time is
fall times.
3.2.3 Switching Current
Switching
gates
(Figure
9)
currents
for
are obtained
all
the logic
families in NAND, NOR, XOR
from transient
and
analysis over an exhaustive set of
NAND
full
adder
inputs.
NOR
0.12
="
0.1
0.15
3.
=
0.1
<J
0.05
|
08
0.06
0.04
O
0.02
0
m
CPL
CMOS
LEAP
CMOSP
DPL
Full Adder
0.25
1.6
1.4
0.2
r 0.15
I
0.1
3
o
0.05
0
llnln
CMOS
CPL
LEAP
DPL
mentioned
discharging
nodes.
in
section
shows
families. The total
represent
length
of
the
of unit
drain
families is
is
0.4
El
CMOS
size.
n*CG.
Since these
power
sum of
dissipation
The sizing
of
inverters
in Figure 10. The total
CMOSP
DPL
drain
due to charging
occurs
proportional
to the
NAND
capacitance of
gates
directly
all
the
CD
and
the
logic
and
Cg
transistor with width and
proportional
transistor with width of
capacitance calculations are
to the width
V is n*CD
and transmission gates used
17
for
and gate capacitances.
capacitances are
capacitance of a
LEAP
Current Comparison
is therefore
is the
CPL
and gate capacitances of a minimum sized
feature
shown
0.6
capacitances of output nodes of
capacitance
the transistor, the drain
capacitance
t
O
0
2.1.1, switching
the
0-8
0.2 4
Switching
of capacitive nodes and
Figure 11
1
I
CMOSP
Figure 9.
As
3.
and gate
in different logic
shown
in Figure 11.
<
Figure 10. Inverter and Transmission
CTotai
gates
=
2(3Cdp)
=
6CDP
+
4CDN
=
2Cdp
+
2(2Cdn)
+
4Cdn
+
sizing
+
6Cgp
6CGp
+
4Cqn
4CGn
+
3h
CTotai
-1?
3
^
=
2CDP
+
4CDN
+
2CDP
+
+
6Cgp
6CGP
+
+
4Cgn
4CGN
^h
_J~L
3
_L
TL
i>-
3
C
."^
=
2(2CDN)
CTotai
3
_TL
=
2C
4Cdp
=
+
2CGP
+
8Cqn
+
+
6CGP
16Cgp
+
+
4CGN
8Cgn
T>-
3
:^>-
C
=
2(3CDP)
Cjotai
-
2C
+
=
2(2CDN)
12Cdp
+
+
6CGP
8Cqn
+
+
4CGN
12Cgp
+
8Cqn
>4>-
-E3-1
Cxotai
=
=
2(3CDP)
6CDp
Figure 11. Capacitance
+
+
2(2CDN)
4CDN
+
+
6CGp
6CGP
+
calculations at output node
18
+
4CGN
4CGN
It is
from the Figure 1 1 that DPL
seen
due to higher
signals.
number of
This is followed
for NAND
and
NOR
transistors.
CPL logic families have high
and
However, they
by CMOS+,
CMOS
and
complementary
output
LEAP logic families. Simulation
results
(Figure 9) follow this
gates
also provide
However, in
pattern.
gate, the pass transistor and transmission gate logic families
currents than
CMOS because
of
the rest of the logic
concentrating
reduction
3.3.
on
family
has
shown
families. Therefore, the
CMOS logic
show
the
XOR
case of
lower switching
their efficient MUX like implementations.
On the whole, CMOS logic
than
capacitive nodes
family
only.
The
better
rest
current
of
dissipation
the thesis
next three sections will
work
focus
on
results
be
will
leakage
techniques for CMOS logic family.
Transistor
Stack
effect
stacks
is
a
phenomenon
where
Isub flowing
through
a
connected transistors reduces when more than one transistor of the stack
example, a
stack of
two
series connected
OFF transistors is
shown
stack
of
is turned
series
off.
For
in Figure 12.
vDD
Figure 12. Voltage developed at intermediate
A
small potential
V, is developed
a result of subthreshold current
potential
developed
results
at the
node
intermediate
flowing
due to
subthreshold current
node
between the two transistors
through the series connected transistors.
in the following:
19
as
This
Reduced Vgs
Reduced Vds
Body effect (higher
The
Vgs, Vds
reduced
voltages and
that the leakage of
shown
leakage in
a single
gate
body
is
stack
in
reduced subthreshold current.
an order of magnitude
a result of stack
effect,
subthreshold
the state of input vector. Subthreshold
on
for
effect result
two-transistor
a
transistor [9]. As
becomes dependent
input NAND
source-to-bulk voltage)
all
the input vectors are
shown
A
B
1
1
0
1
17.4
1
0
6.45
0
0
0.876
Subthreshold leakage
It is
less than the
leakage
current values
current
for
a
two
in the Table 1.
currents
(nA)
17.26
Table 1. Subthreshold leakage for 2-input NAND gate
Many
least
algorithms
have been
subthreshold current.
measure
the leakage
proposed
The
current
2n
there are
only to
combinations of
easiest
for
input
are evaluated
based technique
for
a
large
currents are monitored.
employs
a genetic
information to
near-optimal
A
pursuit of
vectors
was proposed
way
was proposed
20
input
combinations.
the
vectors
leakage
For
larger
that result in
vector
an n-input
feasibility
circuits with
of
inputs
of
and vectors
number of
finding
giving
minimum
in [11]. This technique
improved
vector,
inputs,
minimal
leakage
is to
this algorithm
in [10]. In this technique, leakage
speculate new search points with expected
solution.
the
minimum
limiting
inputs. For
more efficient
algorithm
input
thus
number of random
finding
finding
of
way
all possible
circuits with small number of
random-search
in
a
currents
leakage
vectors which
exploits
historical
performance to
find
Since stacking
can
be
utilized
leakage
by forcing
These
gates.
results
operation to avoid
in
a
stack effect
(by
transistors
stack
affecting the
reduced subthreshold
significantly
adding
be
must
functionality
an extra transistor
ON
switched
of the circuit.
performance.
added
only in
Usually
The
authors
in
[12]
fraction
the devices
of
can
delay
impacting
operating
insertion
control
frequency. The
clock
algorithm
that
in
authors
provides
a
transistors only in non-critical high-leakage
However, introduction
of
3.4.
Dual Threshold CMOS
leakage
DTCMOS
performance of a
can
voltages
current,
while
critical
required,
be
assigned
paths
Not
all
delay
large
since a
approach
the
the circuit.
number of
the chip
power of
to
a
without
leakage
inserting
stack
slack conditions.
transistors is 30%
stack
be
of
the
(DTCMOS)
technique
is
It
non-critical
maintained
delay
for leakage
the transistors in
paths
as
21
so
use of
no
to reduce
additional
transistors are
achieving low leakage
can
be
leakage
low threshold transistors
power reduction even
paths
delay
that higher threshold
due to the
non-critical
of
proposes
performance unaffected while
good
dependence
the
utilizes
threshold voltage.
to transistors in
Moreover, this technique is
operation.
its
performance
the
performance of
satisfying the
and
[16,17]. Unlike MTCMOS technique,
paths
leaving
reduction
transistor on
delay
the
transistors connected to power or ground.
the widths
of
degrading
[13] have developed
structured
algorithm makes an assumption that the size of
sum of
in
of
be forced-stack
the paths are non-critical thus reducing the overall leakage
This
mode
active
proposed that additional series stack transistors must
non-critical paths to maintain the overall
a significant
effect
in the stack) to high
during
transistors results in reduced drive current and therefore
stack
current, this
in
assigned
results.
active mode of
high-threshold
voltages
this may
as
proposed a
result
Breadth-First Search
high Vth. BFS is
optimal
Whether
in the
a node should
used
be
critical
path
(BFS) based
being
changed.
algorithm
for selecting
to explore
every node of the
assigned to a
The
circuit
high threshold depends
in [17]
authors
and
to
assigning
check
on whether
its
its
an
slack.
slack
is
still positive.
>
Critical
o
path
Non-critical
Low Vth
path
Figure 13. Dual
3.5.
Variable Threshold CMOS
High Vth
V, CMOS circuit
(VTCMOS)
VTCMOS technique involves achieving different threshold
biasing
bulk
which was proposed
voltage
to
achieve
in [18]. A body-bias
different threshold
circuit
is
used
voltages as shown
to
voltages
control
the
by
body-
source-to-
in Figure 14.
standby
VBP
!
active
active
V,
standby
Figure 14. Schematic of VTCMOS
In
active
junction is
mode,
no
reverse
body
bias is
applied
biased to increase the
while
circuit
in standby
mode
the
threshold voltage which reduces
22
source-to-body
leakage
current.
Chapter 4
In
this
Subthreshold
an
chapter,
leakage
subthreshold and gate
and
extensive
current
Gate Leakage Characteristics
analysis
is
Different
performed.
two leakage currents such as device terminal voltages,
stack and position of
of
transistors are identified
interaction between the two leakage
technique is proposed that reduces both subthreshold
that affect the
OFF transistors in
Emphasis is laid
Finally
a
and gate
of
characteristics
scenarios
number of
and analyzed.
currents.
level
circuit
of
on
leakage
new
leakage
the
a
study
reduction
currents
based
on
the analysis performed.
Significant Igate
intermediate
studies
flowing
node voltages.
concentrated
However, they may
on
not
be
In
through
such
finding
the circuit may affect
cases,
Isub
minimum
applicable when
leakage
authors examined the
interdependence between
transistors and reverse
Igate in OFF
not
hold true for 45nm
and
Igate for
technology
an
inverter
and
node are shown
than
in NMOS
considered
Isub
32nm technologies. As
in Figure 15.
to that in the ON NMOS transistor.
transistors and can
vectors
and
to
along
reduce
with
PMOS
Igate in
an
and
Igate. However, Igate in PMOS
NMOS devices
23
at
values of
45nm
NMOS transistor is
However, Igate in PMOS
be safely ignored.
This fact does
example, the typical
the OFF
ISUb [21,22].
Isub. In [23], the
transistors was considered negligible.
with equal sized
the
Igate become interdependent. Previous
and
Igate is
ISUb by changing
transistors is
and
Isub
32nm
comparable
relatively less
Igate=2.77
pA
Igate=5.56pA
Isub=5.495
8.49
nA
Lh=19.2
nA
nA
Ieate=1.048nA
(a)
Igate=6
45r
(b)
pA
Igate=12pA
Isub=18.8
lgate=L05
45nm
nA
nA
-=
=0.31 nA
(c)
(d)
32nm
Figure 15. Typical subthreshold and gate leakage
32nm
currents
(a,c) Logic high input (b,d) Logic low input
In
order to
logic blocks (NAND
The NMOS
and
the
interdependence,
NOR)
and a sequential
analyze
and
PMOS devices
are sized
However,
the analysis holds true for
were used
to break down the
and
2)
4. 1.
analysis of
for
representative
block (D
analysis
1)
analysis of
interdependence between
Isub
and
combinational
flip-flop) have been
DC
symmetrical
minimum sized
CMOS
and transient response.
transistors too. The
leakage
chosen.
current
following
steps
considering only Isub
Igate.
4-Input CMOS NAND Leakage Analysis
In this
it into two
section we perform
case studies.
Case study I
Case study II includes Igate to
simulations
leakage
were performed
analysis
evaluates
understand
for
a
leakage
4-input NAND
current
the interdependence
using BSIM4 technology
24
model
gate
by dividing
accounting only for Isub.
between Isub
and
for 45nm feature
Igate. All
size
[24].
4.1.1 Case Study
-1
The behavior
4-input NAND
network of the
in the
stack
from the
can
gate
be
better
visualized
by
considering the
(Figure 16). Let TO, Tl, T2
output node to
combinations are shown
leakage
Isub
of
in Table 2. The
currents and are also categorized
Leakage
ground.
results
in
entries are arranged
based
on
the number
of
Figure 16. Schematic of a 4-input CMOS NAND pull-down
The
1)
following
observations were made
The higher the
This
pattern
reduced
with
Isub
is
compared
internal
to a
negative
node
which
OFF device [25,26]
for
all
possible
increasing
input
order of
the
OFF transistors.
network
more
OFF
and
second case where
is higher than the first
effect.
25
the
T2 is
subthreshold
OFF devices
and
in Figure 17 for input
are switched
is 0.106V. In the
is 0.127V
two stacked
Vgs [27]. Turning OFF
voltage as shown
the first case, TO and Tl
transistors
OFF transistors, the lower the
single
T3 be the transistors
for Isub
a result of stack effect where
the highest
stack's
number of
and
pull-down
leakage
show
is determined
by
current.
significantly
the transistor
transistors in the stack raises the
vectors
voltage at
switched
case and
(0,0,1,1)
the node
and
(0,0,0,1). In
between the two
off, the voltage at the same
hence it has
an
increased
stack
A B C D
Isub (nA)
4 OFF Transistors
0 0 0 0
0.296
3 OFF Transistors
10 0 0
0.4
0 0 0 1
0.413
0 0 10
0.413
0 10 0
0.413
2 OFF Transistors
110 0
0.798
10 0 1
0.809
10 10
0.809
0 0 11
0.879
0 10 1
0.879
0 110
0.879
1 OFF Transistor
1110
10.924
110 1
11.617
10 11
13.285
0 111
35.808
0 OFF Transistors
1111
Table 2. Subthreshold leakage
34.319
currents for a
4-input CMOS NAND
gate at
45nm
node
Vr
PUN
Vout
-
o
-
Vqut
VDD
-
iE TO
0.127 V
0.
HC
Tl
0.0237 V
i
HC
T2
i
C
T3
(b)
(a)
Figure 17. Intermediate
node voltages
based
on number
(a) (0,0,U) (b) (0,0,0,1)
26
of OFF transistors
VDD
2) For
top
of
a
fixed
number of
OFF transistors in the stack, the
transistor in a stack is
ON,
this would
since
cause a
the OFF transistors below the ON transistor. This
single
OFF transistor.
Isub because V^
Isub is
Among
the
across
because
smaller
top
of the
input combinations, the Vdi
drop
because
Vth drop
as
the
of more
position of
ON
the OFF transistor
channel resistive
TO
HP
~J-
0.067
1
1
Tl
HL
3~
HL
mV
T2
0.022
mV
HL
V0ut
-
and reduce
Vds
Vti, drop
all other
cases with a
the highest
input patterns,
(1,1,0,1)
and
(1,1,1,0)
channel resistive
depicted in Figure 18.
as
down in
goes
in
(0,1,1,1) has
Vdd- For
'
a
Isub
stack,
gets smaller
Vqut
-
Vm>T
OUT
Vdd
HI~~J-TO
=
-
V
v DD
1 -| I
0.756 V
0.761 V
0.759 V
HLti
~J- 0.723 V
mV
HLT2
j 0.72:-
"J- 0.007
mV
!HLt3
HLT3
(b)
(c)
Figure 18. Subthreshold leakage dependence
on
\
1HLT2
0-jrT2
~J- 0.008
(a)
it
predominant
transistor. For
Vqd
TO
HL
H-
~}~ 0.016
T3
the
drops.
HLti
0.045
|-
1
mV
top
on whether
PUN
^DD
_
is
based
across
combination
to the
addition
PUN
Vqut
Vtn drop
effect
equals
across the
varies
the OFF transistor is less due to the
across
PUN
0
transistor nearly
the ON transistors in
across
Therefore
these cases, the input
Isub
{- 0.70s V
mV
HL
13
(d)
V,h drop and ON channel resistive drop
(a) (0,1,1,1) (b) (1,0,1,1) (c) (1,1,0,1) (d) (1,1,1,0)
3)
When
(1,1,1,1)
transistors
NMOS
leaking
transistor
(0,1,1,1) inputs
and
in
parallel
and
are considered, the
summing up
leaking. However, leakage
(1,1,1,1) input. This is because ISUb depends
mentioned
previously,
the NMOS
and
while
current
former input has
the later input
for
on the size of
the PMOS
has only
a single
(0,1,1,1) input is higher
than
the transistor (from Eq. 5). As
PMOS transistors
27
all
are
sized
for
symmetrical
transient
and
transistors
DC
response as shown
wherein
in Figure 19. This is
(1,1,1,1) input results in highest leakage
not
true
for
minimum-sized
current.
Vdd
t
HCJ3 Hg^L3~HT
Figure 19. Transisitor sizing for 4-input NAND
4.1.2 Case
Study
-2
In this study, the interdependence between
for
all possible
dependent
1) Igate in
on
input
gate
Isub
and
Igate is
considered.
combinations were obtained and were
following
three factors
which are explained
The leakage
results
found to be predominantly
below.
the top-most transistor:
Late depends strongly
on
Vgs
Vgd
and
voltages
of
the
device
as
shown
inverter in Figure 15.
vDD
vDD
t
PUN
PUN
Vqut
-
Vdd
PDN
PDN
(b)
(a)
current
-
5
'5
Figure 20. Gate
Vqut
Vdd
drawn
by top-most transistor in a stack
(a) Logic high input (b)
28
Logic low input
in the
case of
Maximum Igate is
is VDD.
stack
Using
is
the same principle, reverse
switched
OFF because
stack with two or more
component
2) Isub
Igate:
replaced
cases
by
where
there is
conducting transistor, Igate
0.106V is developed
voltage
at
of
at
least
replaces
the
through
TO
than the dependence
leakage
component
of
one
in the
on
stack.
small
voltage
Igate
This
Tl due to
in Figure 20. For
component
above
a
is the
exhibit
and
below
a
where a potential of
Isub flowing
Igate. But the dependence
through TO.
Igate from its
The
gate
to
Isub
on
Vgs is
stronger
and remains as the
only
in [23].
Vqut
Vdd
of
-
Vdd
0.2 V
i
(b)
Tl reducing
increases the
node voltage
between TO
and
of 0.106 is developed due to
subthreshold
leakage
voltage raised
current
the
rail.
was also observed
-
of
the node to 0.2V. This increase in voltage
(a)
(a)
particular reverse
and
the NMOS device
the top-most transistor
Vgd [23]. Thus, Igate displaces Isub
0.106 V
Figure 21. Gate leakage
of
voltage as shown
for transistor Tl to
voltage at
Vqut
current
Vgd
Isub. This is depicted in Figure 21
and also reduces
Igate
Vgd
when
and
non-conducting transistor
between TO
node
developed is sufficiently
Isub
negative
drawn from the supply
drain. Igate further increases the
reduces
high
Vgs
and
Igate is drawn
OFF transistors, this
dominant leakage
In
input is logic high
observed when
29
(b)
subthreshold
leakage
to 0.2 due to gate leakage
3) Isub
added
to Igate:
Figure 22 illustrates
Tl is
Isub is
to the ground via ON
connected
leakage
the case where
do
currents
not affect
interdependent but simply
transistors, it
This
explained as shown
was also observed
transistors are OFF or
order of
most
are
in Table 3. As
when
in [23]. The leakage
mentioned earlier,
there is stack effect,
ON,
in the top
of
not
drawing Igate
the table. The
transistors switched
from supply
next
seven
for
categories
cases when
Igate dominates ISUb
the table entries. Therefore the first four input
transistors
between TO
and
The two
remains at ground potential.
tabulated in ascending order and also grouped into five different
factors
node
particular node and are therefore not
the voltage at that
add up.
Igate. Since the
added to
two
on
the
or more
have the top
(or drain node) to
combinations
OFF, resulting in Igate flowing from
based
determines the
combinations which
voltage
input
and
results are
gate
node,
have their top-most
the supply voltage to the gate
node.
PUN
Vout
o
HLto,
I
4.58
current
from the
has only
current of
supply.
T2
power supply.
replaces
The only
Isub
current
of
35.78
nA
nA
Figure 22. Subthreshold leakage
1) "No Igate drawn; Isub
Vdd
-
current added
one
input
to
gate
Tl. Therefore, effectively
ground
is the
30
current
combination which
This is because TO has
reaching the
leakage
no gate
leakage
no current
gate current
draws the least
and
the gate
is drawn from the
from the
gate of
T2.
ABCD
Leakage
drawn from supply
current
Igate
not
drawn; lsub
Igate
not
drawn; Stack
1010
0.533
1000
0.873
1100
1.164
1001
1.273
0110
1.276
0010
1.282
1.302
lgate
drawn; Stack
1.544
0001
1.687
2.151
No
stack
lsub dominates
effect;
1110
11.09
1101
11.816
1011
13.546
0111
37.064
1111
34.314
Table 3. Total leakage
draw any
effect
0000
0011
not
replaced
0100
0101
does
effect
1.251
Igate drawn; lsub
2) "No Igate drawn; Stack
(nA)
replaced
currents categorized for
4-input CMOS NAND gate
effect"
has three input
gate current
from supply
transistors, low Isub flows due to
combinations.
voltage.
Because there
transistor
replaced
TO is
has four input
switched
because there is
conducting transistor
as
OFF
at
and
least
described
therefore
one
combinations.
non-conducting transistor
category,
are
Igate is drawn from
two or more
the
OFF
power supply.
above
and
Isub is
below
a
previously.
has three input
Stack
two or more
ON
In these combinations,
draws Igate from the
effect"
4) "Igate drawn;
are
being
stack effect.
replaced"
3) "Igate drawn; ISUb
Transistor TO
power
combinations.
supply to the
OFF transistors, low Isub flows due to
31
gate of
Similar to the
previous
transistor TO. Because there
stack effect.
5) The last
category has
The
inside this category is because
pattern
as explained
Thus,
in
section
values
is
from
scaled
of
the
in
considered
study 1
case
the dominant leakage
Vth drop
a stack plays an
plus
along
and total
non-uniformly for
a
with
ON
values
display
of
role
mechanism.
channel resistive
from
in
deciding
for the
vectors
Isub. Figure 23
leakage
better
important
leakage
also shown that minimum
Igate is
the same when
graph
It is
vectors.
making Isub
drop
4.1.1.
the top-most transistor
leakage
Isub
no stack effect
case of
minimum
ISUb
shows a comparison
study 2. The
case
leakage
are not
between
y-axis of
the
results.
*
35
JO
:
=.
20
:
w
ID
3
*.
0>
4
Total leakage
less
than
subthreshold
.
leakage
|
LS
v
1
0.5
i
0
is
j
1 I
_
\
6-
5-
a-
V
V
V
Input Combinations
n Subthreshold
leakage b Total Leakage
Figure 23. Comparison of subthreshold
It
can
be
seen
less than the
from the
graph
when
case
combination neither
Isub
only Isub is
nor
when
only
Isub is
vector
considered.
Igate is drawn from
the interdependence between
beyond
that for the input
Isub
and
and
Igate, it is
considered.
32
the
total leakage
(1,0,1,0)
currents
the total leakage current
is
explained
earlier, for this input
power supply.
Therefore, by utilizing
As
possible
to
reduce
the total leakage current
4.2.
4-Input CMOS NOR Leakage Analysis
Since
Figure 16,
Igate in PMOS devices is
the total
analysis would
similar
be
leakage
similar
current
to that
dependence between the
as
current)
in NAND
gate
negligible as shown
for
a
NOR
gate
in the
is determined
case of
by
the inverter in
Isub. Therefore, the
the NAND gate in case study I. NOR
of
number of
OFF transistors
Isub (or
and
gate shows
total leakage
(Table 4).
A B C D
Leakage
drawn from supply
current
(nA)
4 OFF Transistors
1111
0.09
3 OFF Transistors
1110
0.143
110 1
0.149
10 11
0.162
0 111
0.184
2 OFF Transistors
110 0
0.324
10 10
0.334
0 110
0.367
10 0 1
0.375
0 10 1
0.408
0.442
0 0 11
1 OFF Transistor
10 0 0
7.696
0 10 0
8.433
0 0 10
10.28
0 0 0 1
36.282
0 OFF Transistors
34.075
0 0 0 0
Table 4. Total leakage
The higher the
case of
number of
stack
ISUb depends
inability
the PMOS device to
above
it. This
effect
is
number of
is ON,
NOR gate,
of
4-input CMOS NOR
OFF transistors, the lower is the
the NAND gate, for a fixed
the first transistor in the
currents for
on whether
since
this
Isub because
OFF transistors,
would cause a
of stack effect.
Isub depends
Vth drop
in
cases with a single
33
the
Vds
of
In
on whether
across
the bottom transistor of the stack is
pass a perfect zero reduces
predominant
gate
ON,
it. For the
since
the
the OFF transistors
OFF transistor
as
depicted in
Figure 24. The input
switched
OFF transistor nearly
due to the
(1,0,0,0)
voltage
combination
inability
and
as
the
VDD. For
equals
as
all other
input
the bottom transistor to pass a
input combinations, Vds
(0,1,0,0)
developed
Therefore,
of
has the highest Isub
(0,0,0,1)
a
result
position of
of
ON
across
channel
the OFF transistor
Vds
combinations
perfect
across
Isllb is lower
In addition, for
zero.
up in
a
of
the transistors below it.
stack,
Isub
gets smaller.
0.3 V
0.999 V
0.999 V
0.999 V
0.281 v
0.284 V
0.999 V
0.999 V
0.238 V
0.24 V
0.246 V
0.999 V
Vn,rr
=
Vn,iT
0
=
the
the OFF transistor is less due to the
resistance
goes
since
VnT
0
=
0
PDN
Figure 24.
lsub dependence
(d)
(c)
(b)
(a)
on state
of bottom transistor in the
stack
(T3)
(a) (1,0,0,0) (b) (0,1,0,0) (c) (0,0,1,0) (d) (0,0,0,1)
4.3.
New Leakage Reduction Technique
The
predicting
categories
For
vectors
subthreshold and gate
a stack of
structured approach
1)
leakage
minimum
considering both
described in NAND
to
finding
leakage
minimum
reduce
NOR
stacks
NMOS transistors, the
The first step is to
thereby inducing
for
and
gate
34
be
analysis can
number
of
used
in
transistors,
currents.
leakage
stack effect.
variable
with
following
Isub by turning
leakage
sequence of steps
demonstrates
a
vectors.
off at
least two transistors
in
the stack
2) With
ON,
more
as
3) With
this
of
leakage
4) With
top
in the stack, the
drawing Igate from the
would avoid
is has
at
least
one
non-conducting
this ON transistor replaces
vectors
more
for
a stack of
than four
as possible while
would avoid
Isub
two, three
as
supply
satisfying the
drawing Igate
stack with a
higher
four transistors
Turning
Therefore,
==
v OUT
vDD
:=
VDD
TO
i
HL
to
o
HL^ti
oHL
Tl
o
HL
ti
0 -\r T2
i
HL
T2
oHI
ignored,
stack
minimum
v
Vqut
i
HC
of
(a)
PMOS transistors,
leakage is
2-transistor
since
obtained when
OFF.
35
transistors
in the
in the
leakage
case of
vectors
(1,1,1,.
.
in
a
..0,1,0).
Vdd
T3
(c)
(b)
vectors for
minimum
ON the top transistors
pattern of
HLto
Figure 25. Minimum leakage
the
in Figure 25.
as explained
o
(a)
so that
PUN
PUN
\'oUT
many
minimum
follow the
it
4.1.2. The
are shown
turn ON as
above conditions.
transistors would
PUN
a
section
from their drains to their gates,
number of
be turned ON
must
transistor above and below
transistors, it is necessary to
be turned
voltage.
described in
and
the top-most transistor in section 4.1.2.
For
transistor must
uppermost
than three transistors in the stack, another transistor
more
such that
Igate
than two transistors
all
(b)
gate
3-transistor
currents
(c) 4-transistor stacks
are
small
enough
to be
the transistors in the stack are turned
A
input
new algorithm
pin-reordering.
be
circuit will
discussed
nearest
For
checked
above.
based
a given
input
Consider
Number
of
inputs
all the
with
input
which makes use of
nodes of
states and then reordered
transistors
a stack of
the
according to the
'A'
connected
4 transistor
and
how they
stacks and
rules
to the transistor
connected to the next transistor and so on.
2, 3
in the
gates
'B'
combinations to
achieve minimum
input vector,
for their logic
to the output and input
shows all
the above analysis is developed
on
Table 5
are reordered
to
leakage.
transistors in
Number
stack
2
(A,B,C,D)
(A,B,C,D)
NMOS Stack
PMOS Stack
(1,0)
(1,0,0)
(1.1.0)
(1,0,0,0)
(1,0,1,0)
(1,1,1,0)
(0,1)
(0,1,1)
(0,0,1)
1
1
3
2
1
4
Reordered
Reordered
ON Transistors
of
2
3
(0,1,1,1)
(0,0,1,1)
(0,0,0,1)
Table 5. Input pin reordering
In this chapter, the
interdependence
was
circuit
It
studied.
transistors, the total leakage
only Isub is
considered
drawn from the supply
applied as an
for
only
stacks
Isub
and
voltage.
input to the NAND
ISUb
was considered.
with
interdependence
Igate
This
A
minimum
Isub
and
stacks
Isub
can
with
be
leakage
Late including
with
two
exploited
was seen when
gate.
standard approach
36
vectors are
to reduce total
the
The total leakage
Igate. Finally,
by
or
their
OFF
more
Igate. Leakage
different
when
Igate. We have demonstrated that the
to
a variable number of transistors was
between
and
is predominantly determined
current
as compared to
interdependence between
Isub
of
that in
shown
was
the NAND gate showed that
analysis of
when
level behavior
a new
minimum
leakage
current was
leakage
by
current
vector was
less than the
predict minimum
developed
leakage
leakage
making
case
vectors
use of
the
reduction algorithm was
developed based
on
achieve minimum
leakage.
the above analysis which makes use of input pin reordering to
37
Chapter 5
The leakage
techniques described
reduction
[7]. The functional descriptions for
circuits
The
Results
following is
a
summary
of what
were
implemented
most of
is presently
the
s298, s400, s444 and s526 are traffic light
s953
is
sl238
Table 6
shows
benchmark
a controller synthesized
is
from
data consisting
of
not
been
provided.
in literature [32].
controllers
high level description
a
randomly inserted flip-flops
a combinational circuit with
statistical
have
circuits
published
ISC AS 89 benchmark
on
the
number
of
gates
in
present
each
circuit.
ISCAS89
Benchmark Circuits
DFF
NAND
AND
OR
NOR
Inverter
s27
3
1
1
4
2
2
s298
14
9
31
19
16
44
s382
21
30
11
34
24
59
s400
21
36
11
34
25
58
S444
21
58
13
34
14
62
S526
21
22
56
35
28
52
s820
5
54
76
66
60
33
s832
5
54
78
66
64
25
s953
29
114
49
112
36
84
S1238
18
125
134
57
112
80
l_
Table 6. Statistics for ISCAS89 benchmark circuits
All
simulations were performed
using BSIM4 technology
using Nanosim [29]
[24]. Leakage
currents
distribution
total power dissipation thus making
Critical
level
of
were measured
paths and critical
static
timing
delays
analysis
model
were measured
tool.
38
it
for 45nm feature
which provides
a suitable tool
using Pathmill
[30]
for
a
size
detailed
power analysis.
which
is
a
transistor
5. 1.
Transistor Stacks
This technique
current.
Input
is done
by
vector
utilizes
the leakage behavior in transistor
to a circuit is first identified that
measuring leakage
However, due
current
to increased number
of
task to test for all input combinations.
tested
for randomly
These
combinations.
control
generated
input
random
all
The
1) Identify
following
reduce
possible
input
vector
Therefore,
circuits with
vectors which
are
form
generated
large
algorithm was used
in
leakage
current.
This
combinations.
inputs in large benchmark circuits, it is
numbers
number of
a
difficult
inputs
a subset of all possible
are
input
using rand() function. Leakage
implementing
which
do
not
lie in
this technique.
critical path
2) Identify minimum leakage
For
to
the least leakage
gives
transistors are then inserted in series to high leakage gates
critical paths.
3)
for
stacks
each
logic
If gate
gate
not
in
in
vector.
the circuit,
critical path, then
If only
one transistor
is OFF, then
1.
If gate
output
=
1, insert NMOS
stack
transistor.
2.
If gate
output
=
0, insert PMOS
stack
transistor.
3.
Reevaluate
a.
If
critical path
critical path
is changed, then
remove
the stack
keep
the stack
transistor.
b.
If
critical path
is
unchanged,
then
transistor.
4)
Reevaluate total leakage
current
to find leakage
39
reduction achieved.
In the first step,
critical paths are
then found
by
qualify for
out
stack
transistor,
parameters
using Pathmill. Minimum leakage
by
the two methods
one of
mentioned earlier.
transistor insertion are identified. These are
critical path and which
stack
identified
have only
critical path
change, then the
along
stack
In step three,
gates
that that
vector
not
lie in
one
transistor switched OFF. After the insertion
with
its
path
transistor is
delay
are reevaluated.
removed.
This
If any
algorithm
that
gates
do
of
is
of a
these two
is partly
adopted
from [13].
The
stack
widths
of
transistors that are added to control leakage
transistors in the
before
currents
ISCAS89
Benchmark
and after
Gates
the
Table 7
stack.
stack
shows
12
s298
s382
the
sum of
the subthreshold and gate
leakage
transistors are added.
Minimum Leakage Vector
Gates Controlled
'sub
s27
to the
are sized equal
Leakage Control
(uA)
'qate
'sub
(uA)
'qate
4
0.47
0.06
0.424
0.06
133
75
3.44
0.55
2.104
0.53
179
116
4.13
0.59
2.807
0.57
s400
184
118
4.24
0.6
2.818
0.58
s444
202
95
4.36
0.66
3.1
0.63
s526
214
102
5.4
0.92
3.285
0.89
S820
294
159
5.35
0.88
2.0
0.82
s832
292
154
5.45
0.9
1.98
0.89
S1238
526
336
10.01
1.43
3.36
1.33
Table 7. Leakage
"Gates
added.
leakage
after
current reduction achieved
by transistor stacks
controlled"
column
"Minimum leakage
represents
achieved
achieved
for
control
number of gates
vector"
column
vectors are applied and
leakage
the
"Leakage
shows
is 68% for the
leakage
26(a)
reduction
stack
transistors
the leakage currents
the percentage reduction
The highest leakage
This leakage
40
shows
the
currents when minimum
column shows
currents.
case of sl238.
the leakage
Control"
transistors are added. Figure
subthreshold
with
current
reduction
technique does not have
any
leakage
substantial effect on gate
phenomenon which
mainly targets the
current
since
subthreshold
100
|
90
C
5
80
1
70
o
60
cc
in
50
S
40
S
30
5
20
o
"
it
basically
leakage
current.
90
80
8
3
a
70
60
50
o
40
>
30
CO
20
HL
0
s27
S298
S382
s400
s444
S526
s820
s832
8
10
S.
o
s1238
S27
S298
S382
S444
S400
(a)
Figure 26. Transistor Stacks
seen
control
(a) Leakage
by
reduction achieved
depends
on
the
reduction
stack.
Table 8
shows
added
to a
Consider
stack of
a stack of
the
not as
high
variations
A
Leakage
as when
with
NMOS transistors
to
flowing
in leakage
three transistors
connected next
ABC
is
current
through the stack.
current
at
the
top
current reductions when a control
with
input A
connected nearest
in
a
such
of
the
transistor
to the output and
and so on.
(nA)
Leakage Control
(nA)
Leakage Reduction
0.809
12.741
1
11.82
0.798
11
reduction
reduction achieved
reduction achieved
.022
in transistor stacks
for input
for input
41
(nA)
36.221
1
leakage
leakage
Therefore, in
the OFF transistor lies
37.1
times that of
much
OFF. The lower the OFF
13.55
in Table 8, leakage
number of
the OFF transistor begin in different positions.
Table 8. Variations in leakage
seen
switched
0 1
0
how
4.1.1, leakage
1
1
S1238
This is because the
on
0.879
0 1
As
between the
transistor depends
the device that is
position of
leakage
s832
transistor inserted
with stack
reduction achieved.
the addition. As discussed in section
cases
input B
no exact correspondence
a control
adding
transistor, the lower is the leakage
is
(b) Percentage of gates
current reduction
from Figure 26 that there is
current existed prior to
s820
S526
(b)
transistors added and percentage leakage
leakage
stack
stack effect
100
o
10
It is
the
uses
vector
vector
"0 1
"1 1 0".
1"
is
more
Therefore,
than three
there is no
between
strict correlation
number of control
leakage
transistors added and
reduction
achieved.
5.2.
DTCMOS
As
mentioned
in the
section
performance of a transistor on
voltages
current,
can
while
be
its threshold
critical paths
is
similar
in
assigned to transistors
delay performance
in
3.4, DTCMOS
is
It
voltage.
non-critical
maintained
due to the
[12,13]. This technique is implemented
to the one implemented in stack
the dependence of
utilizes
delay
proposes
that higher threshold
paths
as
so
use of
by
the
to
reduce
leakage
low threshold transistors
following
algorithm which
effect.
I) Find critical path
For
2)
each
a.
logic
If
gate
gate
not
in the circuit,
in
critical
transistors in the
b.
Reevaluate
then
path,
assign
high-threshold
voltage
to
gate.
critical path
If critical path
is changed, then
reassign
low
threshold voltage to
the transistors.
If critical path
3)
Reevaluate total leakage
Devices in
normal
non-critical paths
threshold voltage.
increased beyond
0.5*VDD
current reduction achieved
number
of
gates
with
is unchanged, then
current
to find
are assigned a
leakage
by
normal
this technique. "Gates
transistors.
42
high Vtn transistor.
savings achieved.
Vth is 0.466
maintain substantial current
high Vth
the
threshold voltage which
This is because the
to
keep
Figure
is 1.06 times the
volts
drive. Table 9
and
shows
is
not
leakage
Controlled"
column represents the
27(a)
shows
percentage
leakage
reduction
Leakage
reduction
that there is
leakage
a
27(b)
up to 42% is
shows
achieved
by
The bar
current reduction achieved.
the
this
between the
correspondence
variations across all
the
Figure
and
achieved
higher is the leakage
method.
number
Gates
the
number of
(a)
and
high Vth
(b)
and
show similar
transistors with high
1
V,h (uA)
.06*Vth
Vth,
Uub
(uA)
'aate
0.066
0.42
'gate
0.065
2.5
0.53
12
5
133
108
3.54
0.55
s382
179
164
4.343
0.59
2.76
0.57
s400
184
167
4.364
0.6
2.848
0.58
s444
202
146
4.46
0.65
3.047
0.62
s526
214
176
5.5
0.92
3.819
0.9
s820
294
197
5.59
0.95
3.9
0.93
s832
292
250
5.7
0.97
3.66
0.95
S1238
526
480
10.42
5.87
3.66
3.6
current reduction achieved
90
80
80
70
70
60
60
50
50
40
40
30
30
20
20
by
DTCMOS
10
a
0
S298
S382
s400
S444
s526
s820
S832
s27
S1238
S298
S382
Figure 27. DTCMOS
S444
S400
S526
S820
S832
S1238
(b)
(a)
(a) Leakage
current reduction
(b) Percentage
of transistors
with
high
V,h
VTCMOS
VTCMOS is based
on
the
transistors to increase the threshold
0.1
with
s27
100
current.
from Figure 27
s298
90
5.3.
seen
'sub
0.5
100
S27
be
of transistors
Gates Controlled
Table 9. Leakage
0
can
controlled.
reduction achieved.
ISCAS89 Benchmark
10
It
of transistors
from Figure
graphs
benchmarks. The higher
the
percentage
Table 10
shows the
leakage
principle
of
voltage and
currents
volts.
43
for
applying
a
reverse
thereby reducing
increasing
reverse
body
bias to the
subthreshold
leakage
bias in
steps of
body
ISCAS89 Benchmark
Body
Gates
0
0.36
0.29
2.653
2.16
2.16
4.343
3.47
3
2.38
2.38
184
4.364
3.476
3.035
2.4
2.4
202
4.46
3.612
3.153
2.56
2.56
214
5.5
4.53
4.02
3.36
3.36
s820
294
5.59
4.38
3.85
3.18
3.18
s953
424
8.98
7.21
6.43
5.42
5.42
S1238
526
10.42
8.17
7.17
5.88
5.88
s382
179
s400
s444
s526
variation
current reduces almost
applying further
Leakage
linearly
reverse
0.5
of subthreshold
the
bias
Body
Figure 28. Leakage
Reductions
as
high
43%
as
for
can
be
leakage
reaches
VTCMOS
with
body
does
current
-0.3
body
By
saturates.
Bias
current as a function
the
all
benchmark
achieved
by
this
of body bias
circuits
is
shown
method.
70
60
50
40
30
20
10
0
s298
volts.
volts.
80
s27
-0.3
decrease but
not
90
U
bias. The leakage
bias up to
100
T3
.29
-0.2
-0.3
reduction
by
applied reverse
leakage
the
current plateaus when reverse
current
L3.54
current reduction achieved
with
bias,
-0.4
Leakage
-0.4
0.4
12
133
the
shows
-0.3
2.934
s27
s298
Table 10. Leakage
Figure 28
-0.1
Bias
-0.2
s382
Figure 29. Leakage
s400
s444
s526
s820
current reduction achieved
44
s953
by
S1238
VTCMOS
is Figure 29.
5.4.
New Leakage Reduction Technique
The techniques implemented
new
leakage
is based
technique reduces both
reduction
input-pin reordering
on
circuit, the input nodes
Depending
on
far only target
so
section
4.3. For
the gates are traced and
of all
the inputs present at
a particular
leakage
subthreshold and gate
discussed in
as
subthreshold
leakage
a given
leakage
currents
before
gate, reordering is done based
values are averaged over all applied
input
leakage
Uub
Optimized lsub
'qate
Optimized lgate
s27
0.49
0.457
0.066
0.061
s298
3.54
3.2
0.55
0.46
s344
4.14
3.8
0.5
0.47
0.53
s382
4.34
4.07
0.59
s400
13.05
12.78
0.6
0.54
S444
4.5
4.23
0.65
0.59
s526
5.49
5.03
0.92
0.76
s820
8.98
7.91
1.26
1.12
s832
10.42
8.88
1.48
1.168
s953
8.98
7.91
1.26
1.12
S1238
10.42
8.88
1.48
1.168
to 26%. The
structure
properties
gate
the leakage
currents can
reduction
be
the
leakage
in the
currents.
reduction
or
any
earlier
before
in
because,
process
and after
state.
Table 5
current
leakage
not
this
parameters.
as
this technique
as
Subthreshold
currents.
currents can
high
in the
be
does
It merely
exploits
provides a
between
way to
reduced
other
technique
the interdependence
45
input pin reordering
for both leakage
while gate
achieved
circuit such as
However,
currents
savings
up to 20%
described
circuits
present
current
reduced
percentage
techniques
of
The leakage
pin reordering.
to a
subthreshold
ISCAS89 Benchmark
shows
on
It
combinations.
Table 11. Subthreshold and gate leakage
Figure 30
input
and after
vector
for their logic
checked
The
currents.
input
to reduce both subthreshold and gate leakage currents. Table 11 shows the
and gate
current.
not
up
leakage
modify the
the inherent
subthreshold and
reduce gate
leakage
currents
in
addition to
technique is that it
DTCMOS
VTCMOS
can
only subthreshold leakage
be
combined with
VTCMOS. Section 5.5
and
combined with
input
currents.
existing leakage
gives
Another
reduction
the leakage
advantage of
techniques such as
for DTCMOS
results
this
and
pin reordering.
50
45
40
35
30
a Subthreshold
25
Gate Leakage
20
15
10
5
iR
0
# / / # / / & # f f
Figure 30. Leakage
The
above
terms of reducing
this leakage
circuit
in standby
all
vector
necessary
pin
summarizes all
mode
must
demonstrate the
leakage
in the
circuit
in turn dependent
supplied
when minimum
needed
For
each gate
a.
in the
Identify
depends
on
of
However, for
vector
that
this technique in
the
is
application of
supplied to the
leakage
logic
their input
the supplied input vector.
Therefore,
results
vector
is
the
be decided to
can
be
achieved
realize
the
if input
pin
The
following
reduction
technique.
applied.
to implement this leakage
algorithm
vector
circuit
transistor stacks with
greater
46
pin
states at
on
mode must
Best
phase.
I) Identify and apply minimum leakage
2)
effectiveness
currents.
in the standby
reordering in design
the steps
reordering
be known beforehand. This is because the input
present
states are
to be
reordering is done
by Input pin
technique in VLSI circuits, the input
the gates
These logic
the input
given to
subthreshold and gate
reduction
reordering for
nodes.
data is
current reduction achieved
^
than or equal to two transistors.
3)
of transistors in the
b.
Find
c.
Find logic
d.
Perform input pin reordering based
Reevaluate
number
stack
of all input ports
states
subthreshold
and
Table 5
on
leakage
gate
to
currents
find leakage
current
reduction achieved
Minimum leakage
at
vector
is found in
a similar
in "Stack Effect". The logic
as
way
the input nodes of all the gates are found using Nanosim. Figure 3 1
realized
by
reduced
this method. These savings
leakage
current
recorded over all possible
and
represent
maximum
input
the
leakage
percentage
current
shows
the
states
savings
difference between the
(the highest leakage
current
vectors).
50
g
45
I
35
<o
25
S 40
|
30
S1
20
I
15
a 10
"
IT
5
a.
$
/ f*
jy
Figure 31. Total leakage
This
method shows savings
leakage
minimum
circuit can
overhead
5.5.
be
vectors
modified
on various
a part of
to force
&~
,&
r
reduction achieved
up to 26%
to
& 4?
& &
&~
*#
F F ?
the
minimum
by
input pin reordering
benchmark
circuit which
leakage
j?
circuits.
For
is idle, latches
vectors with
very little
application of
present
area and
in the
delay
[28].
Input-pin reordering
Among
the
techniques
capability of reducing
both
combined with
described
above,
subthreshold and gate
47
DTCMOS/VTCMOS
only input
leakage
pin
reordering has the
currents as opposed
to only
subthreshold leakage
Therefore,
current.
reduction techniques should result
with
gate
leakage
leakage
instance, in
this
stack
technique
combined
a
an
wherein
or
the
on
pin
VTCMOS
combined
subthreshold
reordering
circuit
only be
can
is
not
reordering.
since
the
with
leakage
modified
reduction
along
with
other
structurally.
For
therefore
stacks and
Input
pin
reordering
is
not
modified
circuit
leakage
other
combined
to the bottom of the
are added
restraint
DTCMOS
improved
pin
effect, transistors
imposes
with
Input
reduction.
techniques
reduction
in
this technique
be
can
in these
techniques.
To
combine
implemented first in
applied
pin
a similar
reordering
way
to the circuit and input
DTCMOS
5.4
input
or
VTCMOS leakage
respectively.
reordering is
Figure 32
pin
described in
section
reordering is done
reduction
shows
combined with
as
DTCMOS/VTCMOS,
with
the
the
former
5.5. Minimum leakage
accordingly.
vector
This is followed
techniques as implemented in sections
leakage
be
must
current reduction achieved when
5.3
input
is
by
and
pin
DTCMOS.
100
90
g
80
g
I
60
<i>
S*
50
5
30
? Subthreshold
Gate Leakage
40
S
20
q!
10
10
0
Figure 32. Input pin reordering
This
method shows subthreshold
benchmark
DTCMOS
circuit.
was
accompanied
by
The highest
about
gate
leakage
combined with
reduction of
subthreshold
leakage
reduction
up to 52% for the
leakage
42%. This improvement in
DTCMOS
reduction
subthreshold
case of si 23 8
achieved
leakage
by
using
reduction
is
too. The gate leakage reductions achieved are the
48
in input-pin reordering
same as
currents.
s832.
Therefore,
Figure 33
reordering is
since
the highest gate
shows
DTCMOS does
leakage
the percentage
not
have any
effect on gate
leakage
26% for the
case of
reduction remains at
leakage
reduction
achieved
when
input
pin
VTCMOS.
combined with
100
c
o
o
a
a
rr
90
80
70
60
4)
o>
ra
50
c
30
o
o
? Subthreshold
Gate Leakage
40
t
20
a.
10
0
Figure 33. Input pin reordering
As
seen
from the figure, the highest
the case of s820 benchmark
using VTCMOS
alone
leakage
technique
reduction
accompanied
achieved are
on gate
by
the
leakage
26% for the
gate
circuit.
was
currents.
subthreshold
Highest
shows
leakage
subthreshold
43%. Therefore,
leakage
same as
combined with
similar
improvement in
reduction
too.
Also,
in input-pin reordering
Therefore,
49
reduction achieved
leakage
to the
the gate
since
leakage
leakage
VTCMOS does
leakage
is 53% for
reduction achieved
by
technique, this
previous
subthreshold
the highest gate
case of s832.
VTCMOS
reduction and
is
current reductions
not
have any
effect
reduction again remains at
5.6.
Comparison
of
The highest leakage
5
chapter
leakage
3)VTCMOS 4)Input
Input
pin
reductions
achieved
from
graphically displayed in Figure 34
are
different
represent
Leakage Reduction Techniques
pin
reordering 4) Input
combined with
reordering
pin
the
where
techniques:
reduction
the techniques described
all
x-axis
index
in
numbers
1) Stack Effect 2) DTCMOS
combined with
reordering
DTCMOS
5)
VTCMOS.
100
c
o
3
80
3
|
CD
O)
ra
60
1
-
2
-
3
j
40
c
CO
4
20
-
6
1
2
3
4
5
-
effect
VTCMOS
-
-
5
a.
Stack
DTCMOS
Pin reordering
Pin reordering & DTCMOS
Pin reordering & VTCMOS
6
Leakage Reduction Technique
Figure 34. Leakage
As
seen
from the figure,
the
graph represents subthreshold
are also accompanied
and
6, 6
shows
combined with
both
by
stack effect results
a
reduction
and
gate
26%
leakage
out
in the highest leakage
reduction only.
reduction
subthreshold
leakage
to
be the
currents.
reduction
the techniques
in
Techniques
gate
leakage
reduction.
technique should
as
currents.
4, 5
6
Among 4,
5
pin
reordering
technique for reducing
the gate
be the
However,
and
such as
Therefore,
most effective
Specially,
reduction.
leakage
most effective
currents
technique
generations.
also worthwhile
techniques.
Since
to low leakage gates, this
of the control
of
VTCMOS has turned
increase rapidly, this leakage
It is
leakage
highest
the highest
subthreshold
for upcoming
reduction achieved for all
to discuss the disadvantages associated with other
stack effect
incurs
a
is based
discernable
on
inserting
area overhead.
additional control
leakage
transistors
Moreover, choosing
the size
transistors in not a trivial task. One must always check to see that there is
50
no
impact due to insertion
delay
critical paths.
become
If the
size
is
reduced
currents since subthreshold
There is
the
Sizing
critical paths.
require
reduction
no
period.
in both idle
Input
of
additional
the
pin
multiple
current
disadvantages
in
the
and
It
point, then leakage
on
sizing
fabrication
also
is incurred
of
the
process
technique
does
not
VTCMOS leakage
and unlike
latches
in the
leakage
is
thus
good
incur any
reduction
DTCMOS,
circuit.
vectors can
Therefore,
be
transistors.
multiple
with
prolonging
for leakage
delay
techniques
do
no need of
to the circuit
incurred is
Vth
chip
power
or area overhead.
DTCMOS. Unlike
there is
applied
area overhead
51
non-
in high leakage
control
the case of input reordering, if a portion of a
minimum
in
control paths will
can result
transistors. Circuits
Vth
associated with stack effect and
idle state, then
present
steps
when placed
proportional to the width of a transistor.
in literature
uses multiple
and active mode.
Vth devices. In
is
However, DTCMOS
reordering
area overhead
a certain
transistors too large
control
no standard approach proposed
manufacturing
any
these control transistors even
beyond
leakage
Dual threshold CMOS
devices
of
stack
effect,
incorporating
large
by
not exhibit
circuit
is in
modifying the
quite negligible.
Chapter 6
Conclusion
With scaling feature sizes, leakage
becoming
the dominant
size, gate leakage
leakage
Very
reduction
few
techniques do
analysis on
total power
techniques
not consider gate
45nm
significantly
and
dissipation. Specially,
at sub-65nm
feature
subthreshold
leakage
and
Considering
32nm
the
current
were proposed
models shows
that this
power
in the
devices,
presence of series
showed
the least
case of
switching
structure.
power
CMOS logic
superior power
In the
in terms
short-circuit power
of
dissipation,
family
dissipation
next
and
step,
exhibited
induce the
transistors which
only in XOR
superior results
family
dissipation
a
new
leakage
were performed
by
in the
full
currents was proposed.
for
such as
CMOS,
and active
the least leakage currents
due to the
analyzed
stack effect.
since
for the
CMOS
rest of
to other logic
leakage
subthreshold and gate
simulations
1)
The
static
were
CMOS logic
family
circuits are ratioless.
adder gates as a result of
results compared
analysis
Our
also
In the
pass-transistor and pass-transmission gates showed
was chosen
running
current.
reduction
their efficient
MUX like
the thesis as it showed overall
families.
currents were studied and analyzed
their circuit level behavior. The interdependence between the two
currents was studied
the
be ignored.
Different logic families
gate circuits
and pass-transmission
dissipations. CMOS logic
process.
of
are switched off.
component cannot
leakage in NMOS
gate
steps were performed
pass-transistor
Most
in literature. However these
in NMOS devices that
technique that reduces both subthreshold and gate leakage
following
current.
techniques proposed are devoted towards subthreshold leakage
reduction
is
increasing
faster than
current grows
leakage
gate
part of
is
power
on
analysis of
52
basic CMOS
leakage
current
gates.
The
leakage
following
considering only Isub
steps
and
2)
analysis of interdependence between
1) For
analysis are:
drawn from the
for the
vectors
the case of
ISUb
case of
current
two
Igate. The
and
current
observations made
the same when
are not
found that
was
categories
Igate is
were
leakage
Igate
can
be
on
observations
lead to the inference that the interdependence between Isub
exploited to reduce
and
input
reduces
pin reordering.
both
The
prevailing
This
leakage
implementing
them
technique did not
on
technique
such
as
up to the
current, it had the capability
of
stack
DTCMOS
and
This
account
for
leakage
reduction and
gate
VTCMOS
work can
gate
be
leakage
extended
currents
26%
by
developing
vectors.
and
Igate
input
These
be
can
vectors
that
a new algorithm
effect,
gate
in terms
leakage
and
the
best
leakage
modifying the
currents.
and
new
of
results
the
of
VTCMOS
leakage
reducing
by
reduction
subthreshold
Therefore this technique
results were promising.
by
The
new
achieving up to 53%
reduction.
new
in PMOS devices. This
53
DTCMOS
While the
most
against
compared
circuits.
technique combined with VTCMOS showed the
subthreshold
was
other techniques
reducing
to reduce total
application of appropriate
behind
only Isub is
currents.
ISCAS89 benchmark
measure
was combined with
leakage
reduction
techniques
reduction
by
the motivation
was
subthreshold and gate
new
for predicting low leakage input
the total leakage current
Isub 3) In
the interdependence
and
which are useful
current
is applied, the
when
between Isub
Igate
with
vector
exploited
identified based
our
Minimum leakage
along
is less than
voltage
and
by Igate 2)
considered
when minimum
drawn from the supply
4) Different
from
OFF transistors, the total leakage
or more
Thus interdependence between Isub
considered.
key
supply is predominantly determined
power
NAND gate, it
a
total leakage
leakage
a stack with
ISUb
leakage
reduction algorithm
component was
to
ignored in this
thesis
as
it
was
found
negligible compared
However,
at
written to
implement the
from
lower feature sizes, this
standard cells.
It
new
must
be
leakage
to gate
component
leakage
to work on a
54
in NMOS devices.
may increase. Furthermore, the
reduction algorithm
modified
currents
fully
only
works
ASIC design.
for
circuits
code
built
Bibliography
[1]
V. De, S. Borkar,
Performance",
"Technology
and
Design Challenges for Low Power
In Proceedings of Low Power Electronics
and
and
High
Design, 1999,
pp.
163-168.
[2]
S. Tyagi, "A 130nm
generation
Vth
6 layers
transistors
and
logic technology
Cu interconnects", In Proceedings of IEDM
of
Technical Digest International, Dec, 2000,
[3]
K.
Roy
2005,
[4]
K.
and
ch.
1,
pp.
567-570.
K. S. Yeo, Low-Voltage, Low-Power VLSI Subsystems, Mc-Graw Hill,
pp.
2-3.
Roy, S. Mukhopadhyay
Mechanisms
and
and
H.
Mahmoodi-Meimand, "Leakage Current
Leakage Reduction Techniques in Deep-Submicrometer CMOS
Circuits", In Proceedings of the IEEE, Feb, 2003,
[5]
Y. Taur,
70nm transistors, Dual
featuring
and
pp.
305-327.
T. H. Ning, Fundamentals of Modern VLSI Devices, New York,
Cambridge Univ. Press, 1998.
[6]
S. Mukhopadhyay, A. Raychowdhury,
and
K. Roy, "Accurate Estimation
Leakage Current in Scaled CMOS Logic Circuits Based
on
of
Total
Compact Current
Modeling", In Proceedings of Design Automation Conference, June, 2003,
pp. 169-
174.
[7]
ISCAS89 Benchmark
[8]
Z. Chen, M.
CMOS
Circuits,
Johnson, L. Wei
circuits
considering
http://www.fm.vslib.cz/~kes/asic/iscas/
and
K. Roy, "Estimation
accurate
of International Symposium
on
modeling
of
of transistor
Low Power Electronics
244.
55
standby leakage
power
in
stacks", In Proceedings
and
Design, 1998,
pp. 239-
[9]
Y. Ye, S. Borkar
and
V. De, "New technique for standby leakage
performance circuits",
pp.
In Dog. Tech. Papers Symposium
S.
Mukhopadhyay,
Mechanisms
and
high-
VLSI Circuits, 1998.
of the
Chen, M. Johnson, L. Wei,
CMOS
circuits
and
H.
Mahmoodi-Meimand,
"Leakage
Current
Leakage Reduction Techniques in Deep-Submicrometer CMOS
Circuits", In Proceedings
Z.
in
40-41.
[10] K, Roy,
[11]
on
reduction
considering
IEEE, Feb, 2003,
and
on
305-327.
K. Roy, "Estimation
accurate
of International Symposium
pp.
modeling
of
of
standby leakage
power
in
transistor stacks", In Proceedings
Low Power Electronics
and
Design, 1998,
pp. 239-
244.
[12] S. Narendra, S. Borkar, V. De, D.Antonidis, A. Chandrakasan, "Scaling
Effect
and
Use
D.
and
Design, August, 2001,
pp.
Somasekhar, K. Roy, M. C. Johnson, "Leakage Control
VLSI Systems,
Feb, 2002,
pp.
with
Efficient
High-Speed Digital Circuit
Technology
with
A.
Yamada, "1-V
pp.
847-854.
Chandrakasan, D. Antoiadis, "Transitor-Sizing Issues
Multi-Threshold
Automation
J.
Multithreshold-voltage
CMOS", In IEEE Journal of Solid-State Circuits, August, 1995,
[15] J. Kao,
CMOS
on
1-5.
[14] S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu,
Supply
on
195-200.
Transistor Stacks in Single Threshold CMOS", In IEEE Transactions
of
Power
Stack
its Application for Leakage Reduction", In International Symposium
Low Power Electronics
[13] L. Chiou,
of
Technology",
Conference, June, 1997,
pp.
56
In
Proceedings
409-414.
and
34th
of the
Tool for
Design
[16]
P.
Pant, V. K. De, A. Chatterjee, "Simultaneous Power Supply, Threshold Voltage
and
Transistor Size Optimization for Low-Power Operation
IEEE
[17]
transactions on VLSI
Systems, Dec, 1998,
L. Wei, Z. Chen, K. Roy, M. C.
Optimization
Applications,"
538-545.
for
circuits
In IEEE Transactions
CMOS Circuits", In
Johnson, Y. Ye, V. K. De, "Design
Dual-Threshold
of
pp.
of
on
Low-Voltage
VLSI Systems, March, 1999,
Low-Power
pp.
16-24.
[18] T. Kuroda, "A 0.9V 150MHz lOmW 4mm 2-D Discrete Cosine Transform
processor with variable
Circuits, Nov, 1996,
[19] Y. Oowaki, "A
pp.
1770-1779.
Circuit Design
State Circuits Conference, Feb, 1998,
A.
pp.
Raychowdhury,
with
Substrate-over-Biasing",
and
Circuits
[21]
and
In IEEE Transactions
Systems, March, 2005,
Z. Chen, M. Johnson, L. Wei,
in CMOS
Circuits
and
Considering
International Symposium
on
pp.
In
Solid-
88-89.
K. Roy, "Accurate Estimation
Leakage in Nanometer-Scale Bulk CMOS Circuits Based
Doping Profile",
core
threshold voltage scheme", In IEEE Journal
of Solid-State
sub-O.lum
[20] S. Mukhopadhyay,
and
on
on
Device
of
Total
Geometry
and
Computer-Aided Design of Integrated
363-381.
K. Roy, "Estimation
of
Accurate
of
Modeling
Standby
Leakage Power
Transistor
Low Power Design Electronics
and
Stacks", In
Design, 1998,
pp.
239-244.
[22] M. C. Johnson, D. Somasekhar,
and
K. Roy, "Models
leakage in CMOS circuits", In IEEE Transactions
Integrated Circuits
and
Systems, June 1999,
57
pp.
and algorithms
on
for bounds
on
Computer-Aided Design of
714-725.
[23]
D. Lee, D. Blaauw,
D. Sylvester, "Gate Oxide Leakage Current Analysis
and
Reduction for VLSI Circuits", In IEEE Transactions
pp.
on
VLSI
card
45nm BSIM4
model
for bulk CMOS.
[25] Y. Ye, S. Borkar,
high-performance
Z.
Systems, Feb, 2004,
155-166.
[24] Predictive Technology Model, http://www.eas.asu.edu/~ptm
[26]
and
and
V. De, "A
new
technique for standby leakage
reduction
in
circuits,"
In Symposium
Chen, M. Johnson, L. Wei,
in CMOS Circuits
and
Considering
International Symposium
on
VLSI Circuits, June, 1998.
on
K. Roy,"Estimation
Accurate
Modeling
Low Power Electronics
Standby
of
of
and
Leakage Power
Transistor Stacks", In
Design, 1998,
pp. 239-
244.
[27] A. Agarwal, S. Mukhopadhyay,
"Leakage Power Analysis
March, 2006,
[28] J. P. Halter
pp.
and
and
A.
Raychowdhury, C. H. Kim,
and
K.
Roy,
Reduction for Nanaoscale Circuits", In IEEE, Micro,
68-80.
F. N. Najim, "A Gate-Level Leakage Power Reduction Method for
Ultra-Low-Power CMOS Circuits", In Proceedings of the IEEE Custom Integrated
Circuits Conference, May, 1997,
pp.
475-478.
[29] Synopsys Nanosim
http://www.svnopsys.com/products/mixedsignal/nanosim/nanosim.html
[30]
Synopsys Pathmill http://www.svnopsys.com/products/analvsis/pathmill ds.html
[31]
D.
Helms,
"Leakage
Proceedings of
electronics
Power
Modeling,
Estimation
and
Optimization",
MARLOW (Marketplace for dissemination of low
design), 2005.
58
In
power micro
[32]
F. Brglez, D. Bryan
and
K. Kozminski, "Combinational Profiles
Benchmark Circuits", In IEEE Symposium
1929-1934.
59
on
Circuits
and
of
Sequential
Systems, May, 1989,
pp.